leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ath9k: Cleanup TX power calculation for 4K chips

Browse Source 
Write CCK power-per-rate array always and report
correct TX power to regulatory.

Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith 2009-08-07 09:45:30 +05:30 committed by John W. Linville
parent 7f63845f2a
commit bf466fb67c
1 changed files with 34 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/net/wireless/ath/ath9k/eeprom_4k.c
View File

@ -737,11 +737,23 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
ratesArray[i] = AR5416_MAX_RATE_POWER; ratesArray[i] = AR5416_MAX_RATE_POWER;
} }
/* Update regulatory */
i = rate6mb;
if (IS_CHAN_HT40(chan))
i = rateHt40_0;
else if (IS_CHAN_HT20(chan))
i = rateHt20_0;
ah->regulatory.max_power_level = ratesArray[i];
if (AR_SREV_9280_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) {
for (i = 0; i < Ar5416RateSize; i++) for (i = 0; i < Ar5416RateSize; i++)
ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
} }
/* OFDM power per rate */
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
ATH9K_POW_SM(ratesArray[rate18mb], 24) ATH9K_POW_SM(ratesArray[rate18mb], 24)
| ATH9K_POW_SM(ratesArray[rate12mb], 16) | ATH9K_POW_SM(ratesArray[rate12mb], 16)
@ -753,7 +765,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
| ATH9K_POW_SM(ratesArray[rate36mb], 8) | ATH9K_POW_SM(ratesArray[rate36mb], 8)
| ATH9K_POW_SM(ratesArray[rate24mb], 0)); | ATH9K_POW_SM(ratesArray[rate24mb], 0));
if (IS_CHAN_2GHZ(chan)) { /* CCK power per rate */
REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
ATH9K_POW_SM(ratesArray[rate2s], 24) ATH9K_POW_SM(ratesArray[rate2s], 24)
| ATH9K_POW_SM(ratesArray[rate2l], 16) | ATH9K_POW_SM(ratesArray[rate2l], 16)
@ -764,8 +776,8 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
| ATH9K_POW_SM(ratesArray[rate11l], 16) | ATH9K_POW_SM(ratesArray[rate11l], 16)
| ATH9K_POW_SM(ratesArray[rate5_5s], 8) | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
| ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
}
/* HT20 power per rate */
REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
ATH9K_POW_SM(ratesArray[rateHt20_3], 24) ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
| ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
@ -777,6 +789,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
| ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
| ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
/* HT40 power per rate */
if (IS_CHAN_HT40(chan)) { if (IS_CHAN_HT40(chan)) {
REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
ATH9K_POW_SM(ratesArray[rateHt40_3] + ATH9K_POW_SM(ratesArray[rateHt40_3] +
@ -796,27 +809,12 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
ht40PowerIncForPdadc, 8) ht40PowerIncForPdadc, 8)
| ATH9K_POW_SM(ratesArray[rateHt40_4] + | ATH9K_POW_SM(ratesArray[rateHt40_4] +
ht40PowerIncForPdadc, 0)); ht40PowerIncForPdadc, 0));
REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
| ATH9K_POW_SM(ratesArray[rateExtCck], 16) | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
| ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
| ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
} }
i = rate6mb;
if (IS_CHAN_HT40(chan))
i = rateHt40_0;
else if (IS_CHAN_HT20(chan))
i = rateHt20_0;
if (AR_SREV_9280_10_OR_LATER(ah))
ah->regulatory.max_power_level =
ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
else
ah->regulatory.max_power_level = ratesArray[i];
} }
static void ath9k_hw_4k_set_addac(struct ath_hw *ah, static void ath9k_hw_4k_set_addac(struct ath_hw *ah,