forked from Minki/linux
drm/amdgpu: refine code for VCE2.0 and related dpm code.
v2: clean up vce cg function. use sw cg when vce stoped. 1. implement vce_stop function. 2. not start vce when hw_init. 3. refine vce cg/pg code. 4. delete bypass mode. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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28ed5504ab
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@ -1142,13 +1142,23 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
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/* XXX select vce level based on ring/task */
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/* XXX select vce level based on ring/task */
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adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
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adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
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mutex_unlock(&adev->pm.mutex);
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mutex_unlock(&adev->pm.mutex);
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amdgpu_pm_compute_clocks(adev);
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amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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} else {
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} else {
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amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_GATE);
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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mutex_lock(&adev->pm.mutex);
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mutex_lock(&adev->pm.mutex);
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adev->pm.dpm.vce_active = false;
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adev->pm.dpm.vce_active = false;
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mutex_unlock(&adev->pm.mutex);
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mutex_unlock(&adev->pm.mutex);
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}
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amdgpu_pm_compute_clocks(adev);
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amdgpu_pm_compute_clocks(adev);
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}
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}
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}
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}
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}
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void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
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void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
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@ -4256,12 +4256,6 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev,
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if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
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if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
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if (amdgpu_new_state->evclk) {
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if (amdgpu_new_state->evclk) {
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/* turn the clocks on when encoding */
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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if (ret)
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return ret;
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pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
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pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
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tmp = RREG32_SMC(ixDPM_TABLE_475);
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tmp = RREG32_SMC(ixDPM_TABLE_475);
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tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
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tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
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@ -4273,9 +4267,6 @@ static int ci_update_vce_dpm(struct amdgpu_device *adev,
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ret = ci_enable_vce_dpm(adev, false);
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ret = ci_enable_vce_dpm(adev, false);
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if (ret)
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if (ret)
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return ret;
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return ret;
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/* turn the clocks off when not encoding */
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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}
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}
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}
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}
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return ret;
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return ret;
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@ -1550,11 +1550,6 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
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if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
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if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
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kv_dpm_powergate_vce(adev, false);
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kv_dpm_powergate_vce(adev, false);
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/* turn the clocks on when encoding */
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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if (ret)
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return ret;
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if (pi->caps_stable_p_state)
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if (pi->caps_stable_p_state)
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pi->vce_boot_level = table->count - 1;
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pi->vce_boot_level = table->count - 1;
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else
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else
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@ -1573,15 +1568,9 @@ static int kv_update_vce_dpm(struct amdgpu_device *adev,
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amdgpu_kv_send_msg_to_smc_with_parameter(adev,
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amdgpu_kv_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_VCEDPM_SetEnabledMask,
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PPSMC_MSG_VCEDPM_SetEnabledMask,
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(1 << pi->vce_boot_level));
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(1 << pi->vce_boot_level));
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kv_enable_vce_dpm(adev, true);
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kv_enable_vce_dpm(adev, true);
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} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
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} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
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kv_enable_vce_dpm(adev, false);
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kv_enable_vce_dpm(adev, false);
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/* turn the clocks off when not encoding */
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ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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if (ret)
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return ret;
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kv_dpm_powergate_vce(adev, true);
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kv_dpm_powergate_vce(adev, true);
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}
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}
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@ -1713,32 +1702,19 @@ static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
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static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
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static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
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{
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{
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struct kv_power_info *pi = kv_get_pi(adev);
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struct kv_power_info *pi = kv_get_pi(adev);
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int ret;
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if (pi->vce_power_gated == gate)
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if (pi->vce_power_gated == gate)
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return;
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return;
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pi->vce_power_gated = gate;
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pi->vce_power_gated = gate;
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if (gate) {
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if (!pi->caps_vce_pg)
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if (pi->caps_vce_pg) {
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return;
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/* shutdown the VCE block */
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ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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if (gate)
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AMD_PG_STATE_GATE);
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/* XXX: check for errors */
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/* power off the VCE block */
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amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
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amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
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}
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else
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} else {
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if (pi->caps_vce_pg) {
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/* power on the VCE block */
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amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
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amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
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/* re-init the VCE block */
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ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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/* XXX: check for errors */
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}
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}
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}
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}
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static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
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static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
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@ -2996,7 +2972,6 @@ static int kv_dpm_late_init(void *handle)
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kv_dpm_powergate_acp(adev, true);
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kv_dpm_powergate_acp(adev, true);
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kv_dpm_powergate_samu(adev, true);
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kv_dpm_powergate_samu(adev, true);
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kv_dpm_powergate_vce(adev, true);
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return 0;
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return 0;
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}
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}
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@ -46,6 +46,11 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
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static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
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static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
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static int vce_v2_0_wait_for_idle(void *handle);
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static int vce_v2_0_wait_for_idle(void *handle);
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static void vce_v2_0_init_cg(struct amdgpu_device *adev);
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static void vce_v2_0_disable_cg(struct amdgpu_device *adev);
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static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
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bool sw_cg);
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/**
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/**
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* vce_v2_0_ring_get_rptr - get read pointer
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* vce_v2_0_ring_get_rptr - get read pointer
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*
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*
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@ -152,11 +157,14 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
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struct amdgpu_ring *ring;
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struct amdgpu_ring *ring;
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int r;
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int r;
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vce_v2_0_mc_resume(adev);
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/* set BUSY flag */
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/* set BUSY flag */
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WREG32_P(mmVCE_STATUS, 1, ~1);
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WREG32_P(mmVCE_STATUS, 1, ~1);
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vce_v2_0_init_cg(adev);
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vce_v2_0_disable_cg(adev);
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vce_v2_0_mc_resume(adev);
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ring = &adev->vce.ring[0];
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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@ -189,6 +197,54 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
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return 0;
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return 0;
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}
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}
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static int vce_v2_0_stop(struct amdgpu_device *adev)
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{
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int i, j;
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int status;
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if (vce_v2_0_lmi_clean(adev)) {
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DRM_INFO("vce is not idle \n");
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return 0;
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}
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/*
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for (i = 0; i < 10; ++i) {
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for (j = 0; j < 100; ++j) {
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status = RREG32(mmVCE_FW_REG_STATUS);
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if (!(status & 1))
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break;
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mdelay(1);
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}
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break;
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}
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*/
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if (vce_v2_0_wait_for_idle(adev)) {
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DRM_INFO("VCE is busy, Can't set clock gateing");
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return 0;
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}
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/* Stall UMC and register bus before resetting VCPU */
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WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
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for (i = 0; i < 10; ++i) {
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for (j = 0; j < 100; ++j) {
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status = RREG32(mmVCE_LMI_STATUS);
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if (status & 0x240)
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break;
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mdelay(1);
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}
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break;
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}
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WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);
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/* put LMI, VCPU, RBC etc... into reset */
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WREG32_P(mmVCE_SOFT_RESET, 1, ~0x1);
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WREG32(mmVCE_STATUS, 0);
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return 0;
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}
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static int vce_v2_0_early_init(void *handle)
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static int vce_v2_0_early_init(void *handle)
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{
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -254,11 +310,8 @@ static int vce_v2_0_hw_init(void *handle)
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int r, i;
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int r, i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = vce_v2_0_start(adev);
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amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
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/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
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vce_v2_0_enable_mgcg(adev, true, false);
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if (r)
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return 0;
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for (i = 0; i < adev->vce.num_rings; i++)
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for (i = 0; i < adev->vce.num_rings; i++)
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adev->vce.ring[i].ready = false;
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adev->vce.ring[i].ready = false;
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@ -349,50 +402,40 @@ static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
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static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
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static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
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{
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{
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if (vce_v2_0_wait_for_idle(adev)) {
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u32 orig, tmp;
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DRM_INFO("VCE is busy, Can't set clock gateing");
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return;
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}
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WREG32_P(mmVCE_LMI_CTRL2, 0x100, ~0x100);
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/* LMI_MC/LMI_UMC always set in dynamic,
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* set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0}
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*/
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp &= ~0x00060006;
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if (vce_v2_0_lmi_clean(adev)) {
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/* Exception for ECPU, IH, SEM, SYS blocks needs to be turned on/off by SW */
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DRM_INFO("LMI is busy, Can't set clock gateing");
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return;
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}
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WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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WREG32(mmVCE_STATUS, 0);
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if (gated)
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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/* LMI_MC/LMI_UMC always set in dynamic, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0} */
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if (gated) {
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if (gated) {
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/* Force CLOCK OFF , set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {*, 1} */
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tmp |= 0xe10000;
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WREG32(mmVCE_CLOCK_GATING_B, 0xe90010);
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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} else {
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} else {
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/* Force CLOCK ON, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {1, 0} */
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tmp |= 0xe1;
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WREG32(mmVCE_CLOCK_GATING_B, 0x800f1);
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tmp &= ~0xe10000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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}
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}
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/* Set VCE_UENC_CLOCK_GATING always in dynamic mode {*_FORCE_ON, *_FORCE_OFF} = {0, 0}*/;
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orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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WREG32(mmVCE_UENC_CLOCK_GATING, 0x40);
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tmp &= ~0x1fe000;
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tmp &= ~0xff000000;
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if (tmp != orig)
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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if (tmp != orig)
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
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/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
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WREG32_P(mmVCE_LMI_CTRL2, 0, ~0x100);
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if(gated)
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if(!gated) {
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
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mdelay(100);
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WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
|
|
||||||
|
|
||||||
vce_v2_0_firmware_loaded(adev);
|
|
||||||
WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
|
static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
|
||||||
@ -400,10 +443,9 @@ static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
|
|||||||
WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
|
WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
|
static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
|
||||||
|
bool sw_cg)
|
||||||
{
|
{
|
||||||
bool sw_cg = false;
|
|
||||||
|
|
||||||
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
|
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
|
||||||
if (sw_cg)
|
if (sw_cg)
|
||||||
vce_v2_0_set_sw_cg(adev, true);
|
vce_v2_0_set_sw_cg(adev, true);
|
||||||
@ -473,8 +515,6 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
|
|||||||
|
|
||||||
WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
|
WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
|
||||||
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
|
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
|
||||||
|
|
||||||
vce_v2_0_init_cg(adev);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool vce_v2_0_is_idle(void *handle)
|
static bool vce_v2_0_is_idle(void *handle)
|
||||||
@ -539,33 +579,20 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void vce_v2_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
|
|
||||||
{
|
|
||||||
u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
|
|
||||||
|
|
||||||
if (enable)
|
|
||||||
tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
|
|
||||||
else
|
|
||||||
tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
|
|
||||||
|
|
||||||
WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static int vce_v2_0_set_clockgating_state(void *handle,
|
static int vce_v2_0_set_clockgating_state(void *handle,
|
||||||
enum amd_clockgating_state state)
|
enum amd_clockgating_state state)
|
||||||
{
|
{
|
||||||
bool gate = false;
|
bool gate = false;
|
||||||
|
bool sw_cg = false;
|
||||||
|
|
||||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
|
||||||
|
|
||||||
|
if (state == AMD_CG_STATE_GATE) {
|
||||||
vce_v2_0_set_bypass_mode(adev, enable);
|
|
||||||
|
|
||||||
if (state == AMD_CG_STATE_GATE)
|
|
||||||
gate = true;
|
gate = true;
|
||||||
|
sw_cg = true;
|
||||||
|
}
|
||||||
|
|
||||||
vce_v2_0_enable_mgcg(adev, gate);
|
vce_v2_0_enable_mgcg(adev, gate, sw_cg);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -582,12 +609,8 @@ static int vce_v2_0_set_powergating_state(void *handle,
|
|||||||
*/
|
*/
|
||||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||||
|
|
||||||
if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
if (state == AMD_PG_STATE_GATE)
|
if (state == AMD_PG_STATE_GATE)
|
||||||
/* XXX do we need a vce_v2_0_stop()? */
|
return vce_v2_0_stop(adev);
|
||||||
return 0;
|
|
||||||
else
|
else
|
||||||
return vce_v2_0_start(adev);
|
return vce_v2_0_start(adev);
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user