forked from Minki/linux
drm/amdkfd: Add GFXv9 device queue manager
Signed-off-by: John Bridgman <john.bridgman@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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@ -35,7 +35,7 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \
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kfd_kernel_queue_vi.o kfd_kernel_queue_v9.o \
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kfd_packet_manager.o kfd_process_queue_manager.o \
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kfd_device_queue_manager.o kfd_device_queue_manager_cik.o \
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kfd_device_queue_manager_vi.o \
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kfd_device_queue_manager_vi.o kfd_device_queue_manager_v9.o \
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kfd_interrupt.o kfd_events.o cik_event_interrupt.o \
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kfd_dbgdev.o kfd_dbgmgr.o kfd_crat.o
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@ -1386,7 +1386,10 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm,
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void __user *alternate_aperture_base,
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uint64_t alternate_aperture_size)
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{
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bool retval;
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bool retval = true;
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if (!dqm->asic_ops.set_cache_memory_policy)
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return retval;
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mutex_lock(&dqm->lock);
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@ -1655,6 +1658,11 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
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case CHIP_POLARIS11:
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device_queue_manager_init_vi_tonga(&dqm->asic_ops);
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break;
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case CHIP_VEGA10:
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case CHIP_RAVEN:
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device_queue_manager_init_v9(&dqm->asic_ops);
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break;
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default:
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WARN(1, "Unexpected ASIC family %u",
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dev->device_info->asic_family);
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@ -200,6 +200,8 @@ void device_queue_manager_init_vi(
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struct device_queue_manager_asic_ops *asic_ops);
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void device_queue_manager_init_vi_tonga(
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struct device_queue_manager_asic_ops *asic_ops);
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void device_queue_manager_init_v9(
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struct device_queue_manager_asic_ops *asic_ops);
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void program_sh_mem_settings(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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unsigned int get_queues_num(struct device_queue_manager *dqm);
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84
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
Normal file
84
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
Normal file
@ -0,0 +1,84 @@
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/*
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* Copyright 2016-2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "kfd_device_queue_manager.h"
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#include "vega10_enum.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "sdma0/sdma0_4_0_sh_mask.h"
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static int update_qpd_v9(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
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struct qcm_process_device *qpd);
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void device_queue_manager_init_v9(
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struct device_queue_manager_asic_ops *asic_ops)
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{
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asic_ops->update_qpd = update_qpd_v9;
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asic_ops->init_sdma_vm = init_sdma_vm_v9;
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}
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static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
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{
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uint32_t shared_base = pdd->lds_base >> 48;
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uint32_t private_base = pdd->scratch_base >> 48;
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return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
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private_base;
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}
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static int update_qpd_v9(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd)
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{
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struct kfd_process_device *pdd;
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pdd = qpd_to_pdd(qpd);
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/* check if sh_mem_config register already configured */
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if (qpd->sh_mem_config == 0) {
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qpd->sh_mem_config =
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SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
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if (vega10_noretry &&
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!dqm->dev->device_info->needs_iommu_device)
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qpd->sh_mem_config |=
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1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
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}
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qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
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pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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return 0;
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}
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static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
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struct qcm_process_device *qpd)
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{
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/* Not needed on SDMAv4 any more */
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q->properties.sdma_vm_addr = 0;
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}
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@ -83,6 +83,11 @@ module_param(ignore_crat, int, 0444);
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MODULE_PARM_DESC(ignore_crat,
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"Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
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int vega10_noretry;
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module_param_named(noretry, vega10_noretry, int, 0644);
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MODULE_PARM_DESC(noretry,
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"Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
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static int amdkfd_init_completed;
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int kgd2kfd_init(unsigned int interface_version,
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@ -137,6 +137,11 @@ extern int debug_largebar;
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*/
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extern int ignore_crat;
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/*
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* Set sh_mem_config.retry_disable on Vega10
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*/
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extern int vega10_noretry;
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/**
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* enum kfd_sched_policy
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*
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