forked from Minki/linux
ptp: ptp_clockmatrix: Add PTP_CLK_REQ_EXTTS support
Use TOD_READ_SECONDARY for extts to keep TOD_READ_PRIMARY for gettime and settime exclusively. Before this change, TOD_READ_PRIMARY was used for both extts and gettime/settime, which would result in changing TOD read/write triggers between operations. Using TOD_READ_SECONDARY would make extts independent of gettime/settime operation Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1652712427-14703-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Min Li
Jakub Kicinski
parent
5ff0348b7f
commit
bec6759252
@ -239,73 +239,97 @@ static int wait_for_boot_status_ready(struct idtcm *idtcm)
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return -EBUSY;
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}
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static int _idtcm_set_scsr_read_trig(struct idtcm_channel *channel,
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enum scsr_read_trig_sel trig, u8 ref)
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static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
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{
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struct idtcm *idtcm = channel->idtcm;
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u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
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u8 val;
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u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
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u8 val = 0;
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int err;
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if (trig == SCSR_TOD_READ_TRIG_SEL_REFCLK) {
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err = idtcm_read(idtcm, channel->tod_read_primary,
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TOD_READ_PRIMARY_SEL_CFG_0, &val, sizeof(val));
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if (err)
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return err;
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val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
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val |= (ref << WR_REF_INDEX_SHIFT);
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val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
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val |= (ref << WR_REF_INDEX_SHIFT);
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err = idtcm_write(idtcm, channel->tod_read_primary,
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TOD_READ_PRIMARY_SEL_CFG_0, &val, sizeof(val));
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if (err)
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return err;
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}
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err = idtcm_read(idtcm, channel->tod_read_primary,
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tod_read_cmd, &val, sizeof(val));
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err = idtcm_write(idtcm, channel->tod_read_secondary,
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TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));
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if (err)
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return err;
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val &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
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val |= (trig << TOD_READ_TRIGGER_SHIFT);
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val &= ~TOD_READ_TRIGGER_MODE; /* single shot */
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val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);
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err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
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&val, sizeof(val));
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if (err)
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dev_err(idtcm->dev, "%s: err = %d", __func__, err);
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err = idtcm_write(idtcm, channel->tod_read_primary,
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tod_read_cmd, &val, sizeof(val));
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return err;
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}
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static int idtcm_enable_extts(struct idtcm_channel *channel, u8 todn, u8 ref,
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bool enable)
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static bool is_single_shot(u8 mask)
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{
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struct idtcm *idtcm = channel->idtcm;
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u8 old_mask = idtcm->extts_mask;
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u8 mask = 1 << todn;
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int err = 0;
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/* Treat single bit ToD masks as continuous trigger */
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return mask <= 8 && is_power_of_2(mask);
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}
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if (todn >= MAX_TOD)
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static int idtcm_extts_enable(struct idtcm_channel *channel,
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struct ptp_clock_request *rq, int on)
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{
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u8 index = rq->extts.index;
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struct idtcm *idtcm;
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u8 mask = 1 << index;
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int err = 0;
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u8 old_mask;
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int ref;
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idtcm = channel->idtcm;
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old_mask = idtcm->extts_mask;
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/* Reject requests with unsupported flags */
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if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
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PTP_RISING_EDGE |
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PTP_FALLING_EDGE |
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PTP_STRICT_FLAGS))
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return -EOPNOTSUPP;
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/* Reject requests to enable time stamping on falling edge */
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if ((rq->extts.flags & PTP_ENABLE_FEATURE) &&
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(rq->extts.flags & PTP_FALLING_EDGE))
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return -EOPNOTSUPP;
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if (index >= MAX_TOD)
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return -EINVAL;
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if (enable) {
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if (ref > 0xF) /* E_REF_CLK15 */
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return -EINVAL;
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if (idtcm->extts_mask & mask)
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return 0;
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err = _idtcm_set_scsr_read_trig(&idtcm->channel[todn],
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SCSR_TOD_READ_TRIG_SEL_REFCLK,
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ref);
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if (on) {
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/* Support triggering more than one TOD_0/1/2/3 by same pin */
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/* Use the pin configured for the channel */
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ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
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if (ref < 0) {
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dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
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__func__, channel->tod);
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return -EBUSY;
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}
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err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
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if (err == 0) {
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idtcm->extts_mask |= mask;
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idtcm->event_channel[todn] = channel;
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idtcm->channel[todn].refn = ref;
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}
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} else
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idtcm->extts_mask &= ~mask;
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idtcm->event_channel[index] = channel;
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idtcm->channel[index].refn = ref;
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idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
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if (old_mask == 0 && idtcm->extts_mask)
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schedule_delayed_work(&idtcm->extts_work,
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msecs_to_jiffies(EXTTS_PERIOD_MS));
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if (old_mask)
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return 0;
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schedule_delayed_work(&idtcm->extts_work,
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msecs_to_jiffies(EXTTS_PERIOD_MS));
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}
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} else {
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idtcm->extts_mask &= ~mask;
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idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
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if (idtcm->extts_mask == 0)
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cancel_delayed_work(&idtcm->extts_work);
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}
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return err;
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}
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@ -371,6 +395,31 @@ static void wait_for_chip_ready(struct idtcm *idtcm)
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"Continuing while SYS APLL/DPLL is not locked");
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}
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static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
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struct timespec64 *ts)
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{
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struct idtcm *idtcm = channel->idtcm;
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u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
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u8 buf[TOD_BYTE_COUNT];
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u8 trigger;
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int err;
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err = idtcm_read(idtcm, channel->tod_read_secondary,
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tod_read_cmd, &trigger, sizeof(trigger));
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if (err)
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return err;
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if (trigger & TOD_READ_TRIGGER_MASK)
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return -EBUSY;
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err = idtcm_read(idtcm, channel->tod_read_secondary,
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TOD_READ_SECONDARY_BASE, buf, sizeof(buf));
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if (err)
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return err;
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return char_array_to_timespec(buf, sizeof(buf), ts);
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}
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static int _idtcm_gettime(struct idtcm_channel *channel,
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struct timespec64 *ts, u8 timeout)
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{
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@ -396,7 +445,7 @@ static int _idtcm_gettime(struct idtcm_channel *channel,
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} while (trigger & TOD_READ_TRIGGER_MASK);
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err = idtcm_read(idtcm, channel->tod_read_primary,
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TOD_READ_PRIMARY, buf, sizeof(buf));
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TOD_READ_PRIMARY_BASE, buf, sizeof(buf));
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if (err)
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return err;
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@ -415,67 +464,38 @@ static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
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extts_channel = &idtcm->channel[todn];
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ptp_channel = idtcm->event_channel[todn];
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if (extts_channel == ptp_channel)
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dco_delay = ptp_channel->dco_delay;
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err = _idtcm_gettime(extts_channel, &ts, 1);
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if (err == 0) {
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event.type = PTP_CLOCK_EXTTS;
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event.index = todn;
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event.timestamp = timespec64_to_ns(&ts) - dco_delay;
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ptp_clock_event(ptp_channel->ptp_clock, &event);
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}
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err = _idtcm_gettime_triggered(extts_channel, &ts);
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if (err)
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return err;
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/* Triggered - save timestamp */
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event.type = PTP_CLOCK_EXTTS;
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event.index = todn;
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event.timestamp = timespec64_to_ns(&ts) - dco_delay;
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ptp_clock_event(ptp_channel->ptp_clock, &event);
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return err;
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}
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static u8 idtcm_enable_extts_mask(struct idtcm_channel *channel,
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u8 extts_mask, bool enable)
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{
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struct idtcm *idtcm = channel->idtcm;
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int i, err;
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for (i = 0; i < MAX_TOD; i++) {
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u8 mask = 1 << i;
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u8 refn = idtcm->channel[i].refn;
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if (extts_mask & mask) {
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/* check extts before disabling it */
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if (enable == false) {
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err = idtcm_extts_check_channel(idtcm, i);
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/* trigger happened so we won't re-enable it */
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if (err == 0)
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extts_mask &= ~mask;
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}
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(void)idtcm_enable_extts(channel, i, refn, enable);
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}
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}
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return extts_mask;
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}
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static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
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struct timespec64 *ts)
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{
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struct idtcm *idtcm = channel->idtcm;
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u8 extts_mask = 0;
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u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
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u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT);
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int err;
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/* Disable extts */
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if (idtcm->extts_mask) {
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extts_mask = idtcm_enable_extts_mask(channel, idtcm->extts_mask,
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false);
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}
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err = idtcm_write(idtcm, channel->tod_read_primary,
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tod_read_cmd, &val, sizeof(val));
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if (err)
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return err;
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err = _idtcm_set_scsr_read_trig(channel,
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SCSR_TOD_READ_TRIG_SEL_IMMEDIATE, 0);
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if (err == 0)
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err = _idtcm_gettime(channel, ts, 10);
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/* Re-enable extts */
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if (extts_mask)
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idtcm_enable_extts_mask(channel, extts_mask, true);
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return err;
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return _idtcm_gettime(channel, ts, 10);
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}
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static int _sync_pll_output(struct idtcm *idtcm,
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@ -1702,6 +1722,9 @@ static int initialize_dco_operating_mode(struct idtcm_channel *channel)
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/*
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* Maximum absolute value for write phase offset in picoseconds
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*
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* @channel: channel
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* @delta_ns: delta in nanoseconds
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*
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* Destination signed register is 32-bit register in resolution of 50ps
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*
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* 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
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@ -1958,8 +1981,7 @@ static int idtcm_enable(struct ptp_clock_info *ptp,
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err = idtcm_perout_enable(channel, &rq->perout, true);
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break;
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case PTP_CLK_REQ_EXTTS:
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err = idtcm_enable_extts(channel, rq->extts.index,
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rq->extts.rsv[0], on);
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err = idtcm_extts_enable(channel, rq, on);
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break;
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default:
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break;
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@ -1982,13 +2004,6 @@ static int idtcm_enable_tod(struct idtcm_channel *channel)
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u8 cfg;
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int err;
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/* STEELAI-366 - Temporary workaround for ts2phc compatibility */
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if (0) {
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err = idtcm_output_mask_enable(channel, false);
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if (err)
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return err;
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}
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/*
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* Start the TOD clock ticking.
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*/
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@ -2038,17 +2053,35 @@ static void idtcm_set_version_info(struct idtcm *idtcm)
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product_id, hw_rev_id, config_select);
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}
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static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
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enum ptp_pin_function func, unsigned int chan)
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{
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switch (func) {
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case PTP_PF_NONE:
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case PTP_PF_EXTTS:
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break;
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case PTP_PF_PEROUT:
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case PTP_PF_PHYSYNC:
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return -1;
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}
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return 0;
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}
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static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK];
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static const struct ptp_clock_info idtcm_caps = {
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.owner = THIS_MODULE,
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.max_adj = 244000,
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.n_per_out = 12,
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.n_ext_ts = MAX_TOD,
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.n_pins = MAX_REF_CLK,
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.adjphase = &idtcm_adjphase,
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.adjfine = &idtcm_adjfine,
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.adjtime = &idtcm_adjtime,
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.gettime64 = &idtcm_gettime,
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.settime64 = &idtcm_settime,
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.enable = &idtcm_enable,
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.verify = &idtcm_verify_pin,
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.do_aux_work = &idtcm_work_handler,
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};
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@ -2057,12 +2090,14 @@ static const struct ptp_clock_info idtcm_caps_deprecated = {
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.max_adj = 244000,
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.n_per_out = 12,
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.n_ext_ts = MAX_TOD,
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.n_pins = MAX_REF_CLK,
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.adjphase = &idtcm_adjphase,
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.adjfine = &idtcm_adjfine,
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.adjtime = &idtcm_adjtime_deprecated,
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.gettime64 = &idtcm_gettime,
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.settime64 = &idtcm_settime_deprecated,
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.enable = &idtcm_enable,
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.verify = &idtcm_verify_pin,
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.do_aux_work = &idtcm_work_handler,
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};
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@ -2174,8 +2209,9 @@ static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
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n = 1;
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fodFreq = (u32)div_u64(m, n);
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if (fodFreq >= 500000000)
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return 18 * (u32)div_u64(NSEC_PER_SEC, fodFreq);
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return (u32)div_u64(18 * (u64)NSEC_PER_SEC, fodFreq);
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return 0;
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}
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@ -2188,24 +2224,28 @@ static int configure_channel_tod(struct idtcm_channel *channel, u32 index)
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switch (index) {
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case 0:
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channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0);
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channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0);
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channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0);
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channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0);
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channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
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break;
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case 1:
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channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1);
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channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1);
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channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1);
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channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1);
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channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
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break;
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case 2:
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channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2);
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channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2);
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channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2);
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channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2);
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channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
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break;
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case 3:
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channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3);
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channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3);
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channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3);
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channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3);
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channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
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@ -2221,6 +2261,7 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
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{
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struct idtcm_channel *channel;
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int err;
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int i;
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if (!(index < MAX_TOD))
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return -EINVAL;
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||||
@ -2248,6 +2289,17 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
|
||||
snprintf(channel->caps.name, sizeof(channel->caps.name),
|
||||
"IDT CM TOD%u", index);
|
||||
|
||||
channel->caps.pin_config = pin_config[index];
|
||||
|
||||
for (i = 0; i < channel->caps.n_pins; ++i) {
|
||||
struct ptp_pin_desc *ppd = &channel->caps.pin_config[i];
|
||||
|
||||
snprintf(ppd->name, sizeof(ppd->name), "input_ref%d", i);
|
||||
ppd->index = i;
|
||||
ppd->func = PTP_PF_NONE;
|
||||
ppd->chan = index;
|
||||
}
|
||||
|
||||
err = initialize_dco_operating_mode(channel);
|
||||
if (err)
|
||||
return err;
|
||||
@ -2302,26 +2354,40 @@ static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index)
|
||||
static void idtcm_extts_check(struct work_struct *work)
|
||||
{
|
||||
struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work);
|
||||
int err, i;
|
||||
struct idtcm_channel *channel;
|
||||
u8 mask;
|
||||
int err;
|
||||
int i;
|
||||
|
||||
if (idtcm->extts_mask == 0)
|
||||
return;
|
||||
|
||||
mutex_lock(idtcm->lock);
|
||||
for (i = 0; i < MAX_TOD; i++) {
|
||||
u8 mask = 1 << i;
|
||||
|
||||
if (idtcm->extts_mask & mask) {
|
||||
err = idtcm_extts_check_channel(idtcm, i);
|
||||
for (i = 0; i < MAX_TOD; i++) {
|
||||
mask = 1 << i;
|
||||
|
||||
if ((idtcm->extts_mask & mask) == 0)
|
||||
continue;
|
||||
|
||||
err = idtcm_extts_check_channel(idtcm, i);
|
||||
|
||||
if (err == 0) {
|
||||
/* trigger clears itself, so clear the mask */
|
||||
if (err == 0)
|
||||
if (idtcm->extts_single_shot) {
|
||||
idtcm->extts_mask &= ~mask;
|
||||
} else {
|
||||
/* Re-arm */
|
||||
channel = &idtcm->channel[i];
|
||||
arm_tod_read_trig_sel_refclk(channel, channel->refn);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (idtcm->extts_mask)
|
||||
schedule_delayed_work(&idtcm->extts_work,
|
||||
msecs_to_jiffies(EXTTS_PERIOD_MS));
|
||||
|
||||
mutex_unlock(idtcm->lock);
|
||||
}
|
||||
|
||||
@ -2342,6 +2408,11 @@ static void set_default_masks(struct idtcm *idtcm)
|
||||
idtcm->tod_mask = DEFAULT_TOD_MASK;
|
||||
idtcm->extts_mask = 0;
|
||||
|
||||
idtcm->channel[0].tod = 0;
|
||||
idtcm->channel[1].tod = 1;
|
||||
idtcm->channel[2].tod = 2;
|
||||
idtcm->channel[3].tod = 3;
|
||||
|
||||
idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
|
||||
idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
|
||||
idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
|
||||
@ -2420,8 +2491,8 @@ static int idtcm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct idtcm *idtcm = platform_get_drvdata(pdev);
|
||||
|
||||
idtcm->extts_mask = 0;
|
||||
ptp_clock_unregister_all(idtcm);
|
||||
|
||||
cancel_delayed_work_sync(&idtcm->extts_work);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -10,11 +10,13 @@
|
||||
|
||||
#include <linux/ktime.h>
|
||||
#include <linux/mfd/idt8a340_reg.h>
|
||||
#include <linux/ptp_clock.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#define FW_FILENAME "idtcm.bin"
|
||||
#define MAX_TOD (4)
|
||||
#define MAX_PLL (8)
|
||||
#define MAX_REF_CLK (16)
|
||||
|
||||
#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
|
||||
|
||||
@ -90,6 +92,7 @@ struct idtcm_channel {
|
||||
u16 dpll_ctrl_n;
|
||||
u16 dpll_phase_pull_in;
|
||||
u16 tod_read_primary;
|
||||
u16 tod_read_secondary;
|
||||
u16 tod_write;
|
||||
u16 tod_n;
|
||||
u16 hw_dpll_n;
|
||||
@ -105,6 +108,7 @@ struct idtcm_channel {
|
||||
/* last input trigger for extts */
|
||||
u8 refn;
|
||||
u8 pll;
|
||||
u8 tod;
|
||||
u16 output_mask;
|
||||
};
|
||||
|
||||
@ -116,6 +120,7 @@ struct idtcm {
|
||||
enum fw_version fw_ver;
|
||||
/* Polls for external time stamps */
|
||||
u8 extts_mask;
|
||||
bool extts_single_shot;
|
||||
struct delayed_work extts_work;
|
||||
/* Remember the ptp channel to report extts */
|
||||
struct idtcm_channel *event_channel[MAX_TOD];
|
||||
|
||||
@ -407,7 +407,7 @@
|
||||
#define TOD_READ_PRIMARY_0 0xcc40
|
||||
#define TOD_READ_PRIMARY_0_V520 0xcc50
|
||||
/* 8-bit subns, 32-bit ns, 48-bit seconds */
|
||||
#define TOD_READ_PRIMARY 0x0000
|
||||
#define TOD_READ_PRIMARY_BASE 0x0000
|
||||
/* Counter increments after TOD write is completed */
|
||||
#define TOD_READ_PRIMARY_COUNTER 0x000b
|
||||
/* Read trigger configuration */
|
||||
@ -424,6 +424,16 @@
|
||||
|
||||
#define TOD_READ_SECONDARY_0 0xcc90
|
||||
#define TOD_READ_SECONDARY_0_V520 0xcca0
|
||||
/* 8-bit subns, 32-bit ns, 48-bit seconds */
|
||||
#define TOD_READ_SECONDARY_BASE 0x0000
|
||||
/* Counter increments after TOD write is completed */
|
||||
#define TOD_READ_SECONDARY_COUNTER 0x000b
|
||||
/* Read trigger configuration */
|
||||
#define TOD_READ_SECONDARY_SEL_CFG_0 0x000c
|
||||
/* Read trigger selection */
|
||||
#define TOD_READ_SECONDARY_CMD 0x000e
|
||||
#define TOD_READ_SECONDARY_CMD_V520 0x000f
|
||||
|
||||
#define TOD_READ_SECONDARY_1 0xcca0
|
||||
#define TOD_READ_SECONDARY_1_V520 0xccb0
|
||||
#define TOD_READ_SECONDARY_2 0xccb0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user