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drm/amd/display: Honor the offset for plane 0.

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With modifiers I'd like to support non-dedicated buffers for
images.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: stable@vger.kernel.org # 5.1.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bas Nieuwenhuizen 2019-12-21 19:05:37 +01:00 committed by Alex Deucher
parent 53f4cb8b55
commit be7b9b327e
1 changed files with 9 additions and 5 deletions
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14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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@ -3815,6 +3815,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
struct dc *dc = adev->dm.dc; struct dc *dc = adev->dm.dc;
struct dc_dcc_surface_param input; struct dc_dcc_surface_param input;
struct dc_surface_dcc_cap output; struct dc_surface_dcc_cap output;
uint64_t plane_address = afb->address + afb->base.offsets[0];
uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
uint64_t dcc_address; uint64_t dcc_address;
@ -3858,7 +3859,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
dcc->independent_64b_blks = i64b; dcc->independent_64b_blks = i64b;
dcc_address = get_dcc_address(afb->address, info); dcc_address = get_dcc_address(plane_address, info);
address->grph.meta_addr.low_part = lower_32_bits(dcc_address); address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
address->grph.meta_addr.high_part = upper_32_bits(dcc_address); address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
@ -3889,6 +3890,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
address->tmz_surface = tmz_surface; address->tmz_surface = tmz_surface;
if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
uint64_t addr = afb->address + fb->offsets[0];
plane_size->surface_size.x = 0; plane_size->surface_size.x = 0;
plane_size->surface_size.y = 0; plane_size->surface_size.y = 0;
plane_size->surface_size.width = fb->width; plane_size->surface_size.width = fb->width;
@ -3897,9 +3900,10 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
fb->pitches[0] / fb->format->cpp[0]; fb->pitches[0] / fb->format->cpp[0];
address->type = PLN_ADDR_TYPE_GRAPHICS; address->type = PLN_ADDR_TYPE_GRAPHICS;
address->grph.addr.low_part = lower_32_bits(afb->address); address->grph.addr.low_part = lower_32_bits(addr);
address->grph.addr.high_part = upper_32_bits(afb->address); address->grph.addr.high_part = upper_32_bits(addr);
} else if (format < SURFACE_PIXEL_FORMAT_INVALID) { } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
uint64_t luma_addr = afb->address + fb->offsets[0];
uint64_t chroma_addr = afb->address + fb->offsets[1]; uint64_t chroma_addr = afb->address + fb->offsets[1];
plane_size->surface_size.x = 0; plane_size->surface_size.x = 0;
@ -3920,9 +3924,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
address->video_progressive.luma_addr.low_part = address->video_progressive.luma_addr.low_part =
lower_32_bits(afb->address); lower_32_bits(luma_addr);
address->video_progressive.luma_addr.high_part = address->video_progressive.luma_addr.high_part =
upper_32_bits(afb->address); upper_32_bits(luma_addr);
address->video_progressive.chroma_addr.low_part = address->video_progressive.chroma_addr.low_part =
lower_32_bits(chroma_addr); lower_32_bits(chroma_addr);
address->video_progressive.chroma_addr.high_part = address->video_progressive.chroma_addr.high_part =