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Merge branch 'samsung/cleanup-exynos-clock' into next/soc

Browse Source 
Conflicts:
	arch/arm/mach-exynos/clock-exynos4.c
	arch/arm/mach-exynos/clock.c

The cleanup moves the exynos4 clock implementation away, while
the other branch modifies the file with the old name.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-03-19 20:52:33 +00:00
commit bde755679a
35 changed files with 2072 additions and 2053 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-exynos/Makefile
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@ -12,7 +12,8 @@ obj- :=
# Core
obj-$(CONFIG_ARCH_EXYNOS4) += common.o clock.o
obj-$(CONFIG_ARCH_EXYNOS) += common.o
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o

1568
arch/arm/mach-exynos/clock-exynos4.c Normal file
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File diff suppressed because it is too large Load Diff

30
arch/arm/mach-exynos/clock-exynos4.h Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for exynos4 clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H __FILE__
#include <linux/clk.h>
extern struct clksrc_clk exynos4_clk_aclk_133;
extern struct clksrc_clk exynos4_clk_mout_mpll;
extern struct clksrc_sources exynos4_clkset_mout_corebus;
extern struct clksrc_sources exynos4_clkset_group;
extern struct clk *exynos4_clkset_aclk_top_list[];
extern struct clk *exynos4_clkset_group_list[];
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */

48
arch/arm/mach-exynos/clock-exynos4210.c
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@ -1,7 +1,5 @@
/*
* linux/arch/arm/mach-exynos4/clock-exynos4210.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4210 - Clock support
@ -28,20 +26,20 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/exynos4-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4210_clock_save[] = {
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD1),
SAVE_ITEM(S5P_CLKDIV_IMAGE),
SAVE_ITEM(S5P_CLKDIV_LCD1),
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
};
#endif
@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
}
static struct clksrc_clk clksrcs[] = {
@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_mout_corebus,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
.sources = &exynos4_clkset_mout_corebus,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_fimd",
@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
},
};
@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
{
.name = "sataphy",
.id = -1,
.parent = &clk_aclk_133.clk,
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "sata",
.id = -1,
.parent = &clk_aclk_133.clk,
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
#define exynos4210_clock_resume NULL
#endif
struct syscore_ops exynos4210_clock_syscore_ops = {
static struct syscore_ops exynos4210_clock_syscore_ops = {
.suspend = exynos4210_clock_suspend,
.resume = exynos4210_clock_resume,
};
@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
{
int ptr;
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
clk_mout_mpll.reg_src.shift = 8;
clk_mout_mpll.reg_src.size = 1;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
exynos4_clk_mout_mpll.reg_src.shift = 8;
exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);

32
arch/arm/mach-exynos/clock-exynos4212.c
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@ -1,7 +1,5 @@
/*
* linux/arch/arm/mach-exynos4/clock-exynos4212.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4212 - Clock support
@ -28,22 +26,22 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/exynos4-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4212_clock_save[] = {
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKDIV_IMAGE),
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
};
#endif
static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_mout_mpll.clk,
[1] = &exynos4_clk_mout_mpll.clk,
};
static struct clksrc_sources clk_src_mpll_user = {
@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
.name = "mout_mpll_user",
},
.sources = &clk_src_mpll_user,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
};
static struct clksrc_clk *sysclks[] = {
@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
#define exynos4212_clock_resume NULL
#endif
struct syscore_ops exynos4212_clock_syscore_ops = {
static struct syscore_ops exynos4212_clock_syscore_ops = {
.suspend = exynos4212_clock_suspend,
.resume = exynos4212_clock_resume,
};
@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
int ptr;
/* usbphy1 is removed */
clkset_group_list[4] = NULL;
exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used */
clkset_group_list[6] = &clk_mout_mpll_user.clk;
clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
clk_mout_mpll.reg_src.shift = 12;
clk_mout_mpll.reg_src.size = 1;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_mpll.reg_src.shift = 12;
exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);

1569
arch/arm/mach-exynos/clock.c
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File diff suppressed because it is too large Load Diff

2
arch/arm/mach-exynos/common.c
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@ -695,7 +695,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
int __init exynos4_init_irq_eint(void)
static int __init exynos4_init_irq_eint(void)
{
int irq;

9
arch/arm/mach-exynos/common.h
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@ -15,12 +15,21 @@
void exynos_init_io(struct map_desc *mach_desc, int size);
void exynos4_init_irq(void);
#ifdef CONFIG_ARCH_EXYNOS4
void exynos4_register_clocks(void);
void exynos4_setup_clocks(void);
void exynos4210_register_clocks(void);
void exynos4212_register_clocks(void);
#else
#define exynos4_register_clocks()
#define exynos4_setup_clocks()
#define exynos4210_register_clocks()
#define exynos4212_register_clocks()
#endif
void exynos4_restart(char mode, const char *cmd);
extern struct sys_timer exynos4_timer;

16
arch/arm/mach-exynos/dma.c
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@ -36,7 +36,7 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
u8 pdma0_peri[] = {
static u8 pdma0_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM2_RX,
@ -69,15 +69,15 @@ u8 pdma0_peri[] = {
DMACH_AC97_PCMOUT,
};
struct dma_pl330_platdata exynos4_pdma0_pdata = {
static struct dma_pl330_platdata exynos4_pdma0_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
.peri_id = pdma0_peri,
};
AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
{IRQ_PDMA0}, &exynos4_pdma0_pdata);
static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);
u8 pdma1_peri[] = {
static u8 pdma1_peri[] = {
DMACH_PCM0_RX,
DMACH_PCM0_TX,
DMACH_PCM1_RX,
@ -105,13 +105,13 @@ u8 pdma1_peri[] = {
DMACH_SLIMBUS5_TX,
};
struct dma_pl330_platdata exynos4_pdma1_pdata = {
static struct dma_pl330_platdata exynos4_pdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
.peri_id = pdma1_peri,
};
AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
{IRQ_PDMA1}, &exynos4_pdma1_pdata);
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
static int __init exynos4_dma_init(void)
{

43
arch/arm/mach-exynos/include/mach/exynos4-clock.h
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@ -1,43 +0,0 @@
/*
* linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for exynos4 clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H __FILE__
#include <linux/clk.h>
extern struct clk clk_sclk_hdmi27m;
extern struct clk clk_sclk_usbphy0;
extern struct clk clk_sclk_usbphy1;
extern struct clk clk_sclk_hdmiphy;
extern struct clksrc_clk clk_sclk_apll;
extern struct clksrc_clk clk_mout_mpll;
extern struct clksrc_clk clk_aclk_133;
extern struct clksrc_clk clk_mout_epll;
extern struct clksrc_clk clk_sclk_vpll;
extern struct clk *clkset_corebus_list[];
extern struct clksrc_sources clkset_mout_corebus;
extern struct clk *clkset_aclk_top_list[];
extern struct clksrc_sources clkset_aclk;
extern struct clk *clkset_group_list[];
extern struct clksrc_sources clkset_group;
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */

370
arch/arm/mach-exynos/include/mach/regs-clock.h
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@ -16,195 +16,247 @@
#include <plat/cpu.h>
#include <mach/map.h>
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C930) : \
S5P_CLKREG(0x04930))
#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C960) : \
S5P_CLKREG(0x08960))
#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x0C930) : \
EXYNOS_CLKREG(0x04930))
#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x0C960) : \
EXYNOS_CLKREG(0x08960))
#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
S5P_CLKREG(0x14004) : \
S5P_CLKREG(0x10008))
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
S5P_CLKREG(0x14108) : \
S5P_CLKREG(0x10108))
#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
S5P_CLKREG(0x1410C) : \
S5P_CLKREG(0x1010C))
#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x14004) : \
EXYNOS_CLKREG(0x10008))
#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x14108) : \
EXYNOS_CLKREG(0x10108))
#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
EXYNOS_CLKREG(0x1410C) : \
EXYNOS_CLKREG(0x1010C))
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
#define S5P_APLLCON0_ENABLE_SHIFT (31)
#define S5P_APLLCON0_LOCKED_SHIFT (29)
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
#define S5P_EPLLCON0_ENABLE_SHIFT (31)
#define S5P_EPLLCON0_LOCKED_SHIFT (29)
#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
#define S5P_VPLLCON0_ENABLE_SHIFT (31)
#define S5P_VPLLCON0_LOCKED_SHIFT (29)
#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
/* Only for EXYNOS4210 */
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
/* Only for EXYNOS4212 */
#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
/* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
#define S5P_EPLL_CON S5P_EPLL_CON0
#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
#endif /* __ASM_ARCH_REGS_CLOCK_H */

2
arch/arm/mach-exynos/mach-origen.c
View File

@ -412,7 +412,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
{ MAX8997_BUCK7, &max8997_buck7_data },
};
struct max8997_platform_data __initdata origen_max8997_pdata = {
static struct max8997_platform_data __initdata origen_max8997_pdata = {
.num_regulators = ARRAY_SIZE(origen_max8997_regulators),
.regulators = origen_max8997_regulators,

2
arch/arm/mach-exynos/mach-universal_c210.c
View File

@ -999,7 +999,7 @@ static void __init universal_map_io(void)
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
void s5p_tv_setup(void)
static void s5p_tv_setup(void)
{
/* direct HPD to HDMI chip */
gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");

40
arch/arm/mach-exynos/pm.c
View File

@ -38,29 +38,29 @@
#include <mach/pmu.h>
static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
{ .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
{ .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
{ .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
{ .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
{ .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
{ .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
static struct sleep_save exynos4210_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
{ .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
};
static struct sleep_save exynos4_epll_save[] = {
SAVE_ITEM(S5P_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1),
SAVE_ITEM(EXYNOS4_EPLL_CON0),
SAVE_ITEM(EXYNOS4_EPLL_CON1),
};
static struct sleep_save exynos4_vpll_save[] = {
SAVE_ITEM(S5P_VPLL_CON0),
SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(EXYNOS4_VPLL_CON0),
SAVE_ITEM(EXYNOS4_VPLL_CON1),
};
static struct sleep_save exynos4_core_save[] = {
@ -231,7 +231,7 @@ static void exynos4_restore_pll(void)
locktime = (3000 / pll_in_rate) * p_div;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_EPLL_LOCK);
__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
s3c_pm_do_restore_core(exynos4_epll_save,
ARRAY_SIZE(exynos4_epll_save));
@ -249,7 +249,7 @@ static void exynos4_restore_pll(void)
locktime = 750;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_VPLL_LOCK);
__raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
s3c_pm_do_restore_core(exynos4_vpll_save,
ARRAY_SIZE(exynos4_vpll_save));
@ -260,14 +260,14 @@ static void exynos4_restore_pll(void)
do {
if (epll_wait) {
pll_con = __raw_readl(S5P_EPLL_CON0);
if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
epll_wait = 0;
}
if (vpll_wait) {
pll_con = __raw_readl(S5P_VPLL_CON0);
if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
vpll_wait = 0;
}
} while (epll_wait || vpll_wait);

12
arch/arm/mach-s3c2410/mach-h1940.c
View File

@ -162,7 +162,7 @@ static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
return (latch_state >> (offset + 16)) & 1;
}
struct gpio_chip h1940_latch_gpiochip = {
static struct gpio_chip h1940_latch_gpiochip = {
.base = H1940_LATCH_GPIO(0),
.owner = THIS_MODULE,
.label = "H1940_LATCH",
@ -304,7 +304,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
{ .volt = 3841, .cur = 0, .level = 0},
};
int h1940_bat_init(void)
static int h1940_bat_init(void)
{
int ret;
@ -317,17 +317,17 @@ int h1940_bat_init(void)
}
void h1940_bat_exit(void)
static void h1940_bat_exit(void)
{
gpio_free(H1940_LATCH_SM803_ENABLE);
}
void h1940_enable_charger(void)
static void h1940_enable_charger(void)
{
gpio_set_value(H1940_LATCH_SM803_ENABLE, 1);
}
void h1940_disable_charger(void)
static void h1940_disable_charger(void)
{
gpio_set_value(H1940_LATCH_SM803_ENABLE, 0);
}
@ -364,7 +364,7 @@ static struct platform_device h1940_battery = {
},
};
DEFINE_SPINLOCK(h1940_blink_spin);
static DEFINE_SPINLOCK(h1940_blink_spin);
int h1940_led_blink_set(unsigned gpio, int state,
unsigned long *delay_on, unsigned long *delay_off)

6
arch/arm/mach-s3c2416/clock.c
View File

@ -132,12 +132,6 @@ static struct clk hsmmc0_clk = {
.ctrlbit = S3C2416_HCLKCON_HSMMC0,
};
void __init_or_cpufreq s3c2416_setup_clocks(void)
{
s3c2443_common_setup_clocks(s3c2416_get_pll);
}
static struct clksrc_clk *clksrcs[] __initdata = {
&hsspi_eplldiv,
&hsspi_mux,

8
arch/arm/mach-s3c2416/mach-smdk2416.c
View File

@ -125,7 +125,7 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
}
};
void smdk2416_hsudc_gpio_init(void)
static void smdk2416_hsudc_gpio_init(void)
{
s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE);
@ -133,20 +133,20 @@ void smdk2416_hsudc_gpio_init(void)
s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0);
}
void smdk2416_hsudc_gpio_uninit(void)
static void smdk2416_hsudc_gpio_uninit(void)
{
s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1);
s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0));
}
struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
.epnum = 9,
.gpio_init = smdk2416_hsudc_gpio_init,
.gpio_uninit = smdk2416_hsudc_gpio_uninit,
};
struct s3c_fb_pd_win smdk2416_fb_win[] = {
static struct s3c_fb_pd_win smdk2416_fb_win[] = {
[0] = {
/* think this is the same as the smdk6410 */
.win_mode = {

4
arch/arm/mach-s3c2440/mach-gta02.c
View File

@ -258,7 +258,7 @@ static struct pcf50633_bl_platform_data gta02_backlight_data = {
.ramp_time = 5,
};
struct pcf50633_platform_data gta02_pcf_pdata = {
static struct pcf50633_platform_data gta02_pcf_pdata = {
.resumers = {
[0] = PCF50633_INT1_USBINS |
PCF50633_INT1_USBREM |
@ -404,7 +404,7 @@ static struct platform_device gta02_nor_flash = {
};
struct platform_device s3c24xx_pwm_device = {
static struct platform_device s3c24xx_pwm_device = {
.name = "s3c24xx_pwm",
.num_resources = 0,
};

12
arch/arm/mach-s3c2440/mach-rx1950.c
View File

@ -217,7 +217,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
{ .volt = 3820, .cur = 0, .level = 0},
};
int rx1950_bat_init(void)
static int rx1950_bat_init(void)
{
int ret;
@ -236,25 +236,25 @@ err_gpio1:
return ret;
}
void rx1950_bat_exit(void)
static void rx1950_bat_exit(void)
{
gpio_free(S3C2410_GPJ(2));
gpio_free(S3C2410_GPJ(3));
}
void rx1950_enable_charger(void)
static void rx1950_enable_charger(void)
{
gpio_direction_output(S3C2410_GPJ(2), 1);
gpio_direction_output(S3C2410_GPJ(3), 1);
}
void rx1950_disable_charger(void)
static void rx1950_disable_charger(void)
{
gpio_direction_output(S3C2410_GPJ(2), 0);
gpio_direction_output(S3C2410_GPJ(3), 0);
}
DEFINE_SPINLOCK(rx1950_blink_spin);
static DEFINE_SPINLOCK(rx1950_blink_spin);
static int rx1950_led_blink_set(unsigned gpio, int state,
unsigned long *delay_on, unsigned long *delay_off)
@ -382,7 +382,7 @@ static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
static struct pwm_device *lcd_pwm;
void rx1950_lcd_power(int enable)
static void rx1950_lcd_power(int enable)
{
int i;
static int enabled;

2
arch/arm/mach-s3c64xx/common.h
View File

@ -25,8 +25,6 @@ void s3c64xx_setup_clocks(void);
void s3c64xx_restart(char mode, const char *cmd);
extern struct syscore_ops s3c64xx_irq_syscore_ops;
#ifdef CONFIG_CPU_S3C6400
extern int s3c6400_init(void);

2
arch/arm/mach-s3c64xx/irq-pm.c
View File

@ -96,7 +96,7 @@ static void s3c64xx_irq_pm_resume(void)
S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
}
struct syscore_ops s3c64xx_irq_syscore_ops = {
static struct syscore_ops s3c64xx_irq_syscore_ops = {
.suspend = s3c64xx_irq_pm_suspend,
.resume = s3c64xx_irq_pm_resume,
};

11
arch/arm/mach-s5p64x0/clock.c
View File

@ -73,7 +73,7 @@ static const u32 clock_table[][3] = {
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
};
unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv;
@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
return rate / (clkdiv + 1);
}
unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
unsigned long rate)
{
u32 iter;
@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
return clock_table[ARRAY_SIZE(clock_table) - 1][0];
}
int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
{
u32 round_tmp;
u32 iter;
@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
struct clk_ops s5p64x0_clkarm_ops = {
static struct clk_ops s5p64x0_clkarm_ops = {
.get_rate = s5p64x0_armclk_get_rate,
.set_rate = s5p64x0_armclk_set_rate,
.round_rate = s5p64x0_armclk_round_rate,
@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = {
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
};
struct clk *clkset_hclk_low_list[] = {
static struct clk *clkset_hclk_low_list[] = {
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};

12
arch/arm/mach-s5p64x0/dma.c
View File

@ -38,7 +38,7 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
u8 s5p6440_pdma_peri[] = {
static u8 s5p6440_pdma_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
@ -63,12 +63,12 @@ u8 s5p6440_pdma_peri[] = {
DMACH_SPI1_RX,
};
struct dma_pl330_platdata s5p6440_pdma_pdata = {
static struct dma_pl330_platdata s5p6440_pdma_pdata = {
.nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
.peri_id = s5p6440_pdma_peri,
};
u8 s5p6450_pdma_peri[] = {
static u8 s5p6450_pdma_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
@ -103,13 +103,13 @@ u8 s5p6450_pdma_peri[] = {
DMACH_UART5_TX,
};
struct dma_pl330_platdata s5p6450_pdma_pdata = {
static struct dma_pl330_platdata s5p6450_pdma_pdata = {
.nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
.peri_id = s5p6450_pdma_peri,
};
AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, S5P64X0_PA_PDMA,
{IRQ_DMA0}, NULL);
static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
static int __init s5p64x0_dma_init(void)
{

7
arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
View File

@ -22,16 +22,9 @@ extern struct clksrc_clk clk_mout_epll;
extern int s5p64x0_epll_enable(struct clk *clk, int enable);
extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
extern struct clk_ops s5p64x0_clkarm_ops;
extern struct clksrc_clk clk_armclk;
extern struct clksrc_clk clk_dout_mpll;
extern struct clk *clkset_hclk_low_list[];
extern struct clksrc_sources clkset_hclk_low;
extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);

28
arch/arm/mach-s5pc100/clock.c
View File

@ -170,7 +170,7 @@ static struct clk *clk_src_mout_am_list[] = {
[1] = &clk_div_apll2.clk,
};
struct clksrc_sources clk_src_mout_am = {
static struct clksrc_sources clk_src_mout_am = {
.sources = clk_src_mout_am_list,
.nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
};
@ -212,7 +212,7 @@ static struct clk *clk_src_mout_onenand_list[] = {
[1] = &clk_div_d1_bus.clk,
};
struct clksrc_sources clk_src_mout_onenand = {
static struct clksrc_sources clk_src_mout_onenand = {
.sources = clk_src_mout_onenand_list,
.nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
};
@ -756,7 +756,7 @@ static struct clk *clk_src_group1_list[] = {
[3] = &clk_mout_hpll.clk,
};
struct clksrc_sources clk_src_group1 = {
static struct clksrc_sources clk_src_group1 = {
.sources = clk_src_group1_list,
.nr_sources = ARRAY_SIZE(clk_src_group1_list),
};
@ -766,7 +766,7 @@ static struct clk *clk_src_group2_list[] = {
[1] = &clk_div_mpll.clk,
};
struct clksrc_sources clk_src_group2 = {
static struct clksrc_sources clk_src_group2 = {
.sources = clk_src_group2_list,
.nr_sources = ARRAY_SIZE(clk_src_group2_list),
};
@ -780,7 +780,7 @@ static struct clk *clk_src_group3_list[] = {
[5] = &clk_mout_hpll.clk,
};
struct clksrc_sources clk_src_group3 = {
static struct clksrc_sources clk_src_group3 = {
.sources = clk_src_group3_list,
.nr_sources = ARRAY_SIZE(clk_src_group3_list),
};
@ -806,7 +806,7 @@ static struct clk *clk_src_group4_list[] = {
[5] = &clk_mout_hpll.clk,
};
struct clksrc_sources clk_src_group4 = {
static struct clksrc_sources clk_src_group4 = {
.sources = clk_src_group4_list,
.nr_sources = ARRAY_SIZE(clk_src_group4_list),
};
@ -831,7 +831,7 @@ static struct clk *clk_src_group5_list[] = {
[4] = &clk_mout_hpll.clk,
};
struct clksrc_sources clk_src_group5 = {
static struct clksrc_sources clk_src_group5 = {
.sources = clk_src_group5_list,
.nr_sources = ARRAY_SIZE(clk_src_group5_list),
};
@ -854,7 +854,7 @@ static struct clk *clk_src_group6_list[] = {
[2] = &clk_div_hdmi.clk,
};
struct clksrc_sources clk_src_group6 = {
static struct clksrc_sources clk_src_group6 = {
.sources = clk_src_group6_list,
.nr_sources = ARRAY_SIZE(clk_src_group6_list),
};
@ -866,7 +866,7 @@ static struct clk *clk_src_group7_list[] = {
[3] = &clk_vclk54m,
};
struct clksrc_sources clk_src_group7 = {
static struct clksrc_sources clk_src_group7 = {
.sources = clk_src_group7_list,
.nr_sources = ARRAY_SIZE(clk_src_group7_list),
};
@ -877,7 +877,7 @@ static struct clk *clk_src_mmc0_list[] = {
[2] = &clk_fin_epll,
};
struct clksrc_sources clk_src_mmc0 = {
static struct clksrc_sources clk_src_mmc0 = {
.sources = clk_src_mmc0_list,
.nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
};
@ -889,7 +889,7 @@ static struct clk *clk_src_mmc12_list[] = {
[3] = &clk_mout_hpll.clk,
};
struct clksrc_sources clk_src_mmc12 = {
static struct clksrc_sources clk_src_mmc12 = {
.sources = clk_src_mmc12_list,
.nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
};
@ -901,7 +901,7 @@ static struct clk *clk_src_irda_usb_list[] = {
[3] = &clk_mout_hpll.clk,
};
struct clksrc_sources clk_src_irda_usb = {
static struct clksrc_sources clk_src_irda_usb = {
.sources = clk_src_irda_usb_list,
.nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
};
@ -912,7 +912,7 @@ static struct clk *clk_src_pwi_list[] = {
[2] = &clk_div_mpll.clk,
};
struct clksrc_sources clk_src_pwi = {
static struct clksrc_sources clk_src_pwi = {
.sources = clk_src_pwi_list,
.nr_sources = ARRAY_SIZE(clk_src_pwi_list),
};
@ -923,7 +923,7 @@ static struct clk *clk_sclk_spdif_list[] = {
[2] = &clk_sclk_audio2.clk,
};
struct clksrc_sources clk_src_sclk_spdif = {
static struct clksrc_sources clk_src_sclk_spdif = {
.sources = clk_sclk_spdif_list,
.nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
};

16
arch/arm/mach-s5pc100/dma.c
View File

@ -35,7 +35,7 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
u8 pdma0_peri[] = {
static u8 pdma0_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
@ -68,15 +68,15 @@ u8 pdma0_peri[] = {
DMACH_HSI_TX,
};
struct dma_pl330_platdata s5pc100_pdma0_pdata = {
static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
.peri_id = pdma0_peri,
};
AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, S5PC100_PA_PDMA0,
{IRQ_PDMA0}, &s5pc100_pdma0_pdata);
static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330,
S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
u8 pdma1_peri[] = {
static u8 pdma1_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
@ -109,13 +109,13 @@ u8 pdma1_peri[] = {
DMACH_MSM_REQ3,
};
struct dma_pl330_platdata s5pc100_pdma1_pdata = {
static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
.peri_id = pdma1_peri,
};
AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, S5PC100_PA_PDMA1,
{IRQ_PDMA1}, &s5pc100_pdma1_pdata);
static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
static int __init s5pc100_dma_init(void)
{

16
arch/arm/mach-s5pv210/dma.c
View File

@ -35,7 +35,7 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
u8 pdma0_peri[] = {
static u8 pdma0_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
@ -66,15 +66,15 @@ u8 pdma0_peri[] = {
DMACH_SPDIF,
};
struct dma_pl330_platdata s5pv210_pdma0_pdata = {
static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
.peri_id = pdma0_peri,
};
AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330, S5PV210_PA_PDMA0,
{IRQ_PDMA0}, &s5pv210_pdma0_pdata);
static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
u8 pdma1_peri[] = {
static u8 pdma1_peri[] = {
DMACH_UART0_RX,
DMACH_UART0_TX,
DMACH_UART1_RX,
@ -109,13 +109,13 @@ u8 pdma1_peri[] = {
DMACH_PCM2_TX,
};
struct dma_pl330_platdata s5pv210_pdma1_pdata = {
static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
.peri_id = pdma1_peri,
};
AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330, S5PV210_PA_PDMA1,
{IRQ_PDMA1}, &s5pv210_pdma1_pdata);
static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
static int __init s5pv210_dma_init(void)
{

2
arch/arm/mach-s5pv210/mach-goni.c
View File

@ -844,7 +844,7 @@ static struct s5p_fimc_isp_info goni_camera_sensors[] = {
},
};
struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
.isp_info = goni_camera_sensors,
.num_clients = ARRAY_SIZE(goni_camera_sensors),
};

2
arch/arm/mach-s5pv210/mach-smdkv210.c
View File

@ -140,7 +140,7 @@ static struct dm9000_plat_data smdkv210_dm9000_platdata = {
.dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
};
struct platform_device smdkv210_dm9000 = {
static struct platform_device smdkv210_dm9000 = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(smdkv210_dm9000_resources),

2
arch/arm/plat-s3c24xx/s3c2443-clock.c
View File

@ -53,7 +53,7 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
* elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
* such directly equating the two source clocks is impossible.
*/
struct clk clk_mpllref = {
static struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
};

2
arch/arm/plat-s5p/irq-eint.c
View File

@ -200,7 +200,7 @@ static struct irq_chip s5p_irq_vic_eint = {
#endif
};
int __init s5p_init_irq_eint(void)
static int __init s5p_init_irq_eint(void)
{
int irq;

2
arch/arm/plat-s5p/irq-gpioint.c
View File

@ -41,7 +41,7 @@ struct s5p_gpioint_bank {
void (*handler)(unsigned int, struct irq_desc *);
};
LIST_HEAD(banks);
static LIST_HEAD(banks);
static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
{

13
arch/arm/plat-samsung/devs.c
View File

@ -791,17 +791,6 @@ struct platform_device s3c_device_iis = {
};
#endif /* CONFIG_PLAT_S3C24XX */
#ifdef CONFIG_CPU_S3C2440
struct platform_device s3c2412_device_iis = {
.name = "s3c2412-iis",
.id = -1,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
#endif /* CONFIG_CPU_S3C2440 */
/* IDE CFCON */
#ifdef CONFIG_SAMSUNG_DEV_IDE
@ -1125,7 +1114,7 @@ static struct resource s5p_pmu_resource[] = {
DEFINE_RES_IRQ(IRQ_PMU)
};
struct platform_device s5p_device_pmu = {
static struct platform_device s5p_device_pmu = {
.name = "arm-pmu",
.id = ARM_PMU_DEVICE_CPU,
.num_resources = ARRAY_SIZE(s5p_pmu_resource),

2
arch/arm/plat-samsung/dma-ops.c
View File

@ -116,7 +116,7 @@ static inline int samsung_dmadev_flush(unsigned ch)
return dmaengine_terminate_all((struct dma_chan *)ch);
}
struct samsung_dma_ops dmadev_ops = {
static struct samsung_dma_ops dmadev_ops = {
.request = samsung_dmadev_request,
.release = samsung_dmadev_release,
.prepare = samsung_dmadev_prepare,

230
drivers/devfreq/exynos4_bus.c
View File

@ -311,51 +311,51 @@ static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
/* Change Divider - DMC0 */
tmp = data->dmc_divtable[index];
__raw_writel(tmp, S5P_CLKDIV_DMC0);
__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
} while (tmp & 0x11111111);
/* Change Divider - TOP */
tmp = data->top_divtable[index];
__raw_writel(tmp, S5P_CLKDIV_TOP);
__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
} while (tmp & 0x11111);
/* Change Divider - LEFTBUS */
tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
S5P_CLKDIV_BUS_GDLR_SHIFT) |
EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
(exynos4210_clkdiv_lr_bus[index][1] <<
S5P_CLKDIV_BUS_GPLR_SHIFT));
EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
} while (tmp & 0x11);
/* Change Divider - RIGHTBUS */
tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
S5P_CLKDIV_BUS_GDLR_SHIFT) |
EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
(exynos4210_clkdiv_lr_bus[index][1] <<
S5P_CLKDIV_BUS_GPLR_SHIFT));
EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
} while (tmp & 0x11);
return 0;
@ -376,137 +376,137 @@ static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
/* Change Divider - DMC0 */
tmp = data->dmc_divtable[index];
__raw_writel(tmp, S5P_CLKDIV_DMC0);
__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
} while (tmp & 0x11111111);
/* Change Divider - DMC1 */
tmp = __raw_readl(S5P_CLKDIV_DMC1);
tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
tmp &= ~(S5P_CLKDIV_DMC1_G2D_ACP_MASK |
S5P_CLKDIV_DMC1_C2C_MASK |
S5P_CLKDIV_DMC1_C2CACLK_MASK);
tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
EXYNOS4_CLKDIV_DMC1_C2C_MASK |
EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
S5P_CLKDIV_DMC1_G2D_ACP_SHIFT) |
EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
(exynos4x12_clkdiv_dmc1[index][1] <<
S5P_CLKDIV_DMC1_C2C_SHIFT) |
EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
(exynos4x12_clkdiv_dmc1[index][2] <<
S5P_CLKDIV_DMC1_C2CACLK_SHIFT));
EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_DMC1);
__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_DMC1);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
} while (tmp & 0x111111);
/* Change Divider - TOP */
tmp = __raw_readl(S5P_CLKDIV_TOP);
tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
tmp &= ~(S5P_CLKDIV_TOP_ACLK266_GPS_MASK |
S5P_CLKDIV_TOP_ACLK100_MASK |
S5P_CLKDIV_TOP_ACLK160_MASK |
S5P_CLKDIV_TOP_ACLK133_MASK |
S5P_CLKDIV_TOP_ONENAND_MASK);
tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
tmp |= ((exynos4x12_clkdiv_top[index][0] <<
S5P_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
(exynos4x12_clkdiv_top[index][1] <<
S5P_CLKDIV_TOP_ACLK100_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
(exynos4x12_clkdiv_top[index][2] <<
S5P_CLKDIV_TOP_ACLK160_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
(exynos4x12_clkdiv_top[index][3] <<
S5P_CLKDIV_TOP_ACLK133_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
(exynos4x12_clkdiv_top[index][4] <<
S5P_CLKDIV_TOP_ONENAND_SHIFT));
EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_TOP);
__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
} while (tmp & 0x11111);
/* Change Divider - LEFTBUS */
tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
S5P_CLKDIV_BUS_GDLR_SHIFT) |
EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
(exynos4x12_clkdiv_lr_bus[index][1] <<
S5P_CLKDIV_BUS_GPLR_SHIFT));
EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
} while (tmp & 0x11);
/* Change Divider - RIGHTBUS */
tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
S5P_CLKDIV_BUS_GDLR_SHIFT) |
EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
(exynos4x12_clkdiv_lr_bus[index][1] <<
S5P_CLKDIV_BUS_GPLR_SHIFT));
EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
} while (tmp & 0x11);
/* Change Divider - MFC */
tmp = __raw_readl(S5P_CLKDIV_MFC);
tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
tmp &= ~(S5P_CLKDIV_MFC_MASK);
tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
S5P_CLKDIV_MFC_SHIFT));
EXYNOS4_CLKDIV_MFC_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_MFC);
__raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_MFC);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
} while (tmp & 0x1);
/* Change Divider - JPEG */
tmp = __raw_readl(S5P_CLKDIV_CAM1);
tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
tmp &= ~(S5P_CLKDIV_CAM1_JPEG_MASK);
tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
S5P_CLKDIV_CAM1_JPEG_SHIFT));
EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_CAM1);
__raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
} while (tmp & 0x1);
/* Change Divider - FIMC0~3 */
tmp = __raw_readl(S5P_CLKDIV_CAM);
tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
tmp &= ~(S5P_CLKDIV_CAM_FIMC0_MASK | S5P_CLKDIV_CAM_FIMC1_MASK |
S5P_CLKDIV_CAM_FIMC2_MASK | S5P_CLKDIV_CAM_FIMC3_MASK);
tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
S5P_CLKDIV_CAM_FIMC0_SHIFT) |
EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
(exynos4x12_clkdiv_sclkip[index][2] <<
S5P_CLKDIV_CAM_FIMC1_SHIFT) |
EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
(exynos4x12_clkdiv_sclkip[index][2] <<
S5P_CLKDIV_CAM_FIMC2_SHIFT) |
EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
(exynos4x12_clkdiv_sclkip[index][2] <<
S5P_CLKDIV_CAM_FIMC3_SHIFT));
EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
__raw_writel(tmp, S5P_CLKDIV_CAM);
__raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
do {
tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
} while (tmp & 0x1111);
return 0;
@ -760,55 +760,55 @@ static int exynos4210_init_tables(struct busfreq_data *data)
int mgrp;
int i, err = 0;
tmp = __raw_readl(S5P_CLKDIV_DMC0);
tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
for (i = LV_0; i < EX4210_LV_NUM; i++) {
tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
S5P_CLKDIV_DMC0_ACPPCLK_MASK |
S5P_CLKDIV_DMC0_DPHY_MASK |
S5P_CLKDIV_DMC0_DMC_MASK |
S5P_CLKDIV_DMC0_DMCD_MASK |
S5P_CLKDIV_DMC0_DMCP_MASK |
S5P_CLKDIV_DMC0_COPY2_MASK |
S5P_CLKDIV_DMC0_CORETI_MASK);
tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
EXYNOS4_CLKDIV_DMC0_DMC_MASK |
EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
S5P_CLKDIV_DMC0_ACP_SHIFT) |
EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
(exynos4210_clkdiv_dmc0[i][1] <<
S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
(exynos4210_clkdiv_dmc0[i][2] <<
S5P_CLKDIV_DMC0_DPHY_SHIFT) |
EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
(exynos4210_clkdiv_dmc0[i][3] <<
S5P_CLKDIV_DMC0_DMC_SHIFT) |
EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
(exynos4210_clkdiv_dmc0[i][4] <<
S5P_CLKDIV_DMC0_DMCD_SHIFT) |
EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
(exynos4210_clkdiv_dmc0[i][5] <<
S5P_CLKDIV_DMC0_DMCP_SHIFT) |
EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
(exynos4210_clkdiv_dmc0[i][6] <<
S5P_CLKDIV_DMC0_COPY2_SHIFT) |
EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
(exynos4210_clkdiv_dmc0[i][7] <<
S5P_CLKDIV_DMC0_CORETI_SHIFT));
EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
data->dmc_divtable[i] = tmp;
}
tmp = __raw_readl(S5P_CLKDIV_TOP);
tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
for (i = LV_0; i < EX4210_LV_NUM; i++) {
tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK |
S5P_CLKDIV_TOP_ACLK100_MASK |
S5P_CLKDIV_TOP_ACLK160_MASK |
S5P_CLKDIV_TOP_ACLK133_MASK |
S5P_CLKDIV_TOP_ONENAND_MASK);
tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
tmp |= ((exynos4210_clkdiv_top[i][0] <<
S5P_CLKDIV_TOP_ACLK200_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
(exynos4210_clkdiv_top[i][1] <<
S5P_CLKDIV_TOP_ACLK100_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
(exynos4210_clkdiv_top[i][2] <<
S5P_CLKDIV_TOP_ACLK160_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
(exynos4210_clkdiv_top[i][3] <<
S5P_CLKDIV_TOP_ACLK133_SHIFT) |
EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
(exynos4210_clkdiv_top[i][4] <<
S5P_CLKDIV_TOP_ONENAND_SHIFT));
EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
data->top_divtable[i] = tmp;
}
@ -868,32 +868,32 @@ static int exynos4x12_init_tables(struct busfreq_data *data)
int ret;
/* Enable pause function for DREX2 DVFS */
tmp = __raw_readl(S5P_DMC_PAUSE_CTRL);
tmp |= DMC_PAUSE_ENABLE;
__raw_writel(tmp, S5P_DMC_PAUSE_CTRL);
tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
tmp |= EXYNOS4_DMC_PAUSE_ENABLE;
__raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL);
tmp = __raw_readl(S5P_CLKDIV_DMC0);
tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
for (i = 0; i < EX4x12_LV_NUM; i++) {
tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
S5P_CLKDIV_DMC0_ACPPCLK_MASK |
S5P_CLKDIV_DMC0_DPHY_MASK |
S5P_CLKDIV_DMC0_DMC_MASK |
S5P_CLKDIV_DMC0_DMCD_MASK |
S5P_CLKDIV_DMC0_DMCP_MASK);
tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
EXYNOS4_CLKDIV_DMC0_DMC_MASK |
EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
S5P_CLKDIV_DMC0_ACP_SHIFT) |
EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
(exynos4x12_clkdiv_dmc0[i][1] <<
S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
(exynos4x12_clkdiv_dmc0[i][2] <<
S5P_CLKDIV_DMC0_DPHY_SHIFT) |
EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
(exynos4x12_clkdiv_dmc0[i][3] <<
S5P_CLKDIV_DMC0_DMC_SHIFT) |
EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
(exynos4x12_clkdiv_dmc0[i][4] <<
S5P_CLKDIV_DMC0_DMCD_SHIFT) |
EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
(exynos4x12_clkdiv_dmc0[i][5] <<
S5P_CLKDIV_DMC0_DMCP_SHIFT));
EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
data->dmc_divtable[i] = tmp;
}