forked from Minki/linux
Here's the main clk pull request for this merge window. We have some
late breaking reports that a patch series to rework clk rate range
support broke boot on some devices, so I've left that branch out of this
PR. Hopefully we can get to that next week, or punt on it and let it
bake another cycle. That means we don't really have any changes to the
core framework this time around besides a few typo fixes. Instead this
is all clk driver updates and fixes.
The usual suspects are here (again), with Qualcomm dominating the
diffstat. We look to have gained support for quite a few new Qualcomm
SoCs and Dmitry worked on updating many of the existing Qualcomm drivers
to use clk_parent_data. After that we have MediaTek drivers getting some
much needed updates, in particular to support GPU DVFS. There are also
quite a few Samsung clk driver patches, but that's mostly because there
was a maintainer change and so last release we missed some of those
patches.
Overall things look normal, but I'm slowly reviewing core framework code
nowadays and that shows given the rate range patches had to be yanked
last minute. Let's hope this situation changes soon.
New Drivers:
- Support for Renesas VersaClock7 clock generator family
- Add Spreadtrum UMS512 SoC clk support
- New clock drivers for MediaTek Helio X10 MT6795
- Display clks for Qualcomm SM6115, SM8450
- GPU clks for Qualcomm SC8280XP
- Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
Deleted Drivers:
- Remove DaVinci DM644x and DM646x clk driver support
Updates:
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on RaspberryPi
- Mark PLLC critical on bcm2835
- More devm helpers for fixed rate registration
- Various PXA168 clk driver fixes
- Add resets for MediaTek MT8195 PCIe and USB
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
- Add missing DPI1_HDMI clock in MT8195 VDOSYS1
- Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
- Fix GPU clock topology on MT8195
- Propogate rate changes from GPU clock gate up the tree
- Clock mux notifiers for GPU-related PLLs
- Conversion of more "simple" drivers to mtk_clk_simple_probe()
- Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
- Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek
- Shrink MT8192 clock driver by deduplicating clock parent lists
- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider
- add generic clocks for U(S)ART available on SAMA5D2 SoCs
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H
- Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
- Add I2C clocks and resets on RZ/V2M
- Document clock support for the RZ/Five SoC
- mux-variant clock using the table variant to select parents
- clock controller for the rv1126 soc
- conversion of rk3128 to yaml and relicensing of the yaml bindings
to gpl2+MIT (following dt-binding guildelines)
- Exynos7885: add FSYS, TREX and MFC clock controllers
- Exynos850: add IS and AUD (audio) clock controllers with bindings
- ExynosAutov9: add FSYS clock controllers with bindings
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers
- ExynosAutov9: add few missing Peric 0/1 gates
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks
- Minor code improvements (use of_device_get_match_data() helper, code
style)
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
already maintainers that architecture/platform
- Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention
issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP
- Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
- Qualcomm SDM660 SDCC1 moved to floor clk ops
- Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was
added/fixed
- The Qualcomm MSM8996 CPU clocks are updated with support for ACD
- Support for Qualcomm SDM670 GCC and RPMh clks was added
- Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for many Qualcomm SoCs
- Support for per-reset defined delay on Qualcomm was introduced
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have some late breaking reports that a patch series to rework clk
rate range support broke boot on some devices, so I've left that
branch out of this. Hopefully we can get to that next week, or punt on
it and let it bake another cycle. That means we don't really have any
changes to the core framework this time around besides a few typo
fixes. Instead this is all clk driver updates and fixes.
The usual suspects are here (again), with Qualcomm dominating the
diffstat. We look to have gained support for quite a few new Qualcomm
SoCs and Dmitry worked on updating many of the existing Qualcomm
drivers to use clk_parent_data. After that we have MediaTek drivers
getting some much needed updates, in particular to support GPU DVFS.
There are also quite a few Samsung clk driver patches, but that's
mostly because there was a maintainer change and so last release we
missed some of those patches.
Overall things look normal, but I'm slowly reviewing core framework
code nowadays and that shows given the rate range patches had to be
yanked last minute. Let's hope this situation changes soon.
New Drivers:
- Support for Renesas VersaClock7 clock generator family
- Add Spreadtrum UMS512 SoC clk support
- New clock drivers for MediaTek Helio X10 MT6795
- Display clks for Qualcomm SM6115, SM8450
- GPU clks for Qualcomm SC8280XP
- Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
Deleted Drivers:
- Remove DaVinci DM644x and DM646x clk driver support
Updates:
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on
RaspberryPi
- Mark PLLC critical on bcm2835
- More devm helpers for fixed rate registration
- Various PXA168 clk driver fixes
- Add resets for MediaTek MT8195 PCIe and USB
- Miscellaneous of_node_put() fixes
- Nuke dt-bindings/clk path (again) by moving headers to
dt-bindings/clock
- Convert gpio-clk-gate binding to YAML
- Various fixes to AMD/Xilinx Zynqmp clk driver
- Graduate AMD/Xilinx "clocking wizard" driver from staging
- Add missing DPI1_HDMI clock in MT8195 VDOSYS1
- Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
- Fix GPU clock topology on MT8195
- Propogate rate changes from GPU clock gate up the tree
- Clock mux notifiers for GPU-related PLLs
- Conversion of more "simple" drivers to mtk_clk_simple_probe()
- Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
- Fixes to previous |struct clk| to |struct clk_hw| conversion on
MediaTek
- Shrink MT8192 clock driver by deduplicating clock parent lists
- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider
- add generic clocks for U(S)ART available on SAMA5D2 SoCs
- reset controller support for Polarfire clocks
- .round_rate and .set rate support for clk-mpfs
- code cleanup for clk-mpfs
- PLL support for PolarFire SoC's Clock Conditioning Circuitry
- Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
V4H
- Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
- Add I2C clocks and resets on RZ/V2M
- Document clock support for the RZ/Five SoC
- mux-variant clock using the table variant to select parents
- clock controller for the rv1126 soc
- conversion of rk3128 to yaml and relicensing of the yaml bindings
to gpl2+MIT (following dt-binding guildelines)
- Exynos7885: add FSYS, TREX and MFC clock controllers
- Exynos850: add IS and AUD (audio) clock controllers with bindings
- ExynosAutov9: add FSYS clock controllers with bindings
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers
- ExynosAutov9: add few missing Peric 0/1 gates
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks
- Minor code improvements (use of_device_get_match_data() helper,
code style)
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as
he already maintainers that architecture/platform
- Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving
retention issues during suspend of USB on Qualcomm sc7180/sc7280
and SC8280XP
- Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
- Qualcomm SDM660 SDCC1 moved to floor clk ops
- Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018
was added/fixed
- The Qualcomm MSM8996 CPU clocks are updated with support for ACD
- Support for Qualcomm SDM670 GCC and RPMh clks was added
- Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
num_parents was done for many Qualcomm SoCs
- Support for per-reset defined delay on Qualcomm was introduced"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits)
clk: qcom: gcc-sm6375: Ensure unsigned long type
clk: qcom: gcc-sm6375: Remove unused variables
clk: qcom: kpss-xcc: convert to parent data API
clk: introduce (devm_)hw_register_mux_parent_data_table API
clk: allow building lan966x as a module
clk: clk-xgene: simplify if-if to if-else
clk: ast2600: BCLK comes from EPLL
clk: clocking-wizard: Depend on HAS_IOMEM
clk: clocking-wizard: Use dev_err_probe() helper
clk: nxp: fix typo in comment
clk: pxa: add a check for the return value of kzalloc()
clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
dt-bindings: clock: vc5: Add 5P49V6975
clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
clk: Renesas versaclock7 ccf device driver
dt-bindings: Renesas versaclock7 device tree bindings
clk: ti: Balance of_node_get() calls for of_find_node_by_name()
clk: imx: scu: fix memleak on platform_device_add() fails
clk: vc5: Use regmap_{set,clear}_bits() where appropriate
...
This commit is contained in:
Linus Torvalds
commit
bdc753c7fc
@ -23,6 +23,7 @@ properties:
|
||||
- mediatek,mt2701-infracfg
|
||||
- mediatek,mt2712-infracfg
|
||||
- mediatek,mt6765-infracfg
|
||||
- mediatek,mt6795-infracfg
|
||||
- mediatek,mt6779-infracfg_ao
|
||||
- mediatek,mt6797-infracfg
|
||||
- mediatek,mt7622-infracfg
|
||||
@ -60,6 +61,7 @@ if:
|
||||
enum:
|
||||
- mediatek,mt2701-infracfg
|
||||
- mediatek,mt2712-infracfg
|
||||
- mediatek,mt6795-infracfg
|
||||
- mediatek,mt7622-infracfg
|
||||
- mediatek,mt7986-infracfg
|
||||
- mediatek,mt8135-infracfg
|
||||
|
||||
@ -25,6 +25,7 @@ properties:
|
||||
- mediatek,mt2712-mmsys
|
||||
- mediatek,mt6765-mmsys
|
||||
- mediatek,mt6779-mmsys
|
||||
- mediatek,mt6795-mmsys
|
||||
- mediatek,mt6797-mmsys
|
||||
- mediatek,mt8167-mmsys
|
||||
- mediatek,mt8173-mmsys
|
||||
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
- mediatek,mt2701-pericfg
|
||||
- mediatek,mt2712-pericfg
|
||||
- mediatek,mt6765-pericfg
|
||||
- mediatek,mt6795-pericfg
|
||||
- mediatek,mt7622-pericfg
|
||||
- mediatek,mt7629-pericfg
|
||||
- mediatek,mt8135-pericfg
|
||||
|
||||
@ -23,7 +23,6 @@ properties:
|
||||
clocks:
|
||||
description:
|
||||
Common clock binding for CLK_IN, XTI/REF_CLK
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
Binding for simple gpio gated clock.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "gpio-gate-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- enable-gpios : GPIO reference for enabling and disabling the clock.
|
||||
|
||||
Optional properties:
|
||||
- clocks: Maximum of one parent clock is supported.
|
||||
|
||||
Example:
|
||||
clock {
|
||||
compatible = "gpio-gate-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
42
Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
Normal file
42
Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
Normal file
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Simple GPIO clock gate
|
||||
|
||||
maintainers:
|
||||
- Jyri Sarha <jsarha@ti.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: gpio-gate-clock
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
enable-gpios:
|
||||
description: GPIO reference for enabling and disabling the clock.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- enable-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
clock {
|
||||
compatible = "gpio-gate-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
@ -56,6 +56,7 @@ properties:
|
||||
- idt,5p49v5935
|
||||
- idt,5p49v6901
|
||||
- idt,5p49v6965
|
||||
- idt,5p49v6975
|
||||
|
||||
reg:
|
||||
description: I2C device address
|
||||
@ -108,7 +109,7 @@ patternProperties:
|
||||
properties:
|
||||
idt,mode:
|
||||
description:
|
||||
The output drive mode. Values defined in dt-bindings/clk/versaclock.h
|
||||
The output drive mode. Values defined in dt-bindings/clock/versaclock.h
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 6
|
||||
@ -134,6 +135,7 @@ allOf:
|
||||
enum:
|
||||
- idt,5p49v5933
|
||||
- idt,5p49v5935
|
||||
- idt,5p49v6975
|
||||
then:
|
||||
# Devices with builtin crystal + optional external input
|
||||
properties:
|
||||
@ -151,7 +153,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
#include <dt-bindings/clock/versaclock.h>
|
||||
|
||||
/* 25MHz reference crystal */
|
||||
ref25: ref25m {
|
||||
|
||||
@ -34,6 +34,7 @@ properties:
|
||||
- mediatek,mt2712-apmixedsys
|
||||
- mediatek,mt6765-apmixedsys
|
||||
- mediatek,mt6779-apmixedsys
|
||||
- mediatek,mt6795-apmixedsys
|
||||
- mediatek,mt7629-apmixedsys
|
||||
- mediatek,mt8167-apmixedsys
|
||||
- mediatek,mt8183-apmixedsys
|
||||
|
||||
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT6795
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The devices provide clock gate control in different IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt6795-mfgcfg
|
||||
- mediatek,mt6795-vdecsys
|
||||
- mediatek,mt6795-vencsys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
mfgcfg: clock-controller@13000000 {
|
||||
compatible = "mediatek,mt6795-mfgcfg";
|
||||
reg = <0 0x13000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
vdecsys: clock-controller@16000000 {
|
||||
compatible = "mediatek,mt6795-vdecsys";
|
||||
reg = <0 0x16000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
vencsys: clock-controller@18000000 {
|
||||
compatible = "mediatek,mt6795-vencsys";
|
||||
reg = <0 0x18000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT6795
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description:
|
||||
The Mediatek system clock controller provides various clocks and system
|
||||
configuration like reset and bus protection on MT6795.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt6795-apmixedsys
|
||||
- mediatek,mt6795-infracfg
|
||||
- mediatek,mt6795-pericfg
|
||||
- mediatek,mt6795-topckgen
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
topckgen: clock-controller@10000000 {
|
||||
compatible = "mediatek,mt6795-topckgen", "syscon";
|
||||
reg = <0 0x10000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8365-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8365
|
||||
|
||||
maintainers:
|
||||
- Markus Schneider-Pargmann <msp@baylibre.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8365-apu
|
||||
- mediatek,mt8365-imgsys
|
||||
- mediatek,mt8365-mfgcfg
|
||||
- mediatek,mt8365-vdecsys
|
||||
- mediatek,mt8365-vencsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apu: clock-controller@19020000 {
|
||||
compatible = "mediatek,mt8365-apu", "syscon";
|
||||
reg = <0x19020000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8365
|
||||
|
||||
maintainers:
|
||||
- Markus Schneider-Pargmann <msp@baylibre.com>
|
||||
|
||||
description:
|
||||
The apmixedsys module provides most of PLLs which generated from SoC 26m.
|
||||
The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
|
||||
The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8365-topckgen
|
||||
- mediatek,mt8365-infracfg
|
||||
- mediatek,mt8365-apmixedsys
|
||||
- mediatek,mt8365-pericfg
|
||||
- mediatek,mt8365-mcucfg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
topckgen: clock-controller@10000000 {
|
||||
compatible = "mediatek,mt8365-topckgen", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -33,6 +33,7 @@ properties:
|
||||
- mediatek,mt2712-topckgen
|
||||
- mediatek,mt6765-topckgen
|
||||
- mediatek,mt6779-topckgen
|
||||
- mediatek,mt6795-topckgen
|
||||
- mediatek,mt7629-topckgen
|
||||
- mediatek,mt7986-topckgen
|
||||
- mediatek,mt8167-topckgen
|
||||
|
||||
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
|
||||
|
||||
maintainers:
|
||||
- Conor Dooley <conor.dooley@microchip.com>
|
||||
|
||||
description: |
|
||||
Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
|
||||
these blocks contains two PLLs and 2 DLLs & are located in the four corners of
|
||||
the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
|
||||
https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,mpfs-ccc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: PLL0's control registers
|
||||
- description: PLL1's control registers
|
||||
- description: DLL0's control registers
|
||||
- description: DLL1's control registers
|
||||
|
||||
clocks:
|
||||
description:
|
||||
The CCC PLL's have two input clocks. It is required that even if the input
|
||||
clocks are identical that both are provided.
|
||||
minItems: 2
|
||||
items:
|
||||
- description: PLL0's refclk0
|
||||
- description: PLL0's refclk1
|
||||
- description: PLL1's refclk0
|
||||
- description: PLL1's refclk1
|
||||
- description: DLL0's refclk
|
||||
- description: DLL1's refclk
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: pll0_ref0
|
||||
- const: pll0_ref1
|
||||
- const: pll1_ref0
|
||||
- const: pll1_ref1
|
||||
- const: dll0_ref
|
||||
- const: dll1_ref
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell.
|
||||
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
|
||||
PolarFire clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@38100000 {
|
||||
compatible = "microchip,mpfs-ccc";
|
||||
reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
|
||||
<0x39010000 0x1000>, <0x39020000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
|
||||
<&refclk_ccc>, <&refclk_ccc>;
|
||||
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
|
||||
"dll0_ref", "dll1_ref";
|
||||
};
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PolarFire Clock Control Module Binding
|
||||
@ -40,8 +40,21 @@ properties:
|
||||
const: 1
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
|
||||
for the full list of PolarFire clock IDs.
|
||||
ID in its "clocks" phandle cell.
|
||||
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
|
||||
PolarFire clock IDs.
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
description:
|
||||
The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
|
||||
CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
|
||||
peripheral via the clock ID in its "resets" phandle cell.
|
||||
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
|
||||
PolarFire clock IDs.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm A53 PLL Binding
|
||||
|
||||
maintainers:
|
||||
- Sivaprakash Murugesan <sivaprak@codeaurora.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
|
||||
@ -17,6 +17,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq6018-a53pll
|
||||
- qcom,ipq8074-a53pll
|
||||
- qcom,msm8916-a53pll
|
||||
- qcom,msm8939-a53pll
|
||||
|
||||
|
||||
@ -38,6 +38,15 @@ properties:
|
||||
description: child tsens device
|
||||
$ref: /schemas/thermal/qcom-tsens.yaml#
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: cxo
|
||||
- const: pxo
|
||||
- const: pll4
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks and resets on
|
||||
MSM8660
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,gcc.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-msm8660
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxo
|
||||
- const: cxo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8974:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8660";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&pxo_board>, <&cxo_board>;
|
||||
clock-names = "pxo", "cxo";
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8909
|
||||
|
||||
maintainers:
|
||||
- Stephan Gerhold <stephan@gerhold.net>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8909.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8909
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
gcc: clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-msm8909";
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>;
|
||||
clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte";
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8916 or MSM8939.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8916.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8916.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: External MCLK clock
|
||||
- description: External Primary I2S clock
|
||||
- description: External Secondary I2S clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: ext_mclk
|
||||
- const: ext_pri_i2s
|
||||
- const: ext_sec_i2s
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@300000 {
|
||||
compatible = "qcom,gcc-msm8916";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x300000 0x90000>;
|
||||
};
|
||||
...
|
||||
@ -45,29 +45,16 @@ properties:
|
||||
description:
|
||||
Phandle to voltage regulator providing power to the GX domain.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- vdd_gfx-supply
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -32,28 +32,15 @@ properties:
|
||||
- const: xo
|
||||
- const: sleep
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -49,30 +49,13 @@ properties:
|
||||
- const: ufs_rx_symbol_1_clk_src
|
||||
- const: ufs_tx_symbol_0_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -37,32 +37,15 @@ properties:
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -18,11 +18,7 @@ description: |
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
@ -40,9 +36,6 @@ properties:
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
|
||||
@ -30,32 +30,15 @@ properties:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -33,32 +33,15 @@ properties:
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -44,28 +44,15 @@ properties:
|
||||
- const: ufs_phy_tx_symbol_0_clk
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -32,32 +32,15 @@ properties:
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -33,7 +33,7 @@ properties:
|
||||
- description: Primary USB SuperSpeed pipe clock
|
||||
- description: USB4 PHY pipegmux clock source
|
||||
- description: USB4 PHY DP gmux clock source
|
||||
- description: USB4 PHY sys piegmux clock source
|
||||
- description: USB4 PHY sys pipegmux clock source
|
||||
- description: USB4 PHY PCIe pipe clock
|
||||
- description: USB4 PHY router max pipe clock
|
||||
- description: Primary USB4 RX0 clock
|
||||
@ -46,7 +46,7 @@ properties:
|
||||
- description: Second USB4 PHY router max pipe clock
|
||||
- description: Secondary USB4 RX0 clock
|
||||
- description: Secondary USB4 RX1 clock
|
||||
- description: Multiport USB first SupserSpeed pipe clock
|
||||
- description: Multiport USB first SuperSpeed pipe clock
|
||||
- description: Multiport USB second SuperSpeed pipe clock
|
||||
- description: PCIe 2a pipe clock
|
||||
- description: PCIe 2b pipe clock
|
||||
@ -56,30 +56,17 @@ properties:
|
||||
- description: First EMAC controller reference clock
|
||||
- description: Second EMAC controller reference clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
maxItems: 389
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -19,8 +19,51 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sdm845
|
||||
enum:
|
||||
- qcom,gcc-sdm670
|
||||
- qcom,gcc-sdm845
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,gcc-sdm670
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,gcc-sdm845
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
@ -28,7 +71,6 @@ properties:
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source
|
||||
- description: PCIE 1 Pipe clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
@ -37,33 +79,7 @@ properties:
|
||||
- const: pcie_0_pipe_clk
|
||||
- const: pcie_1_pipe_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for SDM845:
|
||||
|
||||
@ -35,28 +35,15 @@ properties:
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -20,9 +20,6 @@ properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sdx65
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
@ -43,25 +40,15 @@ properties:
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 5
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -30,32 +30,15 @@ properties:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -30,32 +30,15 @@ properties:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -32,32 +32,15 @@ properties:
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -31,32 +31,15 @@ properties:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -31,32 +31,15 @@ properties:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -54,28 +54,15 @@ properties:
|
||||
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
|
||||
minItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -46,28 +46,15 @@ properties:
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
|
||||
minItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -17,6 +17,7 @@ description: |
|
||||
dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
dt-bindings/clock/qcom,gpucc-sc8280xp.h
|
||||
dt-bindings/clock/qcom,gpucc-sm6350.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
@ -28,6 +29,7 @@ properties:
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sc7280-gpucc
|
||||
- qcom,sc8180x-gpucc
|
||||
- qcom,sc8280xp-gpucc
|
||||
- qcom,sm6350-gpucc
|
||||
- qcom,sm8150-gpucc
|
||||
- qcom,sm8250-gpucc
|
||||
|
||||
@ -31,30 +31,12 @@ properties:
|
||||
- qcom,mmcc-sdm660
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board sleep source
|
||||
- description: Global PLL 0 clock
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
- description: DisplayPort phy PLL vco clock
|
||||
- description: DisplayPort phy PLL link clock
|
||||
minItems: 8
|
||||
maxItems: 10
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep
|
||||
- const: gpll0
|
||||
- const: dsi0dsi
|
||||
- const: dsi0byte
|
||||
- const: dsi1dsi
|
||||
- const: dsi1byte
|
||||
- const: hdmipll
|
||||
- const: dpvco
|
||||
- const: dplink
|
||||
minItems: 8
|
||||
maxItems: 10
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
@ -85,17 +67,180 @@ required:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,mmcc-msm8998
|
||||
enum:
|
||||
- qcom,mmcc-apq8064
|
||||
- qcom,mmcc-msm8960
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board PXO source
|
||||
- description: PLL 3 clock
|
||||
- description: PLL 3 Vote clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: DSI phy instance 2 dsi clock
|
||||
- description: DSI phy instance 2 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxo
|
||||
- const: pll3
|
||||
- const: pll8_vote
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
- const: dsi2pll
|
||||
- const: dsi2pllbyte
|
||||
- const: hdmipll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,mmcc-msm8994
|
||||
- qcom,mmcc-msm8998
|
||||
- qcom,mmcc-sdm630
|
||||
- qcom,mmcc-sdm660
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,mmcc-msm8994
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Global PLL 0 clock
|
||||
- description: MMSS NoC AHB clock
|
||||
- description: GFX3D clock
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: gpll0
|
||||
- const: mmssnoc_ahb
|
||||
- const: oxili_gfx3d_clk_src
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
- const: hdmipll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,mmcc-msm8996
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Global PLL 0 clock
|
||||
- description: MMSS NoC AHB clock
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: gpll0
|
||||
- const: gcc_mmss_noc_cfg_ahb_clk
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
- const: hdmipll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,mmcc-msm8998
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Global PLL 0 clock
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
- description: DisplayPort phy PLL link clock
|
||||
- description: DisplayPort phy PLL vco clock
|
||||
- description: Test clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: gpll0
|
||||
- const: dsi0dsi
|
||||
- const: dsi0byte
|
||||
- const: dsi1dsi
|
||||
- const: dsi1byte
|
||||
- const: hdmipll
|
||||
- const: dplink
|
||||
- const: dpvco
|
||||
- const: core_bi_pll_test_se
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,mmcc-sdm630
|
||||
- qcom,mmcc-sdm660
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board sleep source
|
||||
- description: Global PLL 0 clock
|
||||
- description: Global PLL 0 DIV clock
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: DisplayPort phy PLL link clock
|
||||
- description: DisplayPort phy PLL vco clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: gpll0
|
||||
- const: gpll0_div
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
- const: dp_link_2x_clk_divsel_five
|
||||
- const: dp_vco_divided_clk_src_mux
|
||||
|
||||
examples:
|
||||
# Example for MMCC for MSM8960:
|
||||
- |
|
||||
|
||||
@ -26,22 +26,18 @@ properties:
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Primary PLL clock for power cluster (little)
|
||||
- description: Primary PLL clock for perf cluster (big)
|
||||
- description: Alternate PLL clock for power cluster (little)
|
||||
- description: Alternate PLL clock for perf cluster (big)
|
||||
- description: XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pwrcl_pll
|
||||
- const: perfcl_pll
|
||||
- const: pwrcl_alt_pll
|
||||
- const: perfcl_alt_pll
|
||||
- const: xo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -51,4 +47,7 @@ examples:
|
||||
compatible = "qcom,msm8996-apcc";
|
||||
reg = <0x6400000 0x90000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "xo";
|
||||
};
|
||||
|
||||
@ -29,6 +29,7 @@ properties:
|
||||
- qcom,rpmcc-mdm9607
|
||||
- qcom,rpmcc-msm8226
|
||||
- qcom,rpmcc-msm8660
|
||||
- qcom,rpmcc-msm8909
|
||||
- qcom,rpmcc-msm8916
|
||||
- qcom,rpmcc-msm8936
|
||||
- qcom,rpmcc-msm8953
|
||||
@ -43,6 +44,7 @@ properties:
|
||||
- qcom,rpmcc-sdm660
|
||||
- qcom,rpmcc-sm6115
|
||||
- qcom,rpmcc-sm6125
|
||||
- qcom,rpmcc-sm6375
|
||||
- const: qcom,rpmcc
|
||||
|
||||
'#clock-cells':
|
||||
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
- qcom,sc8280xp-rpmh-clk
|
||||
- qcom,sdm670-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sdx65-rpmh-clk
|
||||
|
||||
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock Controller for SM6115
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks and
|
||||
power domains on SM6115.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,sm6115-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6115-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board sleep clock
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: GPLL0 DISP DIV clock from GCC
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
|
||||
clock-controller@5f00000 {
|
||||
compatible = "qcom,sm6115-dispcc";
|
||||
reg = <0x5f00000 0x20000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
52
Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml
Normal file
52
Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6375
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM6375
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,sm6375-gcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6375-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO Active-Only source
|
||||
- description: Sleep clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@1400000 {
|
||||
compatible = "qcom,sm6375-gcc";
|
||||
reg = <0x01400000 0x1f0000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
|
||||
<&sleep_clk>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller for SM8450
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SM8450.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,sm8450-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-dispcc
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: Display's AHB clock
|
||||
- description: sleep clock
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY1
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY0
|
||||
- description: VCO DIV clock from DP PHY0
|
||||
- description: Link clock from DP PHY1
|
||||
- description: VCO DIV clock from DP PHY1
|
||||
- description: Link clock from DP PHY2
|
||||
- description: VCO DIV clock from DP PHY2
|
||||
- description: Link clock from DP PHY3
|
||||
- description: VCO DIV clock from DP PHY3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm8450-dispcc";
|
||||
reg = <0x0af00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
power-domains = <&rpmhpd SM8450_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
...
|
||||
@ -47,7 +47,6 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
@ -64,7 +63,6 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
|
||||
@ -24,7 +24,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
|
||||
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
|
||||
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-cpg # RZ/V2L
|
||||
- renesas,r9a09g011-cpg # RZ/V2M
|
||||
|
||||
@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Versaclock7 Programmable Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Alex Helms <alexander.helms.jy@renesas.com>
|
||||
|
||||
description: |
|
||||
Renesas Versaclock7 is a family of configurable clock generator and
|
||||
jitter attenuator ICs with fractional and integer dividers.
|
||||
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,rc21008a
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: External crystal or oscillator
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xin
|
||||
|
||||
required:
|
||||
- '#clock-cells'
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
vc7_xin: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <49152000>;
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
reg = <0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vc7: clock-controller@9 {
|
||||
compatible = "renesas,rc21008a";
|
||||
reg = <0x9>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&vc7_xin>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#
|
||||
|
||||
@ -1,58 +0,0 @@
|
||||
* Rockchip RK3126/RK3128 Clock and Reset Unit
|
||||
|
||||
The RK3126/RK3128 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
|
||||
"rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
|
||||
"rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: cru@20000000 {
|
||||
compatible = "rockchip,rk3128-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart2: serial@20068000 {
|
||||
compatible = "rockchip,serial";
|
||||
reg = <0x20068000 0x100>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "sclk_uart", "pclk_uart";
|
||||
};
|
||||
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3126/RK3128 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3126-cru
|
||||
- rockchip,rk3128-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xin24m
|
||||
- enum:
|
||||
- ext_i2s
|
||||
- gmac_clkin
|
||||
- enum:
|
||||
- ext_i2s
|
||||
- gmac_clkin
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@20000000 {
|
||||
compatible = "rockchip,rk3128-cru";
|
||||
reg = <0x20000000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RV1126 Clock and Reset Unit
|
||||
|
||||
maintainers:
|
||||
- Jagan Teki <jagan@edgeble.ai>
|
||||
- Finley Xiao <finley.xiao@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description:
|
||||
The RV1126 clock controller generates the clock and also implements a
|
||||
reset controller for SoC peripherals.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rv1126-cru
|
||||
- rockchip,rv1126-pmucru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff490000 {
|
||||
compatible = "rockchip,rv1126-cru";
|
||||
reg = <0xff490000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -34,7 +34,6 @@ properties:
|
||||
const: 1
|
||||
|
||||
clock-output-names:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
description: Names for AP, CP and BT clocks.
|
||||
|
||||
|
||||
@ -10,7 +10,7 @@ will be controlled instead and the corresponding hw-ops for
|
||||
that is used.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
@ -9,7 +9,7 @@ companion clock finding (match corresponding functional gate
|
||||
clock) and hardware autoidle enable / disable.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
|
||||
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Xilinx clocking wizard
|
||||
|
||||
maintainers:
|
||||
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
|
||||
|
||||
description:
|
||||
The clocking wizard is a soft ip clocking block of Xilinx versal. It
|
||||
reads required input clock frequencies from the devicetree and acts as clock
|
||||
clock output.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- xlnx,clocking-wizard
|
||||
- xlnx,clocking-wizard-v5.2
|
||||
- xlnx,clocking-wizard-v6.0
|
||||
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: clock input
|
||||
- description: axi clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: clk_in1
|
||||
- const: s_axi_aclk
|
||||
|
||||
|
||||
xlnx,speed-grade:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 3]
|
||||
description:
|
||||
Speed grade of the device. Higher the speed grade faster is the FPGA device.
|
||||
|
||||
xlnx,nr-outputs:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 8
|
||||
description:
|
||||
Number of outputs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- xlnx,speed-grade
|
||||
- xlnx,nr-outputs
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@b0000000 {
|
||||
compatible = "xlnx,clocking-wizard";
|
||||
reg = <0xb0000000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
xlnx,speed-grade = <1>;
|
||||
xlnx,nr-outputs = <6>;
|
||||
clock-names = "clk_in1", "s_axi_aclk";
|
||||
clocks = <&clkc 15>, <&clkc 15>;
|
||||
};
|
||||
...
|
||||
@ -266,7 +266,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clk/lochnagar.h>
|
||||
#include <dt-bindings/clock/lochnagar.h>
|
||||
#include <dt-bindings/pinctrl/lochnagar.h>
|
||||
i2c@e0004000 {
|
||||
#address-cells = <1>;
|
||||
|
||||
12
MAINTAINERS
12
MAINTAINERS
@ -4982,7 +4982,7 @@ F: drivers/hwmon/lochnagar-hwmon.c
|
||||
F: drivers/mfd/lochnagar-i2c.c
|
||||
F: drivers/pinctrl/cirrus/pinctrl-lochnagar.c
|
||||
F: drivers/regulator/lochnagar-regulator.c
|
||||
F: include/dt-bindings/clk/lochnagar.h
|
||||
F: include/dt-bindings/clock/lochnagar.h
|
||||
F: include/dt-bindings/pinctrl/lochnagar.h
|
||||
F: include/linux/mfd/lochnagar*
|
||||
F: sound/soc/codecs/lochnagar-sc.c
|
||||
@ -17553,6 +17553,12 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
|
||||
F: drivers/mtd/nand/raw/renesas-nand-controller.c
|
||||
|
||||
RENESAS VERSACLOCK 7 CLOCK DRIVER
|
||||
M: Alex Helms <alexander.helms.jy@renesas.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
|
||||
F: drivers/clk/clk-versaclock7.c
|
||||
|
||||
RESET CONTROLLER FRAMEWORK
|
||||
M: Philipp Zabel <p.zabel@pengutronix.de>
|
||||
S: Maintained
|
||||
@ -17654,6 +17660,7 @@ F: drivers/clk/microchip/clk-mpfs.c
|
||||
F: drivers/i2c/busses/i2c-microchip-core.c
|
||||
F: drivers/mailbox/mailbox-mpfs.c
|
||||
F: drivers/pci/controller/pcie-microchip-host.c
|
||||
F: drivers/reset/reset-mpfs.c
|
||||
F: drivers/rtc/rtc-mpfs.c
|
||||
F: drivers/soc/microchip/
|
||||
F: drivers/spi/spi-microchip-core-qspi.c
|
||||
@ -18172,12 +18179,14 @@ Q: https://patchwork.linuxtv.org/project/linux-media/list/
|
||||
F: drivers/media/platform/samsung/exynos4-is/
|
||||
|
||||
SAMSUNG SOC CLOCK DRIVERS
|
||||
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
M: Tomasz Figa <tomasz.figa@gmail.com>
|
||||
M: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
R: Alim Akhtar <alim.akhtar@samsung.com>
|
||||
L: linux-samsung-soc@vger.kernel.org
|
||||
S: Supported
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
|
||||
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
|
||||
F: Documentation/devicetree/bindings/clock/samsung,s3c*
|
||||
@ -20462,6 +20471,7 @@ R: Sekhar Nori <nsekhar@ti.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/clock/ti/davinci/
|
||||
F: drivers/clk/davinci/
|
||||
F: include/linux/clk/davinci.h
|
||||
|
||||
TI DAVINCI SERIES GPIO DRIVER
|
||||
M: Keerthy <j-keerthy@ti.com>
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
#include <dt-bindings/clock/versaclock.h>
|
||||
|
||||
/ {
|
||||
backlight_lvds: backlight-lvds {
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
#include <dt-bindings/clock/versaclock.h>
|
||||
|
||||
/ {
|
||||
memory@48000000 {
|
||||
|
||||
@ -249,7 +249,7 @@ config COMMON_CLK_GEMINI
|
||||
platform, also known as SL3516 or CS3516.
|
||||
|
||||
config COMMON_CLK_LAN966X
|
||||
bool "Generic Clock Controller driver for LAN966X SoC"
|
||||
tristate "Generic Clock Controller driver for LAN966X SoC"
|
||||
depends on HAS_IOMEM
|
||||
depends on OF
|
||||
depends on SOC_LAN966 || COMPILE_TEST
|
||||
@ -377,6 +377,15 @@ config COMMON_CLK_VC5
|
||||
This driver supports the IDT VersaClock 5 and VersaClock 6
|
||||
programmable clock generators.
|
||||
|
||||
config COMMON_CLK_VC7
|
||||
tristate "Clock driver for Renesas Versaclock 7 devices"
|
||||
depends on I2C
|
||||
depends on OF
|
||||
select REGMAP_I2C
|
||||
help
|
||||
Renesas Versaclock7 is a family of configurable clock generator
|
||||
and jitter attenuator ICs with fractional and integer dividers.
|
||||
|
||||
config COMMON_CLK_STM32MP135
|
||||
def_bool COMMON_CLK && MACH_STM32MP13
|
||||
help
|
||||
|
||||
@ -73,6 +73,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
|
||||
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
|
||||
obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
|
||||
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
|
||||
obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
|
||||
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
|
||||
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
|
||||
|
||||
|
||||
@ -33,8 +33,11 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
|
||||
const char *name = np->name;
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -56,8 +59,11 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
|
||||
const char *name = np->name;
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -79,8 +85,11 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
|
||||
const char *name = np->name;
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -120,7 +129,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
|
||||
struct clk_hw *hw;
|
||||
unsigned int num_parents;
|
||||
const char *parent_names[GENERATED_SOURCE_MAX];
|
||||
struct device_node *gcknp;
|
||||
struct device_node *gcknp, *parent_np;
|
||||
struct clk_range range = CLK_RANGE(0, 0);
|
||||
struct regmap *regmap;
|
||||
|
||||
@ -134,7 +143,9 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
|
||||
if (!num || num > PERIPHERAL_MAX)
|
||||
return;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -180,8 +191,11 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
|
||||
const char *name = np->name;
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -243,12 +257,15 @@ static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
bool bypass;
|
||||
struct device_node *parent_np;
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
bypass = of_property_read_bool(np, "atmel,osc-bypass");
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -268,12 +285,15 @@ static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
|
||||
u32 accuracy = 0;
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
of_property_read_u32(np, "clock-frequency", &frequency);
|
||||
of_property_read_u32(np, "clock-accuracy", &accuracy);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -292,11 +312,14 @@ static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
|
||||
const char *parent_name;
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -316,13 +339,16 @@ static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
|
||||
unsigned int num_parents;
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
num_parents = of_clk_get_parent_count(np);
|
||||
if (num_parents == 0 || num_parents > 2)
|
||||
return;
|
||||
|
||||
of_clk_parent_fill(np, parent_names, num_parents);
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -373,6 +399,7 @@ of_at91_clk_master_setup(struct device_node *np,
|
||||
const char *name = np->name;
|
||||
struct clk_master_characteristics *characteristics;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
num_parents = of_clk_get_parent_count(np);
|
||||
if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
|
||||
@ -386,7 +413,9 @@ of_at91_clk_master_setup(struct device_node *np,
|
||||
if (!characteristics)
|
||||
return;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -433,6 +462,7 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type)
|
||||
const char *name;
|
||||
struct device_node *periphclknp;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
if (!parent_name)
|
||||
@ -442,7 +472,9 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type)
|
||||
if (!num || num > PERIPHERAL_MAX)
|
||||
return;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -601,6 +633,7 @@ of_at91_clk_pll_setup(struct device_node *np,
|
||||
struct regmap *regmap;
|
||||
const char *parent_name;
|
||||
const char *name = np->name;
|
||||
struct device_node *parent_np;
|
||||
struct clk_pll_characteristics *characteristics;
|
||||
|
||||
if (of_property_read_u32(np, "reg", &id))
|
||||
@ -610,7 +643,9 @@ of_at91_clk_pll_setup(struct device_node *np,
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -665,12 +700,15 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
|
||||
const char *parent_name;
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -694,7 +732,7 @@ of_at91_clk_prog_setup(struct device_node *np,
|
||||
unsigned int num_parents;
|
||||
const char *parent_names[PROG_SOURCE_MAX];
|
||||
const char *name;
|
||||
struct device_node *progclknp;
|
||||
struct device_node *progclknp, *parent_np;
|
||||
struct regmap *regmap;
|
||||
|
||||
num_parents = of_clk_get_parent_count(np);
|
||||
@ -707,7 +745,9 @@ of_at91_clk_prog_setup(struct device_node *np,
|
||||
if (!num || num > (PROG_ID_MAX + 1))
|
||||
return;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -756,13 +796,16 @@ static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
|
||||
unsigned int num_parents;
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
num_parents = of_clk_get_parent_count(np);
|
||||
if (num_parents != 2)
|
||||
return;
|
||||
|
||||
of_clk_parent_fill(np, parent_names, num_parents);
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -788,6 +831,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
|
||||
const char *parent_names[SMD_SOURCE_MAX];
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
num_parents = of_clk_get_parent_count(np);
|
||||
if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
|
||||
@ -797,7 +841,9 @@ static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -818,7 +864,7 @@ static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
|
||||
u32 id;
|
||||
struct clk_hw *hw;
|
||||
const char *name;
|
||||
struct device_node *sysclknp;
|
||||
struct device_node *sysclknp, *parent_np;
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
|
||||
@ -826,7 +872,9 @@ static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
|
||||
if (num > (SYSTEM_MAX_ID + 1))
|
||||
return;
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -859,6 +907,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
|
||||
const char *parent_names[USB_SOURCE_MAX];
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
num_parents = of_clk_get_parent_count(np);
|
||||
if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
|
||||
@ -868,7 +917,9 @@ static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -888,6 +939,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
|
||||
const char *parent_name;
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
if (!parent_name)
|
||||
@ -895,7 +947,9 @@ static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
|
||||
@ -915,6 +969,7 @@ static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
|
||||
const char *name = np->name;
|
||||
u32 divisors[4] = {0, 0, 0, 0};
|
||||
struct regmap *regmap;
|
||||
struct device_node *parent_np;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
if (!parent_name)
|
||||
@ -926,7 +981,9 @@ static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap))
|
||||
return;
|
||||
hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
|
||||
@ -946,12 +1003,15 @@ static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
|
||||
const char *parent_name;
|
||||
const char *name = np->name;
|
||||
struct regmap *regmap_pmc, *regmap_sfr;
|
||||
struct device_node *parent_np;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
|
||||
of_property_read_string(np, "clock-output-names", &name);
|
||||
|
||||
regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap_pmc = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap_pmc))
|
||||
return;
|
||||
|
||||
|
||||
@ -120,6 +120,16 @@ static const struct {
|
||||
struct clk_range r;
|
||||
int chg_pid;
|
||||
} sama5d2_gck[] = {
|
||||
{ .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
|
||||
{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
|
||||
{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
|
||||
{ .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
|
||||
|
||||
@ -29,7 +29,6 @@ config CLK_BT1_CCU_PLL
|
||||
|
||||
config CLK_BT1_CCU_DIV
|
||||
bool "Baikal-T1 CCU Dividers support"
|
||||
select RESET_CONTROLLER
|
||||
select MFD_SYSCON
|
||||
default MIPS_BAIKAL_T1
|
||||
help
|
||||
@ -39,4 +38,15 @@ config CLK_BT1_CCU_DIV
|
||||
either gateable or ungateable. Some of the CCU dividers can be as well
|
||||
used to reset the domains they're supplying clock to.
|
||||
|
||||
config CLK_BT1_CCU_RST
|
||||
bool "Baikal-T1 CCU Resets support"
|
||||
select RESET_CONTROLLER
|
||||
select MFD_SYSCON
|
||||
default MIPS_BAIKAL_T1
|
||||
help
|
||||
Enable this to support the CCU reset blocks responsible for the
|
||||
AXI-bus and some subsystems reset. These are mainly the
|
||||
self-deasserted reset controls but there are several lines which
|
||||
can be directly asserted/de-asserted (PCIe and DDR sub-domains).
|
||||
|
||||
endif
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
|
||||
obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
|
||||
obj-$(CONFIG_CLK_BT1_CCU_RST) += ccu-rst.o
|
||||
|
||||
@ -34,9 +34,9 @@
|
||||
#define CCU_DIV_CTL_CLKDIV_MASK(_width) \
|
||||
GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
|
||||
#define CCU_DIV_CTL_LOCK_SHIFTED BIT(27)
|
||||
#define CCU_DIV_CTL_GATE_REF_BUF BIT(28)
|
||||
#define CCU_DIV_CTL_LOCK_NORMAL BIT(31)
|
||||
|
||||
#define CCU_DIV_RST_DELAY_US 1
|
||||
#define CCU_DIV_LOCK_CHECK_RETRIES 50
|
||||
|
||||
#define CCU_DIV_CLKDIV_MIN 0
|
||||
@ -170,6 +170,40 @@ static int ccu_div_gate_is_enabled(struct clk_hw *hw)
|
||||
return !!(val & CCU_DIV_CTL_EN);
|
||||
}
|
||||
|
||||
static int ccu_div_buf_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
CCU_DIV_CTL_GATE_REF_BUF, 0);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ccu_div_buf_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
CCU_DIV_CTL_GATE_REF_BUF, CCU_DIV_CTL_GATE_REF_BUF);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
}
|
||||
|
||||
static int ccu_div_buf_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
u32 val = 0;
|
||||
|
||||
regmap_read(div->sys_regs, div->reg_ctl, &val);
|
||||
|
||||
return !(val & CCU_DIV_CTL_GATE_REF_BUF);
|
||||
}
|
||||
|
||||
static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
@ -288,24 +322,6 @@ static int ccu_div_fixed_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ccu_div_reset_domain(struct ccu_div *div)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (!div || !(div->features & CCU_DIV_RESET_DOMAIN))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&div->lock, flags);
|
||||
regmap_update_bits(div->sys_regs, div->reg_ctl,
|
||||
CCU_DIV_CTL_RST, CCU_DIV_CTL_RST);
|
||||
spin_unlock_irqrestore(&div->lock, flags);
|
||||
|
||||
/* The next delay must be enough to cover all the resets. */
|
||||
udelay(CCU_DIV_RST_DELAY_US);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
struct ccu_div_dbgfs_bit {
|
||||
@ -323,6 +339,7 @@ static const struct ccu_div_dbgfs_bit ccu_div_bits[] = {
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN),
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST),
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV),
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_buf", CCU_DIV_CTL_GATE_REF_BUF),
|
||||
CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL)
|
||||
};
|
||||
|
||||
@ -441,6 +458,9 @@ static void ccu_div_var_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!strcmp("div_buf", name))
|
||||
continue;
|
||||
|
||||
bits[didx] = ccu_div_bits[bidx];
|
||||
bits[didx].div = div;
|
||||
|
||||
@ -477,6 +497,21 @@ static void ccu_div_gate_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
&ccu_div_dbgfs_fixed_clkdiv_fops);
|
||||
}
|
||||
|
||||
static void ccu_div_buf_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
struct ccu_div_dbgfs_bit *bit;
|
||||
|
||||
bit = kmalloc(sizeof(*bit), GFP_KERNEL);
|
||||
if (!bit)
|
||||
return;
|
||||
|
||||
*bit = ccu_div_bits[3];
|
||||
bit->div = div;
|
||||
debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
|
||||
&ccu_div_dbgfs_bit_fops);
|
||||
}
|
||||
|
||||
static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
struct ccu_div *div = to_ccu_div(hw);
|
||||
@ -489,6 +524,7 @@ static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
|
||||
#define ccu_div_var_debug_init NULL
|
||||
#define ccu_div_gate_debug_init NULL
|
||||
#define ccu_div_buf_debug_init NULL
|
||||
#define ccu_div_fixed_debug_init NULL
|
||||
|
||||
#endif /* !CONFIG_DEBUG_FS */
|
||||
@ -520,6 +556,13 @@ static const struct clk_ops ccu_div_gate_ops = {
|
||||
.debug_init = ccu_div_gate_debug_init
|
||||
};
|
||||
|
||||
static const struct clk_ops ccu_div_buf_ops = {
|
||||
.enable = ccu_div_buf_enable,
|
||||
.disable = ccu_div_buf_disable,
|
||||
.is_enabled = ccu_div_buf_is_enabled,
|
||||
.debug_init = ccu_div_buf_debug_init
|
||||
};
|
||||
|
||||
static const struct clk_ops ccu_div_fixed_ops = {
|
||||
.recalc_rate = ccu_div_fixed_recalc_rate,
|
||||
.round_rate = ccu_div_fixed_round_rate,
|
||||
@ -566,6 +609,8 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
|
||||
} else if (div_init->type == CCU_DIV_GATE) {
|
||||
hw_init.ops = &ccu_div_gate_ops;
|
||||
div->divider = div_init->divider;
|
||||
} else if (div_init->type == CCU_DIV_BUF) {
|
||||
hw_init.ops = &ccu_div_buf_ops;
|
||||
} else if (div_init->type == CCU_DIV_FIXED) {
|
||||
hw_init.ops = &ccu_div_fixed_ops;
|
||||
div->divider = div_init->divider;
|
||||
@ -579,6 +624,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
|
||||
goto err_free_div;
|
||||
}
|
||||
parent_data.fw_name = div_init->parent_name;
|
||||
parent_data.name = div_init->parent_name;
|
||||
hw_init.parent_data = &parent_data;
|
||||
hw_init.num_parents = 1;
|
||||
|
||||
|
||||
@ -13,15 +13,26 @@
|
||||
#include <linux/bits.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
/*
|
||||
* CCU Divider private clock IDs
|
||||
* @CCU_SYS_SATA_CLK: CCU SATA internal clock
|
||||
* @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
|
||||
*/
|
||||
#define CCU_SYS_SATA_CLK -1
|
||||
#define CCU_SYS_XGMAC_CLK -2
|
||||
|
||||
/*
|
||||
* CCU Divider private flags
|
||||
* @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
|
||||
* possible.
|
||||
* @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
|
||||
* It can be 0 though, which is functionally the same.
|
||||
* @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
|
||||
* It can be either 0 or greater than 3.
|
||||
* @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
|
||||
* @CCU_DIV_RESET_DOMAIN: Provide reset clock domain method.
|
||||
* @CCU_DIV_RESET_DOMAIN: There is a clock domain reset handle.
|
||||
*/
|
||||
#define CCU_DIV_BASIC BIT(0)
|
||||
#define CCU_DIV_SKIP_ONE BIT(1)
|
||||
#define CCU_DIV_SKIP_ONE_TO_THREE BIT(2)
|
||||
#define CCU_DIV_LOCK_SHIFTED BIT(3)
|
||||
@ -31,11 +42,13 @@
|
||||
* enum ccu_div_type - CCU Divider types
|
||||
* @CCU_DIV_VAR: Clocks gate with variable divider.
|
||||
* @CCU_DIV_GATE: Clocks gate with fixed divider.
|
||||
* @CCU_DIV_BUF: Clock gate with no divider.
|
||||
* @CCU_DIV_FIXED: Ungateable clock with fixed divider.
|
||||
*/
|
||||
enum ccu_div_type {
|
||||
CCU_DIV_VAR,
|
||||
CCU_DIV_GATE,
|
||||
CCU_DIV_BUF,
|
||||
CCU_DIV_FIXED
|
||||
};
|
||||
|
||||
@ -105,6 +118,4 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *init);
|
||||
|
||||
void ccu_div_hw_unregister(struct ccu_div *div);
|
||||
|
||||
int ccu_div_reset_domain(struct ccu_div *div);
|
||||
|
||||
#endif /* __CLK_BT1_CCU_DIV_H__ */
|
||||
|
||||
@ -13,6 +13,12 @@
|
||||
#include <linux/bits.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
/*
|
||||
* CCU PLL private flags
|
||||
* @CCU_PLL_BASIC: Basic PLL required by the kernel as early as possible.
|
||||
*/
|
||||
#define CCU_PLL_BASIC BIT(0)
|
||||
|
||||
/*
|
||||
* struct ccu_pll_init_data - CCU PLL initialization data
|
||||
* @id: Clock private identifier.
|
||||
@ -22,6 +28,7 @@
|
||||
* @sys_regs: Baikal-T1 System Controller registers map.
|
||||
* @np: Pointer to the node describing the CCU PLLs.
|
||||
* @flags: PLL clock flags.
|
||||
* @features: PLL private features.
|
||||
*/
|
||||
struct ccu_pll_init_data {
|
||||
unsigned int id;
|
||||
@ -31,6 +38,7 @@ struct ccu_pll_init_data {
|
||||
struct regmap *sys_regs;
|
||||
struct device_node *np;
|
||||
unsigned long flags;
|
||||
unsigned long features;
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
217
drivers/clk/baikal-t1/ccu-rst.c
Normal file
217
drivers/clk/baikal-t1/ccu-rst.c
Normal file
@ -0,0 +1,217 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Authors:
|
||||
* Serge Semin <Sergey.Semin@baikalelectronics.ru>
|
||||
*
|
||||
* Baikal-T1 CCU Resets interface driver
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "bt1-ccu-rst: " fmt
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <dt-bindings/reset/bt1-ccu.h>
|
||||
|
||||
#include "ccu-rst.h"
|
||||
|
||||
#define CCU_AXI_MAIN_BASE 0x030
|
||||
#define CCU_AXI_DDR_BASE 0x034
|
||||
#define CCU_AXI_SATA_BASE 0x038
|
||||
#define CCU_AXI_GMAC0_BASE 0x03C
|
||||
#define CCU_AXI_GMAC1_BASE 0x040
|
||||
#define CCU_AXI_XGMAC_BASE 0x044
|
||||
#define CCU_AXI_PCIE_M_BASE 0x048
|
||||
#define CCU_AXI_PCIE_S_BASE 0x04C
|
||||
#define CCU_AXI_USB_BASE 0x050
|
||||
#define CCU_AXI_HWA_BASE 0x054
|
||||
#define CCU_AXI_SRAM_BASE 0x058
|
||||
|
||||
#define CCU_SYS_DDR_BASE 0x02c
|
||||
#define CCU_SYS_SATA_REF_BASE 0x060
|
||||
#define CCU_SYS_APB_BASE 0x064
|
||||
#define CCU_SYS_PCIE_BASE 0x144
|
||||
|
||||
#define CCU_RST_DELAY_US 1
|
||||
|
||||
#define CCU_RST_TRIG(_base, _ofs) \
|
||||
{ \
|
||||
.type = CCU_RST_TRIG, \
|
||||
.base = _base, \
|
||||
.mask = BIT(_ofs), \
|
||||
}
|
||||
|
||||
#define CCU_RST_DIR(_base, _ofs) \
|
||||
{ \
|
||||
.type = CCU_RST_DIR, \
|
||||
.base = _base, \
|
||||
.mask = BIT(_ofs), \
|
||||
}
|
||||
|
||||
struct ccu_rst_info {
|
||||
enum ccu_rst_type type;
|
||||
unsigned int base;
|
||||
unsigned int mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* Each AXI-bus clock divider is equipped with the corresponding clock-consumer
|
||||
* domain reset (it's self-deasserted reset control).
|
||||
*/
|
||||
static const struct ccu_rst_info axi_rst_info[] = {
|
||||
[CCU_AXI_MAIN_RST] = CCU_RST_TRIG(CCU_AXI_MAIN_BASE, 1),
|
||||
[CCU_AXI_DDR_RST] = CCU_RST_TRIG(CCU_AXI_DDR_BASE, 1),
|
||||
[CCU_AXI_SATA_RST] = CCU_RST_TRIG(CCU_AXI_SATA_BASE, 1),
|
||||
[CCU_AXI_GMAC0_RST] = CCU_RST_TRIG(CCU_AXI_GMAC0_BASE, 1),
|
||||
[CCU_AXI_GMAC1_RST] = CCU_RST_TRIG(CCU_AXI_GMAC1_BASE, 1),
|
||||
[CCU_AXI_XGMAC_RST] = CCU_RST_TRIG(CCU_AXI_XGMAC_BASE, 1),
|
||||
[CCU_AXI_PCIE_M_RST] = CCU_RST_TRIG(CCU_AXI_PCIE_M_BASE, 1),
|
||||
[CCU_AXI_PCIE_S_RST] = CCU_RST_TRIG(CCU_AXI_PCIE_S_BASE, 1),
|
||||
[CCU_AXI_USB_RST] = CCU_RST_TRIG(CCU_AXI_USB_BASE, 1),
|
||||
[CCU_AXI_HWA_RST] = CCU_RST_TRIG(CCU_AXI_HWA_BASE, 1),
|
||||
[CCU_AXI_SRAM_RST] = CCU_RST_TRIG(CCU_AXI_SRAM_BASE, 1),
|
||||
};
|
||||
|
||||
/*
|
||||
* SATA reference clock domain and APB-bus domain are connected with the
|
||||
* sefl-deasserted reset control, which can be activated via the corresponding
|
||||
* clock divider register. DDR and PCIe sub-domains can be reset with directly
|
||||
* controlled reset signals. Resetting the DDR controller though won't end up
|
||||
* well while the Linux kernel is working.
|
||||
*/
|
||||
static const struct ccu_rst_info sys_rst_info[] = {
|
||||
[CCU_SYS_SATA_REF_RST] = CCU_RST_TRIG(CCU_SYS_SATA_REF_BASE, 1),
|
||||
[CCU_SYS_APB_RST] = CCU_RST_TRIG(CCU_SYS_APB_BASE, 1),
|
||||
[CCU_SYS_DDR_FULL_RST] = CCU_RST_DIR(CCU_SYS_DDR_BASE, 1),
|
||||
[CCU_SYS_DDR_INIT_RST] = CCU_RST_DIR(CCU_SYS_DDR_BASE, 2),
|
||||
[CCU_SYS_PCIE_PCS_PHY_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 0),
|
||||
[CCU_SYS_PCIE_PIPE0_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 4),
|
||||
[CCU_SYS_PCIE_CORE_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 8),
|
||||
[CCU_SYS_PCIE_PWR_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 9),
|
||||
[CCU_SYS_PCIE_STICKY_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 10),
|
||||
[CCU_SYS_PCIE_NSTICKY_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 11),
|
||||
[CCU_SYS_PCIE_HOT_RST] = CCU_RST_DIR(CCU_SYS_PCIE_BASE, 12),
|
||||
};
|
||||
|
||||
static int ccu_rst_reset(struct reset_controller_dev *rcdev, unsigned long idx)
|
||||
{
|
||||
struct ccu_rst *rst = to_ccu_rst(rcdev);
|
||||
const struct ccu_rst_info *info = &rst->rsts_info[idx];
|
||||
|
||||
if (info->type != CCU_RST_TRIG)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
regmap_update_bits(rst->sys_regs, info->base, info->mask, info->mask);
|
||||
|
||||
/* The next delay must be enough to cover all the resets. */
|
||||
udelay(CCU_RST_DELAY_US);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ccu_rst_set(struct reset_controller_dev *rcdev,
|
||||
unsigned long idx, bool high)
|
||||
{
|
||||
struct ccu_rst *rst = to_ccu_rst(rcdev);
|
||||
const struct ccu_rst_info *info = &rst->rsts_info[idx];
|
||||
|
||||
if (info->type != CCU_RST_DIR)
|
||||
return high ? -EOPNOTSUPP : 0;
|
||||
|
||||
return regmap_update_bits(rst->sys_regs, info->base,
|
||||
info->mask, high ? info->mask : 0);
|
||||
}
|
||||
|
||||
static int ccu_rst_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long idx)
|
||||
{
|
||||
return ccu_rst_set(rcdev, idx, true);
|
||||
}
|
||||
|
||||
static int ccu_rst_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long idx)
|
||||
{
|
||||
return ccu_rst_set(rcdev, idx, false);
|
||||
}
|
||||
|
||||
static int ccu_rst_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long idx)
|
||||
{
|
||||
struct ccu_rst *rst = to_ccu_rst(rcdev);
|
||||
const struct ccu_rst_info *info = &rst->rsts_info[idx];
|
||||
u32 val;
|
||||
|
||||
if (info->type != CCU_RST_DIR)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
regmap_read(rst->sys_regs, info->base, &val);
|
||||
|
||||
return !!(val & info->mask);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops ccu_rst_ops = {
|
||||
.reset = ccu_rst_reset,
|
||||
.assert = ccu_rst_assert,
|
||||
.deassert = ccu_rst_deassert,
|
||||
.status = ccu_rst_status,
|
||||
};
|
||||
|
||||
struct ccu_rst *ccu_rst_hw_register(const struct ccu_rst_init_data *rst_init)
|
||||
{
|
||||
struct ccu_rst *rst;
|
||||
int ret;
|
||||
|
||||
if (!rst_init)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
rst = kzalloc(sizeof(*rst), GFP_KERNEL);
|
||||
if (!rst)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
rst->sys_regs = rst_init->sys_regs;
|
||||
if (of_device_is_compatible(rst_init->np, "baikal,bt1-ccu-axi")) {
|
||||
rst->rcdev.nr_resets = ARRAY_SIZE(axi_rst_info);
|
||||
rst->rsts_info = axi_rst_info;
|
||||
} else if (of_device_is_compatible(rst_init->np, "baikal,bt1-ccu-sys")) {
|
||||
rst->rcdev.nr_resets = ARRAY_SIZE(sys_rst_info);
|
||||
rst->rsts_info = sys_rst_info;
|
||||
} else {
|
||||
pr_err("Incompatible DT node '%s' specified\n",
|
||||
of_node_full_name(rst_init->np));
|
||||
ret = -EINVAL;
|
||||
goto err_kfree_rst;
|
||||
}
|
||||
|
||||
rst->rcdev.owner = THIS_MODULE;
|
||||
rst->rcdev.ops = &ccu_rst_ops;
|
||||
rst->rcdev.of_node = rst_init->np;
|
||||
|
||||
ret = reset_controller_register(&rst->rcdev);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register '%s' reset controller\n",
|
||||
of_node_full_name(rst_init->np));
|
||||
goto err_kfree_rst;
|
||||
}
|
||||
|
||||
return rst;
|
||||
|
||||
err_kfree_rst:
|
||||
kfree(rst);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
void ccu_rst_hw_unregister(struct ccu_rst *rst)
|
||||
{
|
||||
reset_controller_unregister(&rst->rcdev);
|
||||
|
||||
kfree(rst);
|
||||
}
|
||||
67
drivers/clk/baikal-t1/ccu-rst.h
Normal file
67
drivers/clk/baikal-t1/ccu-rst.h
Normal file
@ -0,0 +1,67 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
|
||||
*
|
||||
* Baikal-T1 CCU Resets interface driver
|
||||
*/
|
||||
#ifndef __CLK_BT1_CCU_RST_H__
|
||||
#define __CLK_BT1_CCU_RST_H__
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset-controller.h>
|
||||
|
||||
struct ccu_rst_info;
|
||||
|
||||
/*
|
||||
* enum ccu_rst_type - CCU Reset types
|
||||
* @CCU_RST_TRIG: Self-deasserted reset signal.
|
||||
* @CCU_RST_DIR: Directly controlled reset signal.
|
||||
*/
|
||||
enum ccu_rst_type {
|
||||
CCU_RST_TRIG,
|
||||
CCU_RST_DIR,
|
||||
};
|
||||
|
||||
/*
|
||||
* struct ccu_rst_init_data - CCU Resets initialization data
|
||||
* @sys_regs: Baikal-T1 System Controller registers map.
|
||||
* @np: Pointer to the node with the System CCU block.
|
||||
*/
|
||||
struct ccu_rst_init_data {
|
||||
struct regmap *sys_regs;
|
||||
struct device_node *np;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct ccu_rst - CCU Reset descriptor
|
||||
* @rcdev: Reset controller descriptor.
|
||||
* @sys_regs: Baikal-T1 System Controller registers map.
|
||||
* @rsts_info: Reset flag info (base address and mask).
|
||||
*/
|
||||
struct ccu_rst {
|
||||
struct reset_controller_dev rcdev;
|
||||
struct regmap *sys_regs;
|
||||
const struct ccu_rst_info *rsts_info;
|
||||
};
|
||||
#define to_ccu_rst(_rcdev) container_of(_rcdev, struct ccu_rst, rcdev)
|
||||
|
||||
#ifdef CONFIG_CLK_BT1_CCU_RST
|
||||
|
||||
struct ccu_rst *ccu_rst_hw_register(const struct ccu_rst_init_data *init);
|
||||
|
||||
void ccu_rst_hw_unregister(struct ccu_rst *rst);
|
||||
|
||||
#else
|
||||
|
||||
static inline
|
||||
struct ccu_rst *ccu_rst_hw_register(const struct ccu_rst_init_data *init)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void ccu_rst_hw_unregister(struct ccu_rst *rst) {}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __CLK_BT1_CCU_RST_H__ */
|
||||
@ -12,6 +12,7 @@
|
||||
#define pr_fmt(fmt) "bt1-ccu-div: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
@ -24,9 +25,9 @@
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
#include <dt-bindings/reset/bt1-ccu.h>
|
||||
|
||||
#include "ccu-div.h"
|
||||
#include "ccu-rst.h"
|
||||
|
||||
#define CCU_AXI_MAIN_BASE 0x030
|
||||
#define CCU_AXI_DDR_BASE 0x034
|
||||
@ -76,6 +77,16 @@
|
||||
.divider = _divider \
|
||||
}
|
||||
|
||||
#define CCU_DIV_BUF_INFO(_id, _name, _pname, _base, _flags) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.base = _base, \
|
||||
.type = CCU_DIV_BUF, \
|
||||
.flags = _flags \
|
||||
}
|
||||
|
||||
#define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
@ -85,12 +96,6 @@
|
||||
.divider = _divider \
|
||||
}
|
||||
|
||||
#define CCU_DIV_RST_MAP(_rst_id, _clk_id) \
|
||||
{ \
|
||||
.rst_id = _rst_id, \
|
||||
.clk_id = _clk_id \
|
||||
}
|
||||
|
||||
struct ccu_div_info {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
@ -105,11 +110,6 @@ struct ccu_div_info {
|
||||
unsigned long features;
|
||||
};
|
||||
|
||||
struct ccu_div_rst_map {
|
||||
unsigned int rst_id;
|
||||
unsigned int clk_id;
|
||||
};
|
||||
|
||||
struct ccu_div_data {
|
||||
struct device_node *np;
|
||||
struct regmap *sys_regs;
|
||||
@ -118,11 +118,8 @@ struct ccu_div_data {
|
||||
const struct ccu_div_info *divs_info;
|
||||
struct ccu_div **divs;
|
||||
|
||||
unsigned int rst_num;
|
||||
const struct ccu_div_rst_map *rst_map;
|
||||
struct reset_controller_dev rcdev;
|
||||
struct ccu_rst *rsts;
|
||||
};
|
||||
#define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
|
||||
|
||||
/*
|
||||
* AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
|
||||
@ -169,33 +166,22 @@ static const struct ccu_div_info axi_info[] = {
|
||||
CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
|
||||
};
|
||||
|
||||
static const struct ccu_div_rst_map axi_rst_map[] = {
|
||||
CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
|
||||
};
|
||||
|
||||
/*
|
||||
* APB-bus clock is marked as critical since it's a main communication bus
|
||||
* for the SoC devices registers IO-operations.
|
||||
*/
|
||||
static const struct ccu_div_info sys_info[] = {
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_SATA_CLK, "sys_sata_clk",
|
||||
"sata_clk", CCU_SYS_SATA_REF_BASE, 4,
|
||||
CLK_SET_RATE_GATE,
|
||||
CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
|
||||
CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_BUF_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
|
||||
"sys_sata_clk", CCU_SYS_SATA_REF_BASE,
|
||||
CLK_SET_RATE_PARENT),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
|
||||
"pcie_clk", CCU_SYS_APB_BASE, 5,
|
||||
CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
|
||||
CLK_IS_CRITICAL, CCU_DIV_BASIC | CCU_DIV_RESET_DOMAIN),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
|
||||
"eth_clk", CCU_SYS_GMAC0_BASE, 5),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
|
||||
@ -204,10 +190,12 @@ static const struct ccu_div_info sys_info[] = {
|
||||
"eth_clk", CCU_SYS_GMAC1_BASE, 5),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
|
||||
"eth_clk", 10),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
|
||||
"eth_clk", CCU_SYS_XGMAC_BASE, 8),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_CLK, "sys_xgmac_clk",
|
||||
"eth_clk", CCU_SYS_XGMAC_BASE, 1),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
|
||||
"sys_xgmac_clk", 8),
|
||||
CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
|
||||
"eth_clk", 10),
|
||||
"sys_xgmac_clk", 8),
|
||||
CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
|
||||
"eth_clk", CCU_SYS_USB_BASE, 10),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
|
||||
@ -227,74 +215,58 @@ static const struct ccu_div_info sys_info[] = {
|
||||
"ref_clk", 25),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
|
||||
"ref_clk", CCU_SYS_TIMER0_BASE, 17,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CLK_SET_RATE_GATE, CCU_DIV_BASIC),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
|
||||
"ref_clk", CCU_SYS_TIMER1_BASE, 17,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CLK_SET_RATE_GATE, CCU_DIV_BASIC),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
|
||||
"ref_clk", CCU_SYS_TIMER2_BASE, 17,
|
||||
CLK_SET_RATE_GATE, 0),
|
||||
CLK_SET_RATE_GATE, CCU_DIV_BASIC),
|
||||
CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
|
||||
"eth_clk", CCU_SYS_WDT_BASE, 17,
|
||||
CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
|
||||
};
|
||||
|
||||
static const struct ccu_div_rst_map sys_rst_map[] = {
|
||||
CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
|
||||
CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
|
||||
};
|
||||
static struct ccu_div_data *axi_data;
|
||||
static struct ccu_div_data *sys_data;
|
||||
|
||||
static void ccu_div_set_data(struct ccu_div_data *data)
|
||||
{
|
||||
struct device_node *np = data->np;
|
||||
|
||||
if (of_device_is_compatible(np, "baikal,bt1-ccu-axi"))
|
||||
axi_data = data;
|
||||
else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys"))
|
||||
sys_data = data;
|
||||
else
|
||||
pr_err("Invalid DT node '%s' specified\n", of_node_full_name(np));
|
||||
}
|
||||
|
||||
static struct ccu_div_data *ccu_div_get_data(struct device_node *np)
|
||||
{
|
||||
if (of_device_is_compatible(np, "baikal,bt1-ccu-axi"))
|
||||
return axi_data;
|
||||
else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys"))
|
||||
return sys_data;
|
||||
|
||||
pr_err("Invalid DT node '%s' specified\n", of_node_full_name(np));
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
|
||||
unsigned int clk_id)
|
||||
{
|
||||
struct ccu_div *div;
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < data->divs_num; ++idx) {
|
||||
div = data->divs[idx];
|
||||
if (div && div->id == clk_id)
|
||||
return div;
|
||||
if (data->divs_info[idx].id == clk_id)
|
||||
return data->divs[idx];
|
||||
}
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static int ccu_div_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long rst_id)
|
||||
{
|
||||
struct ccu_div_data *data = to_ccu_div_data(rcdev);
|
||||
const struct ccu_div_rst_map *map;
|
||||
struct ccu_div *div;
|
||||
int idx, ret;
|
||||
|
||||
for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
|
||||
if (map->rst_id == rst_id)
|
||||
break;
|
||||
}
|
||||
if (idx == data->rst_num) {
|
||||
pr_err("Invalid reset ID %lu specified\n", rst_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
div = ccu_div_find_desc(data, map->clk_id);
|
||||
if (IS_ERR(div)) {
|
||||
pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
|
||||
return PTR_ERR(div);
|
||||
}
|
||||
|
||||
ret = ccu_div_reset_domain(div);
|
||||
if (ret) {
|
||||
pr_err("Reset isn't supported by divider %s\n",
|
||||
clk_hw_get_name(ccu_div_get_clk_hw(div)));
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct reset_control_ops ccu_div_rst_ops = {
|
||||
.reset = ccu_div_reset,
|
||||
};
|
||||
|
||||
static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
|
||||
{
|
||||
struct ccu_div_data *data;
|
||||
@ -308,13 +280,9 @@ static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
|
||||
if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
|
||||
data->divs_num = ARRAY_SIZE(axi_info);
|
||||
data->divs_info = axi_info;
|
||||
data->rst_num = ARRAY_SIZE(axi_rst_map);
|
||||
data->rst_map = axi_rst_map;
|
||||
} else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
|
||||
data->divs_num = ARRAY_SIZE(sys_info);
|
||||
data->divs_info = sys_info;
|
||||
data->rst_num = ARRAY_SIZE(sys_rst_map);
|
||||
data->rst_map = sys_rst_map;
|
||||
} else {
|
||||
pr_err("Incompatible DT node '%s' specified\n",
|
||||
of_node_full_name(np));
|
||||
@ -365,14 +333,16 @@ static struct clk_hw *ccu_div_of_clk_hw_get(struct of_phandle_args *clkspec,
|
||||
clk_id = clkspec->args[0];
|
||||
div = ccu_div_find_desc(data, clk_id);
|
||||
if (IS_ERR(div)) {
|
||||
if (div != ERR_PTR(-EPROBE_DEFER))
|
||||
pr_info("Invalid clock ID %d specified\n", clk_id);
|
||||
|
||||
return ERR_CAST(div);
|
||||
}
|
||||
|
||||
return ccu_div_get_clk_hw(div);
|
||||
}
|
||||
|
||||
static int ccu_div_clk_register(struct ccu_div_data *data)
|
||||
static int ccu_div_clk_register(struct ccu_div_data *data, bool defer)
|
||||
{
|
||||
int idx, ret;
|
||||
|
||||
@ -380,6 +350,13 @@ static int ccu_div_clk_register(struct ccu_div_data *data)
|
||||
const struct ccu_div_info *info = &data->divs_info[idx];
|
||||
struct ccu_div_init_data init = {0};
|
||||
|
||||
if (!!(info->features & CCU_DIV_BASIC) ^ defer) {
|
||||
if (!data->divs[idx])
|
||||
data->divs[idx] = ERR_PTR(-EPROBE_DEFER);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
init.id = info->id;
|
||||
init.name = info->name;
|
||||
init.parent_name = info->parent_name;
|
||||
@ -396,6 +373,9 @@ static int ccu_div_clk_register(struct ccu_div_data *data)
|
||||
init.base = info->base;
|
||||
init.sys_regs = data->sys_regs;
|
||||
init.divider = info->divider;
|
||||
} else if (init.type == CCU_DIV_BUF) {
|
||||
init.base = info->base;
|
||||
init.sys_regs = data->sys_regs;
|
||||
} else {
|
||||
init.divider = info->divider;
|
||||
}
|
||||
@ -409,49 +389,104 @@ static int ccu_div_clk_register(struct ccu_div_data *data)
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_hw_unregister:
|
||||
for (--idx; idx >= 0; --idx) {
|
||||
if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
|
||||
continue;
|
||||
|
||||
ccu_div_hw_unregister(data->divs[idx]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ccu_div_clk_unregister(struct ccu_div_data *data, bool defer)
|
||||
{
|
||||
int idx;
|
||||
|
||||
/* Uninstall only the clocks registered on the specfied stage */
|
||||
for (idx = 0; idx < data->divs_num; ++idx) {
|
||||
if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
|
||||
continue;
|
||||
|
||||
ccu_div_hw_unregister(data->divs[idx]);
|
||||
}
|
||||
}
|
||||
|
||||
static int ccu_div_of_register(struct ccu_div_data *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register dividers '%s' clock provider\n",
|
||||
of_node_full_name(data->np));
|
||||
goto err_hw_unregister;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_hw_unregister:
|
||||
for (--idx; idx >= 0; --idx)
|
||||
ccu_div_hw_unregister(data->divs[idx]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ccu_div_clk_unregister(struct ccu_div_data *data)
|
||||
{
|
||||
int idx;
|
||||
|
||||
of_clk_del_provider(data->np);
|
||||
|
||||
for (idx = 0; idx < data->divs_num; ++idx)
|
||||
ccu_div_hw_unregister(data->divs[idx]);
|
||||
}
|
||||
|
||||
static int ccu_div_rst_register(struct ccu_div_data *data)
|
||||
{
|
||||
int ret;
|
||||
struct ccu_rst_init_data init = {0};
|
||||
|
||||
data->rcdev.ops = &ccu_div_rst_ops;
|
||||
data->rcdev.of_node = data->np;
|
||||
data->rcdev.nr_resets = data->rst_num;
|
||||
init.sys_regs = data->sys_regs;
|
||||
init.np = data->np;
|
||||
|
||||
ret = reset_controller_register(&data->rcdev);
|
||||
if (ret)
|
||||
data->rsts = ccu_rst_hw_register(&init);
|
||||
if (IS_ERR(data->rsts)) {
|
||||
pr_err("Couldn't register divider '%s' reset controller\n",
|
||||
of_node_full_name(data->np));
|
||||
return PTR_ERR(data->rsts);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ccu_div_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ccu_div_data *data;
|
||||
int ret;
|
||||
|
||||
data = ccu_div_get_data(dev_of_node(&pdev->dev));
|
||||
if (!data)
|
||||
return -EINVAL;
|
||||
|
||||
ret = ccu_div_clk_register(data, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = ccu_div_rst_register(data);
|
||||
if (ret)
|
||||
goto err_clk_unregister;
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_unregister:
|
||||
ccu_div_clk_unregister(data, false);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ccu_div_init(struct device_node *np)
|
||||
static const struct of_device_id ccu_div_of_match[] = {
|
||||
{ .compatible = "baikal,bt1-ccu-axi" },
|
||||
{ .compatible = "baikal,bt1-ccu-sys" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver ccu_div_driver = {
|
||||
.probe = ccu_div_probe,
|
||||
.driver = {
|
||||
.name = "clk-ccu-div",
|
||||
.of_match_table = ccu_div_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(ccu_div_driver);
|
||||
|
||||
static __init void ccu_div_init(struct device_node *np)
|
||||
{
|
||||
struct ccu_div_data *data;
|
||||
int ret;
|
||||
@ -464,22 +499,23 @@ static void ccu_div_init(struct device_node *np)
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
ret = ccu_div_clk_register(data);
|
||||
ret = ccu_div_clk_register(data, true);
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
ret = ccu_div_rst_register(data);
|
||||
ret = ccu_div_of_register(data);
|
||||
if (ret)
|
||||
goto err_clk_unregister;
|
||||
|
||||
ccu_div_set_data(data);
|
||||
|
||||
return;
|
||||
|
||||
err_clk_unregister:
|
||||
ccu_div_clk_unregister(data);
|
||||
ccu_div_clk_unregister(data, true);
|
||||
|
||||
err_free_data:
|
||||
ccu_div_free_data(data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
|
||||
CLK_OF_DECLARE(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);
|
||||
CLK_OF_DECLARE_DRIVER(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
|
||||
CLK_OF_DECLARE_DRIVER(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clk-provider.h>
|
||||
@ -31,13 +32,14 @@
|
||||
#define CCU_PCIE_PLL_BASE 0x018
|
||||
#define CCU_ETH_PLL_BASE 0x020
|
||||
|
||||
#define CCU_PLL_INFO(_id, _name, _pname, _base, _flags) \
|
||||
#define CCU_PLL_INFO(_id, _name, _pname, _base, _flags, _features) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.base = _base, \
|
||||
.flags = _flags \
|
||||
.flags = _flags, \
|
||||
.features = _features, \
|
||||
}
|
||||
|
||||
#define CCU_PLL_NUM ARRAY_SIZE(pll_info)
|
||||
@ -48,6 +50,7 @@ struct ccu_pll_info {
|
||||
const char *parent_name;
|
||||
unsigned int base;
|
||||
unsigned long flags;
|
||||
unsigned long features;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -61,15 +64,15 @@ struct ccu_pll_info {
|
||||
*/
|
||||
static const struct ccu_pll_info pll_info[] = {
|
||||
CCU_PLL_INFO(CCU_CPU_PLL, "cpu_pll", "ref_clk", CCU_CPU_PLL_BASE,
|
||||
CLK_IS_CRITICAL),
|
||||
CLK_IS_CRITICAL, CCU_PLL_BASIC),
|
||||
CCU_PLL_INFO(CCU_SATA_PLL, "sata_pll", "ref_clk", CCU_SATA_PLL_BASE,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
|
||||
CCU_PLL_INFO(CCU_DDR_PLL, "ddr_pll", "ref_clk", CCU_DDR_PLL_BASE,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0),
|
||||
CCU_PLL_INFO(CCU_PCIE_PLL, "pcie_pll", "ref_clk", CCU_PCIE_PLL_BASE,
|
||||
CLK_IS_CRITICAL),
|
||||
CLK_IS_CRITICAL, CCU_PLL_BASIC),
|
||||
CCU_PLL_INFO(CCU_ETH_PLL, "eth_pll", "ref_clk", CCU_ETH_PLL_BASE,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE)
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0)
|
||||
};
|
||||
|
||||
struct ccu_pll_data {
|
||||
@ -78,16 +81,16 @@ struct ccu_pll_data {
|
||||
struct ccu_pll *plls[CCU_PLL_NUM];
|
||||
};
|
||||
|
||||
static struct ccu_pll_data *pll_data;
|
||||
|
||||
static struct ccu_pll *ccu_pll_find_desc(struct ccu_pll_data *data,
|
||||
unsigned int clk_id)
|
||||
{
|
||||
struct ccu_pll *pll;
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
|
||||
pll = data->plls[idx];
|
||||
if (pll && pll->id == clk_id)
|
||||
return pll;
|
||||
if (pll_info[idx].id == clk_id)
|
||||
return data->plls[idx];
|
||||
}
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
@ -133,14 +136,16 @@ static struct clk_hw *ccu_pll_of_clk_hw_get(struct of_phandle_args *clkspec,
|
||||
clk_id = clkspec->args[0];
|
||||
pll = ccu_pll_find_desc(data, clk_id);
|
||||
if (IS_ERR(pll)) {
|
||||
if (pll != ERR_PTR(-EPROBE_DEFER))
|
||||
pr_info("Invalid PLL clock ID %d specified\n", clk_id);
|
||||
|
||||
return ERR_CAST(pll);
|
||||
}
|
||||
|
||||
return ccu_pll_get_clk_hw(pll);
|
||||
}
|
||||
|
||||
static int ccu_pll_clk_register(struct ccu_pll_data *data)
|
||||
static int ccu_pll_clk_register(struct ccu_pll_data *data, bool defer)
|
||||
{
|
||||
int idx, ret;
|
||||
|
||||
@ -148,6 +153,14 @@ static int ccu_pll_clk_register(struct ccu_pll_data *data)
|
||||
const struct ccu_pll_info *info = &pll_info[idx];
|
||||
struct ccu_pll_init_data init = {0};
|
||||
|
||||
/* Defer non-basic PLLs allocation for the probe stage */
|
||||
if (!!(info->features & CCU_PLL_BASIC) ^ defer) {
|
||||
if (!data->plls[idx])
|
||||
data->plls[idx] = ERR_PTR(-EPROBE_DEFER);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
init.id = info->id;
|
||||
init.name = info->name;
|
||||
init.parent_name = info->parent_name;
|
||||
@ -155,6 +168,7 @@ static int ccu_pll_clk_register(struct ccu_pll_data *data)
|
||||
init.sys_regs = data->sys_regs;
|
||||
init.np = data->np;
|
||||
init.flags = info->flags;
|
||||
init.features = info->features;
|
||||
|
||||
data->plls[idx] = ccu_pll_hw_register(&init);
|
||||
if (IS_ERR(data->plls[idx])) {
|
||||
@ -165,22 +179,70 @@ static int ccu_pll_clk_register(struct ccu_pll_data *data)
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_hw_unregister:
|
||||
for (--idx; idx >= 0; --idx) {
|
||||
if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)
|
||||
continue;
|
||||
|
||||
ccu_pll_hw_unregister(data->plls[idx]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ccu_pll_clk_unregister(struct ccu_pll_data *data, bool defer)
|
||||
{
|
||||
int idx;
|
||||
|
||||
/* Uninstall only the clocks registered on the specfied stage */
|
||||
for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
|
||||
if (!!(pll_info[idx].features & CCU_PLL_BASIC) ^ defer)
|
||||
continue;
|
||||
|
||||
ccu_pll_hw_unregister(data->plls[idx]);
|
||||
}
|
||||
}
|
||||
|
||||
static int ccu_pll_of_register(struct ccu_pll_data *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = of_clk_add_hw_provider(data->np, ccu_pll_of_clk_hw_get, data);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register PLL provider of '%s'\n",
|
||||
of_node_full_name(data->np));
|
||||
goto err_hw_unregister;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_hw_unregister:
|
||||
for (--idx; idx >= 0; --idx)
|
||||
ccu_pll_hw_unregister(data->plls[idx]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ccu_pll_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ccu_pll_data *data = pll_data;
|
||||
|
||||
if (!data)
|
||||
return -EINVAL;
|
||||
|
||||
return ccu_pll_clk_register(data, false);
|
||||
}
|
||||
|
||||
static const struct of_device_id ccu_pll_of_match[] = {
|
||||
{ .compatible = "baikal,bt1-ccu-pll" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver ccu_pll_driver = {
|
||||
.probe = ccu_pll_probe,
|
||||
.driver = {
|
||||
.name = "clk-ccu-pll",
|
||||
.of_match_table = ccu_pll_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(ccu_pll_driver);
|
||||
|
||||
static __init void ccu_pll_init(struct device_node *np)
|
||||
{
|
||||
struct ccu_pll_data *data;
|
||||
@ -194,13 +256,22 @@ static __init void ccu_pll_init(struct device_node *np)
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
ret = ccu_pll_clk_register(data);
|
||||
ret = ccu_pll_clk_register(data, true);
|
||||
if (ret)
|
||||
goto err_free_data;
|
||||
|
||||
ret = ccu_pll_of_register(data);
|
||||
if (ret)
|
||||
goto err_clk_unregister;
|
||||
|
||||
pll_data = data;
|
||||
|
||||
return;
|
||||
|
||||
err_clk_unregister:
|
||||
ccu_pll_clk_unregister(data, true);
|
||||
|
||||
err_free_data:
|
||||
ccu_pll_free_data(data);
|
||||
}
|
||||
CLK_OF_DECLARE(ccu_pll, "baikal,bt1-ccu-pll", ccu_pll_init);
|
||||
CLK_OF_DECLARE_DRIVER(ccu_pll, "baikal,bt1-ccu-pll", ccu_pll_init);
|
||||
|
||||
@ -30,6 +30,7 @@
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/math.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -502,6 +503,8 @@ struct bcm2835_clock_data {
|
||||
bool low_jitter;
|
||||
|
||||
u32 tcnt_mux;
|
||||
|
||||
bool round_up;
|
||||
};
|
||||
|
||||
struct bcm2835_gate_data {
|
||||
@ -966,7 +969,7 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
|
||||
return div;
|
||||
}
|
||||
|
||||
static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
|
||||
static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
|
||||
unsigned long parent_rate,
|
||||
u32 div)
|
||||
{
|
||||
@ -993,12 +996,34 @@ static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
|
||||
return temp;
|
||||
}
|
||||
|
||||
static unsigned long bcm2835_round_rate(unsigned long rate)
|
||||
{
|
||||
unsigned long scaler;
|
||||
unsigned long limit;
|
||||
|
||||
limit = rate / 100000;
|
||||
|
||||
scaler = 1;
|
||||
while (scaler < limit)
|
||||
scaler *= 10;
|
||||
|
||||
/*
|
||||
* If increasing a clock by less than 0.1% changes it
|
||||
* from ..999.. to ..000.., round up.
|
||||
*/
|
||||
if ((rate + scaler - 1) / scaler % 1000 == 0)
|
||||
rate = roundup(rate, scaler);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
|
||||
struct bcm2835_cprman *cprman = clock->cprman;
|
||||
const struct bcm2835_clock_data *data = clock->data;
|
||||
unsigned long rate;
|
||||
u32 div;
|
||||
|
||||
if (data->int_bits == 0 && data->frac_bits == 0)
|
||||
@ -1006,7 +1031,12 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
|
||||
|
||||
div = cprman_read(cprman, data->div_reg);
|
||||
|
||||
return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
|
||||
rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
|
||||
|
||||
if (data->round_up)
|
||||
rate = bcm2835_round_rate(rate);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
|
||||
@ -1784,7 +1814,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
|
||||
.load_mask = CM_PLLC_LOADPER,
|
||||
.hold_mask = CM_PLLC_HOLDPER,
|
||||
.fixed_divider = 1,
|
||||
.flags = CLK_SET_RATE_PARENT),
|
||||
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
|
||||
/*
|
||||
* PLLD is the display PLL, used to drive DSI display panels.
|
||||
@ -2143,7 +2173,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
|
||||
.div_reg = CM_UARTDIV,
|
||||
.int_bits = 10,
|
||||
.frac_bits = 12,
|
||||
.tcnt_mux = 28),
|
||||
.tcnt_mux = 28,
|
||||
.round_up = true),
|
||||
|
||||
/* TV encoder clock. Only operating frequency is 108Mhz. */
|
||||
[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
|
||||
|
||||
@ -33,6 +33,7 @@ enum rpi_firmware_clk_id {
|
||||
RPI_FIRMWARE_EMMC2_CLK_ID,
|
||||
RPI_FIRMWARE_M2MC_CLK_ID,
|
||||
RPI_FIRMWARE_PIXEL_BVB_CLK_ID,
|
||||
RPI_FIRMWARE_VEC_CLK_ID,
|
||||
RPI_FIRMWARE_NUM_CLK_ID,
|
||||
};
|
||||
|
||||
@ -51,6 +52,7 @@ static char *rpi_firmware_clk_names[] = {
|
||||
[RPI_FIRMWARE_EMMC2_CLK_ID] = "emmc2",
|
||||
[RPI_FIRMWARE_M2MC_CLK_ID] = "m2mc",
|
||||
[RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = "pixel-bvb",
|
||||
[RPI_FIRMWARE_VEC_CLK_ID] = "vec",
|
||||
};
|
||||
|
||||
#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
|
||||
@ -129,9 +131,18 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
|
||||
[RPI_FIRMWARE_V3D_CLK_ID] = {
|
||||
.export = true,
|
||||
},
|
||||
[RPI_FIRMWARE_PIXEL_CLK_ID] = {
|
||||
.export = true,
|
||||
},
|
||||
[RPI_FIRMWARE_HEVC_CLK_ID] = {
|
||||
.export = true,
|
||||
},
|
||||
[RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = {
|
||||
.export = true,
|
||||
},
|
||||
[RPI_FIRMWARE_VEC_CLK_ID] = {
|
||||
.export = true,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
@ -500,12 +500,15 @@ static void __init berlin2_clock_setup(struct device_node *np)
|
||||
int n, ret;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
if (!clk_data) {
|
||||
of_node_put(parent_np);
|
||||
return;
|
||||
}
|
||||
clk_data->num = MAX_CLKS;
|
||||
hws = clk_data->hws;
|
||||
|
||||
gbase = of_iomap(parent_np, 0);
|
||||
of_node_put(parent_np);
|
||||
if (!gbase)
|
||||
return;
|
||||
|
||||
|
||||
@ -286,19 +286,23 @@ static void __init berlin2q_clock_setup(struct device_node *np)
|
||||
int n, ret;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
if (!clk_data) {
|
||||
of_node_put(parent_np);
|
||||
return;
|
||||
}
|
||||
clk_data->num = MAX_CLKS;
|
||||
hws = clk_data->hws;
|
||||
|
||||
gbase = of_iomap(parent_np, 0);
|
||||
if (!gbase) {
|
||||
of_node_put(parent_np);
|
||||
pr_err("%pOF: Unable to map global base\n", np);
|
||||
return;
|
||||
}
|
||||
|
||||
/* BG2Q CPU PLL is not part of global registers */
|
||||
cpupll_base = of_iomap(parent_np, 1);
|
||||
of_node_put(parent_np);
|
||||
if (!cpupll_base) {
|
||||
pr_err("%pOF: Unable to map cpupll base\n", np);
|
||||
iounmap(gbase);
|
||||
|
||||
@ -80,7 +80,7 @@ struct asm9260_mux_clock {
|
||||
u8 mask;
|
||||
u32 *table;
|
||||
const char *name;
|
||||
const char **parent_names;
|
||||
const struct clk_parent_data *parent_data;
|
||||
u8 num_parents;
|
||||
unsigned long offset;
|
||||
unsigned long flags;
|
||||
@ -232,10 +232,10 @@ static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
|
||||
HW_AHBCLKCTRL1, 16 },
|
||||
};
|
||||
|
||||
static const char __initdata *main_mux_p[] = { NULL, NULL };
|
||||
static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"};
|
||||
static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"};
|
||||
static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"};
|
||||
static struct clk_parent_data __initdata main_mux_p[] = { { .index = 0, }, { .name = "pll" } };
|
||||
static struct clk_parent_data __initdata i2s0_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s0m_div"} };
|
||||
static struct clk_parent_data __initdata i2s1_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s1m_div"} };
|
||||
static struct clk_parent_data __initdata clkout_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "rtc"} };
|
||||
static u32 three_mux_table[] = {0, 1, 3};
|
||||
|
||||
static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
|
||||
@ -255,9 +255,10 @@ static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
|
||||
|
||||
static void __init asm9260_acc_init(struct device_node *np)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct clk_hw *hw, *pll_hw;
|
||||
struct clk_hw **hws;
|
||||
const char *ref_clk, *pll_clk = "pll";
|
||||
const char *pll_clk = "pll";
|
||||
struct clk_parent_data pll_parent_data = { .index = 0 };
|
||||
u32 rate;
|
||||
int n;
|
||||
|
||||
@ -274,21 +275,15 @@ static void __init asm9260_acc_init(struct device_node *np)
|
||||
/* register pll */
|
||||
rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
|
||||
|
||||
/* TODO: Convert to DT parent scheme */
|
||||
ref_clk = of_clk_get_parent_name(np, 0);
|
||||
hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk,
|
||||
ref_clk, NULL, NULL, 0, rate, 0,
|
||||
CLK_FIXED_RATE_PARENT_ACCURACY);
|
||||
|
||||
if (IS_ERR(hw))
|
||||
pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data,
|
||||
0, rate);
|
||||
if (IS_ERR(pll_hw))
|
||||
panic("%pOFn: can't register REFCLK. Check DT!", np);
|
||||
|
||||
for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
|
||||
const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
|
||||
|
||||
mc->parent_names[0] = ref_clk;
|
||||
mc->parent_names[1] = pll_clk;
|
||||
hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,
|
||||
hw = clk_hw_register_mux_table_parent_data(NULL, mc->name, mc->parent_data,
|
||||
mc->num_parents, mc->flags, base + mc->offset,
|
||||
0, mc->mask, 0, mc->table, &asm9260_clk_lock);
|
||||
}
|
||||
|
||||
@ -622,7 +622,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
|
||||
regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
|
||||
|
||||
/* P-Bus (BCLK) clock divider */
|
||||
hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
|
||||
hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0,
|
||||
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
|
||||
ast2600_div_table,
|
||||
&aspeed_g6_clk_lock);
|
||||
|
||||
@ -49,12 +49,24 @@ const struct clk_ops clk_fixed_rate_ops = {
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
|
||||
|
||||
static void devm_clk_hw_register_fixed_rate_release(struct device *dev, void *res)
|
||||
{
|
||||
struct clk_fixed_rate *fix = res;
|
||||
|
||||
/*
|
||||
* We can not use clk_hw_unregister_fixed_rate, since it will kfree()
|
||||
* the hw, resulting in double free. Just unregister the hw and let
|
||||
* devres code kfree() it.
|
||||
*/
|
||||
clk_hw_unregister(&fix->hw);
|
||||
}
|
||||
|
||||
struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
|
||||
struct device_node *np, const char *name,
|
||||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data, unsigned long flags,
|
||||
unsigned long fixed_rate, unsigned long fixed_accuracy,
|
||||
unsigned long clk_fixed_flags)
|
||||
unsigned long clk_fixed_flags, bool devm)
|
||||
{
|
||||
struct clk_fixed_rate *fixed;
|
||||
struct clk_hw *hw;
|
||||
@ -62,6 +74,10 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
|
||||
int ret = -EINVAL;
|
||||
|
||||
/* allocate fixed-rate clock */
|
||||
if (devm)
|
||||
fixed = devres_alloc(devm_clk_hw_register_fixed_rate_release,
|
||||
sizeof(*fixed), GFP_KERNEL);
|
||||
else
|
||||
fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
|
||||
if (!fixed)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
@ -90,9 +106,13 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
|
||||
else
|
||||
ret = of_clk_hw_register(np, hw);
|
||||
if (ret) {
|
||||
if (devm)
|
||||
devres_free(fixed);
|
||||
else
|
||||
kfree(fixed);
|
||||
hw = ERR_PTR(ret);
|
||||
}
|
||||
} else if (devm)
|
||||
devres_add(dev, fixed);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
@ -286,7 +286,7 @@ static struct platform_driver lan966x_clk_driver = {
|
||||
.of_match_table = lan966x_clk_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(lan966x_clk_driver);
|
||||
module_platform_driver(lan966x_clk_driver);
|
||||
|
||||
MODULE_AUTHOR("Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>");
|
||||
MODULE_DESCRIPTION("LAN966X clock driver");
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
#include <linux/mfd/lochnagar1_regs.h>
|
||||
#include <linux/mfd/lochnagar2_regs.h>
|
||||
|
||||
#include <dt-bindings/clk/lochnagar.h>
|
||||
#include <dt-bindings/clock/lochnagar.h>
|
||||
|
||||
#define LOCHNAGAR_NUM_CLOCKS (LOCHNAGAR_SPDIF_CLKOUT + 1)
|
||||
|
||||
|
||||
@ -99,7 +99,7 @@ static void __init nomadik_src_init(void)
|
||||
if (!src_base) {
|
||||
pr_err("%s: must have src parent node with REGS (%pOFn)\n",
|
||||
__func__, np);
|
||||
return;
|
||||
goto out_put;
|
||||
}
|
||||
|
||||
/* Set all timers to use the 2.4 MHz TIMCLK */
|
||||
@ -132,6 +132,9 @@ static void __init nomadik_src_init(void)
|
||||
}
|
||||
writel(val, src_base + SRC_XTALCR);
|
||||
register_reboot_notifier(&nomadik_clk_reboot_notifier);
|
||||
|
||||
out_put:
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -129,20 +129,6 @@ npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
|
||||
#define NPCM7XX_SECCNT (0x68)
|
||||
#define NPCM7XX_CNTR25M (0x6C)
|
||||
|
||||
struct npcm7xx_clk_gate_data {
|
||||
u32 reg;
|
||||
u8 bit_idx;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
/*
|
||||
* If this clock is exported via DT, set onecell_idx to constant
|
||||
* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
|
||||
* this specific clock. Otherwise, set to -1.
|
||||
*/
|
||||
int onecell_idx;
|
||||
};
|
||||
|
||||
struct npcm7xx_clk_mux_data {
|
||||
u8 shift;
|
||||
u8 mask;
|
||||
@ -160,21 +146,6 @@ struct npcm7xx_clk_mux_data {
|
||||
|
||||
};
|
||||
|
||||
struct npcm7xx_clk_div_fixed_data {
|
||||
u8 mult;
|
||||
u8 div;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
u8 clk_divider_flags;
|
||||
/*
|
||||
* If this clock is exported via DT, set onecell_idx to constant
|
||||
* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
|
||||
* this specific clock. Otherwise, set to -1.
|
||||
*/
|
||||
int onecell_idx;
|
||||
};
|
||||
|
||||
|
||||
struct npcm7xx_clk_div_data {
|
||||
u32 reg;
|
||||
u8 shift;
|
||||
|
||||
@ -207,7 +207,7 @@ static const struct of_device_id oxnas_stdclk_dt_ids[] = {
|
||||
|
||||
static int oxnas_stdclk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *np = pdev->dev.of_node, *parent_np;
|
||||
const struct oxnas_stdclk_data *data;
|
||||
struct regmap *regmap;
|
||||
int ret;
|
||||
@ -215,7 +215,9 @@ static int oxnas_stdclk_probe(struct platform_device *pdev)
|
||||
|
||||
data = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
parent_np = of_get_parent(np);
|
||||
regmap = syscon_node_to_regmap(parent_np);
|
||||
of_node_put(parent_np);
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(&pdev->dev, "failed to have parent regmap\n");
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
@ -1063,8 +1063,13 @@ static void __init _clockgen_init(struct device_node *np, bool legacy);
|
||||
*/
|
||||
static void __init legacy_init_clockgen(struct device_node *np)
|
||||
{
|
||||
if (!clockgen.node)
|
||||
_clockgen_init(of_get_parent(np), true);
|
||||
if (!clockgen.node) {
|
||||
struct device_node *parent_np;
|
||||
|
||||
parent_np = of_get_parent(np);
|
||||
_clockgen_init(parent_np, true);
|
||||
of_node_put(parent_np);
|
||||
}
|
||||
}
|
||||
|
||||
/* Legacy node */
|
||||
@ -1159,6 +1164,7 @@ static struct clk * __init create_sysclk(const char *name)
|
||||
sysclk = of_get_child_by_name(clockgen.node, "sysclk");
|
||||
if (sysclk) {
|
||||
clk = sysclk_from_fixed(sysclk, name);
|
||||
of_node_put(sysclk);
|
||||
if (!IS_ERR(clk))
|
||||
return clk;
|
||||
}
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
#include <dt-bindings/clock/versaclock.h>
|
||||
|
||||
/* VersaClock5 registers */
|
||||
#define VC5_OTP_CONTROL 0x00
|
||||
@ -153,6 +153,7 @@ enum vc5_model {
|
||||
IDT_VC5_5P49V5935,
|
||||
IDT_VC6_5P49V6901,
|
||||
IDT_VC6_5P49V6965,
|
||||
IDT_VC6_5P49V6975,
|
||||
};
|
||||
|
||||
/* Structure to describe features of a particular VC5 model */
|
||||
@ -230,8 +231,12 @@ static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
|
||||
container_of(hw, struct vc5_driver_data, clk_mux);
|
||||
const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
|
||||
unsigned int src;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
|
||||
src &= mask;
|
||||
|
||||
if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
|
||||
@ -286,8 +291,12 @@ static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
|
||||
struct vc5_driver_data *vc5 =
|
||||
container_of(hw, struct vc5_driver_data, clk_mul);
|
||||
unsigned int premul;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
|
||||
if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
|
||||
parent_rate *= 2;
|
||||
|
||||
@ -315,11 +324,9 @@ static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
else
|
||||
mask = 0;
|
||||
|
||||
regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
|
||||
return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
|
||||
VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
|
||||
mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops vc5_dbl_ops = {
|
||||
@ -334,14 +341,19 @@ static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
|
||||
struct vc5_driver_data *vc5 =
|
||||
container_of(hw, struct vc5_driver_data, clk_pfd);
|
||||
unsigned int prediv, div;
|
||||
int ret;
|
||||
|
||||
regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
|
||||
ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
/* The bypass_prediv is set, PLL fed from Ref_in directly. */
|
||||
if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
|
||||
return parent_rate;
|
||||
|
||||
regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
|
||||
ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
/* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
|
||||
if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
|
||||
@ -376,15 +388,17 @@ static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
struct vc5_driver_data *vc5 =
|
||||
container_of(hw, struct vc5_driver_data, clk_pfd);
|
||||
unsigned long idiv;
|
||||
int ret;
|
||||
u8 div;
|
||||
|
||||
/* CLKIN within range of PLL input, feed directly to PLL. */
|
||||
if (parent_rate <= 50000000) {
|
||||
regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
|
||||
VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
|
||||
ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
|
||||
VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
|
||||
regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
|
||||
return 0;
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
|
||||
}
|
||||
|
||||
idiv = DIV_ROUND_UP(parent_rate, rate);
|
||||
@ -395,11 +409,12 @@ static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
else
|
||||
div = VC5_REF_DIVIDER_REF_DIV(idiv);
|
||||
|
||||
regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
|
||||
regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
|
||||
VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
|
||||
ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
|
||||
VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
|
||||
}
|
||||
|
||||
static const struct clk_ops vc5_pfd_ops = {
|
||||
@ -551,9 +566,12 @@ static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
hwdata->div_int >> 4, hwdata->div_int << 4,
|
||||
0
|
||||
};
|
||||
int ret;
|
||||
|
||||
regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
|
||||
ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
|
||||
data, 14);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Toggle magic bit in undocumented register for unknown reason.
|
||||
@ -561,12 +579,13 @@ static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
* datasheet somewhat implies this is needed, but the register
|
||||
* and the bit is not documented.
|
||||
*/
|
||||
regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
|
||||
VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
|
||||
regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
|
||||
VC5_GLOBAL_REGISTER_GLOBAL_RESET,
|
||||
ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
|
||||
VC5_GLOBAL_REGISTER_GLOBAL_RESET);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
|
||||
VC5_GLOBAL_REGISTER_GLOBAL_RESET);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops vc5_fod_ops = {
|
||||
@ -594,9 +613,8 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
|
||||
* registers.
|
||||
*/
|
||||
if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
|
||||
ret = regmap_update_bits(vc5->regmap,
|
||||
ret = regmap_set_bits(vc5->regmap,
|
||||
VC5_RESERVED_X0(hwdata->num),
|
||||
VC5_RESERVED_X0_BYPASS_SYNC,
|
||||
VC5_RESERVED_X0_BYPASS_SYNC);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -606,7 +624,10 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
|
||||
* If the input mux is disabled, enable it first and
|
||||
* select source from matching FOD.
|
||||
*/
|
||||
regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
|
||||
ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if ((src & mask) == 0) {
|
||||
src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
|
||||
ret = regmap_update_bits(vc5->regmap,
|
||||
@ -617,18 +638,22 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
|
||||
}
|
||||
|
||||
/* Enable the clock buffer */
|
||||
regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
|
||||
VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
|
||||
ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
|
||||
VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (hwdata->clk_output_cfg0_mask) {
|
||||
dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
|
||||
hwdata->num, hwdata->clk_output_cfg0_mask,
|
||||
hwdata->clk_output_cfg0);
|
||||
|
||||
regmap_update_bits(vc5->regmap,
|
||||
ret = regmap_update_bits(vc5->regmap,
|
||||
VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
|
||||
hwdata->clk_output_cfg0_mask,
|
||||
hwdata->clk_output_cfg0);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -640,8 +665,8 @@ static void vc5_clk_out_unprepare(struct clk_hw *hw)
|
||||
struct vc5_driver_data *vc5 = hwdata->vc5;
|
||||
|
||||
/* Disable the clock buffer */
|
||||
regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
|
||||
VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
|
||||
regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
|
||||
VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
|
||||
}
|
||||
|
||||
static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
|
||||
@ -656,8 +681,12 @@ static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
|
||||
const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
|
||||
VC5_OUT_DIV_CONTROL_SEL_EXT;
|
||||
unsigned int src;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
|
||||
src &= mask;
|
||||
|
||||
if (src == 0) /* Input mux set to DISABLED */
|
||||
@ -725,6 +754,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
|
||||
case IDT_VC5_5P49V5935:
|
||||
case IDT_VC6_5P49V6901:
|
||||
case IDT_VC6_5P49V6965:
|
||||
case IDT_VC6_5P49V6975:
|
||||
default:
|
||||
return n;
|
||||
}
|
||||
@ -819,8 +849,11 @@ static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data
|
||||
{
|
||||
u32 value;
|
||||
int mapped_value;
|
||||
int ret;
|
||||
|
||||
if (of_property_read_u32(node, "idt,xtal-load-femtofarads", &value))
|
||||
return 0;
|
||||
|
||||
if (!of_property_read_u32(node, "idt,xtal-load-femtofarads", &value)) {
|
||||
mapped_value = vc5_map_cap_value(value);
|
||||
if (mapped_value < 0)
|
||||
return mapped_value;
|
||||
@ -830,11 +863,13 @@ static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data
|
||||
* VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so
|
||||
* shift the value 2 places.
|
||||
*/
|
||||
regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03, mapped_value << 2);
|
||||
regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03, mapped_value << 2);
|
||||
}
|
||||
ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03,
|
||||
mapped_value << 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03,
|
||||
mapped_value << 2);
|
||||
}
|
||||
|
||||
static int vc5_update_slew(struct device_node *np_output,
|
||||
@ -956,7 +991,10 @@ static int vc5_probe(struct i2c_client *client)
|
||||
"could not read idt,output-enable-active\n");
|
||||
}
|
||||
|
||||
regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask, src_val);
|
||||
ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask,
|
||||
src_val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Register clock input mux */
|
||||
memset(&init, 0, sizeof(init));
|
||||
@ -1202,7 +1240,7 @@ static const struct vc5_chip_info idt_5p49v6901_info = {
|
||||
.model = IDT_VC6_5P49V6901,
|
||||
.clk_fod_cnt = 4,
|
||||
.clk_out_cnt = 5,
|
||||
.flags = VC5_HAS_PFD_FREQ_DBL,
|
||||
.flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
|
||||
};
|
||||
|
||||
static const struct vc5_chip_info idt_5p49v6965_info = {
|
||||
@ -1212,6 +1250,13 @@ static const struct vc5_chip_info idt_5p49v6965_info = {
|
||||
.flags = VC5_HAS_BYPASS_SYNC_BIT,
|
||||
};
|
||||
|
||||
static const struct vc5_chip_info idt_5p49v6975_info = {
|
||||
.model = IDT_VC6_5P49V6975,
|
||||
.clk_fod_cnt = 4,
|
||||
.clk_out_cnt = 5,
|
||||
.flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL,
|
||||
};
|
||||
|
||||
static const struct i2c_device_id vc5_id[] = {
|
||||
{ "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
|
||||
{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
|
||||
@ -1219,6 +1264,7 @@ static const struct i2c_device_id vc5_id[] = {
|
||||
{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
|
||||
{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
|
||||
{ "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
|
||||
{ "5p49v6975", .driver_data = IDT_VC6_5P49V6975 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, vc5_id);
|
||||
@ -1230,6 +1276,7 @@ static const struct of_device_id clk_vc5_of_match[] = {
|
||||
{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
|
||||
{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
|
||||
{ .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
|
||||
{ .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
|
||||
|
||||
1309
drivers/clk/clk-versaclock7.c
Normal file
1309
drivers/clk/clk-versaclock7.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -522,10 +522,10 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
|
||||
pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
|
||||
data & pclk->param.reg_clk_mask ? "enabled" :
|
||||
"disabled");
|
||||
} else {
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (!pclk->param.csr_reg)
|
||||
return 1;
|
||||
return data & pclk->param.reg_clk_mask ? 1 : 0;
|
||||
}
|
||||
|
||||
|
||||
@ -2188,7 +2188,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
|
||||
{
|
||||
struct clk_core *top, *fail_clk;
|
||||
unsigned long rate;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
if (!core)
|
||||
return 0;
|
||||
@ -3461,7 +3461,7 @@ static void clk_core_reparent_orphans_nolock(void)
|
||||
|
||||
/*
|
||||
* We need to use __clk_set_parent_before() and _after() to
|
||||
* to properly migrate any prepare/enable count of the orphan
|
||||
* properly migrate any prepare/enable count of the orphan
|
||||
* clock. This is important for CLK_IS_CRITICAL clocks, which
|
||||
* are enabled during init but might not have a parent yet.
|
||||
*/
|
||||
@ -3671,7 +3671,6 @@ static int __clk_core_init(struct clk_core *core)
|
||||
|
||||
clk_core_reparent_orphans_nolock();
|
||||
|
||||
|
||||
kref_init(&core->ref);
|
||||
out:
|
||||
clk_pm_runtime_put(core);
|
||||
@ -4750,32 +4749,6 @@ void of_clk_del_provider(struct device_node *np)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_clk_del_provider);
|
||||
|
||||
static int devm_clk_provider_match(struct device *dev, void *res, void *data)
|
||||
{
|
||||
struct device_node **np = res;
|
||||
|
||||
if (WARN_ON(!np || !*np))
|
||||
return 0;
|
||||
|
||||
return *np == data;
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_of_clk_del_provider() - Remove clock provider registered using devm
|
||||
* @dev: Device to whose lifetime the clock provider was bound
|
||||
*/
|
||||
void devm_of_clk_del_provider(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct device_node *np = get_clk_provider_node(dev);
|
||||
|
||||
ret = devres_release(dev, devm_of_clk_release_provider,
|
||||
devm_clk_provider_match, np);
|
||||
|
||||
WARN_ON(ret);
|
||||
}
|
||||
EXPORT_SYMBOL(devm_of_clk_del_provider);
|
||||
|
||||
/**
|
||||
* of_parse_clkspec() - Parse a DT clock specifier for a given device node
|
||||
* @np: device node to parse clock specifier from
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user