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drm/amdgpu: Only retrieve GPU address of GART table after pinning it

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Doing it earlier hits a WARN_ON_ONCE in amdgpu_bo_gpu_offset.

Fixes: "drm/amdgpu: remove gart.table_addr"

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer 2018-08-28 11:26:17 +02:00 committed by Alex Deucher
parent 7ef0b43545
commit bdb1922abd
3 changed files with 12 additions and 3 deletions
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5
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
View File

@ -494,7 +494,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
{
uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
uint64_t table_addr;
int r, i;
u32 field;
@ -505,6 +505,9 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
r = amdgpu_gart_table_vram_pin(adev);
if (r)
return r;
table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
/* Setup TLB control */
WREG32(mmMC_VM_MX_L1_TLB_CNTL,
(0xA << 7) |

5
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
View File

@ -602,7 +602,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
*/
static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
{
uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
uint64_t table_addr;
int r, i;
u32 tmp, field;
@ -613,6 +613,9 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
r = amdgpu_gart_table_vram_pin(adev);
if (r)
return r;
table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
/* Setup TLB control */
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

5
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
View File

@ -807,7 +807,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
*/
static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
{
uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
uint64_t table_addr;
int r, i;
u32 tmp, field;
@ -818,6 +818,9 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
r = amdgpu_gart_table_vram_pin(adev);
if (r)
return r;
table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
/* Setup TLB control */
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);