[media] s5h1432: fix codingstyle issues
Run Lindent and fix a few spacing issues. This patch makes no functional change to the driver. Signed-off-by: Devin Heitmueller <dheitmueller@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Devin Heitmueller
Mauro Carvalho Chehab
parent
9dfde5578d
commit
bda7f4ee67
@ -53,14 +53,13 @@ static int debug;
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printk(arg); \
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} while (0)
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static int s5h1432_writereg(struct s5h1432_state *state,
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u8 addr, u8 reg, u8 data)
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u8 addr, u8 reg, u8 data)
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{
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int ret;
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u8 buf[] = { reg, data };
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struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 2 };
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struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 };
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ret = i2c_transfer(state->i2c, &msg, 1);
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@ -78,14 +77,15 @@ static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{ .addr = addr, .flags = 0, .buf = b0, .len = 1 },
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{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
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{.addr = addr, .flags = 0, .buf = b0, .len = 1},
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{.addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1}
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};
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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printk(KERN_ERR "%s: readreg error (ret == %i)\n",
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__func__, ret);
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__func__, ret);
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return b1[0];
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}
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@ -94,15 +94,14 @@ static int s5h1432_sleep(struct dvb_frontend *fe)
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return 0;
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}
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static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
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static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe,
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u32 bandwidth)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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u8 reg = 0;
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/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2*/
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/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */
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reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
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reg &= ~(0x0C);
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switch (bandwidth) {
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@ -116,141 +115,129 @@ static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
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reg |= 0x00;
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break;
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default:
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return 0;
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return 0;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
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return 1;
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return 1;
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}
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static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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switch (ifFreqHz) {
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case TAIWAN_HI_IF_FREQ_44_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x15);
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break;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x15);
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break;
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case EUROPE_HI_IF_FREQ_36_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x40);
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break;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0x40);
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break;
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case IF_FREQ_6_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xe0);
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break;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xe0);
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break;
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case IF_FREQ_3point3_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
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break;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
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break;
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case IF_FREQ_3point5_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xED);
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break;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x55);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xED);
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break;
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case IF_FREQ_4_MHZ:
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{
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEA);
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break;
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}
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0xAA);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEA);
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break;
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default:
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{
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u32 value = 0;
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value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
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(u32) 32768) / (48 * 1000));
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printk(KERN_INFO "Default IFFreq %d :reg value = 0x%x \n",
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ifFreqHz, value);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 ,
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(u8) value & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 ,
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(u8)(value>>8) & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 ,
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(u8)(value>>16) & 0xFF);
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break;
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}
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u32 value = 0;
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value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
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(u32) 32768) / (48 * 1000));
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printk(KERN_INFO
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"Default IFFreq %d :reg value = 0x%x \n",
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ifFreqHz, value);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4,
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(u8) value & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5,
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(u8) (value >> 8) & 0xFF);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7,
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(u8) (value >> 16) & 0xFF);
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break;
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}
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}
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return 1;
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return 1;
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}
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/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
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static int s5h1432_set_frontend(struct dvb_frontend *fe,
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struct dvb_frontend_parameters *p)
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struct dvb_frontend_parameters *p)
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{
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u32 dvb_bandwidth = 8;
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struct s5h1432_state *state = fe->demodulator_priv;
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if (p->frequency == state->current_frequency) {
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/*current_frequency = p->frequency;*/
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/*state->current_frequency = p->frequency;*/
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/*current_frequency = p->frequency; */
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/*state->current_frequency = p->frequency; */
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} else {
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fe->ops.tuner_ops.set_params(fe, p); msleep(300);
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fe->ops.tuner_ops.set_params(fe, p);
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msleep(300);
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s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
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switch (p->u.ofdm.bandwidth) {
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case BANDWIDTH_6_MHZ:
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_7_MHZ:
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_8_MHZ:
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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default:
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe, p);*/
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe, p); */
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/*Soft Reset chip*/
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
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switch (p->u.ofdm.bandwidth) {
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case BANDWIDTH_6_MHZ:
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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dvb_bandwidth = 6;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_7_MHZ:
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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dvb_bandwidth = 7;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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case BANDWIDTH_8_MHZ:
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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dvb_bandwidth = 8;
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s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
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break;
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default:
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe,p);*/
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/*Soft Reset chip*/
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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return 0;
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}
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/*fe->ops.tuner_ops.set_params(fe,p); */
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/*Soft Reset chip*/
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
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msleep(30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
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}
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@ -259,7 +246,6 @@ static int s5h1432_set_frontend(struct dvb_frontend *fe,
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return 0;
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}
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static int s5h1432_init(struct dvb_frontend *fe)
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{
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struct s5h1432_state *state = fe->demodulator_priv;
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@ -268,66 +254,62 @@ static int s5h1432_init(struct dvb_frontend *fe)
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state->current_frequency = 0;
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printk(KERN_INFO " s5h1432_init().\n");
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/*Set VSB mode as default, this also does a soft reset */
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/*Initialize registers */
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/*Set VSB mode as default, this also does a soft reset*/
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/*Initialize registers*/
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
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/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1); */
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
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/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1);*/
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s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
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/*For NXP tuner*/
|
||||
|
||||
/*For NXP tuner*/
|
||||
/*Set 3.3MHz as default IF frequency */
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4, 0x66);
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5, 0x66);
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7, 0xEE);
|
||||
/* Set reg 0x1E to get the full dynamic range */
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
|
||||
|
||||
/*Set 3.3MHz as default IF frequency*/
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
|
||||
/* Set reg 0x1E to get the full dynamic range */
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
|
||||
|
||||
/*Mode setting in demod*/
|
||||
/* Mode setting in demod */
|
||||
reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
|
||||
reg |= 0x80;
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
|
||||
/*Serial mode*/
|
||||
/* Serial mode */
|
||||
|
||||
/*Soft Reset chip*/
|
||||
/* Soft Reset chip */
|
||||
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
|
||||
msleep(30);
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
|
||||
s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int s5h1432_read_status(struct dvb_frontend *fe, fe_status_t *status)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
|
||||
u16 *signal_strength)
|
||||
u16 *signal_strength)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@ -397,34 +379,34 @@ error:
|
||||
kfree(state);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s5h1432_attach);
|
||||
|
||||
static struct dvb_frontend_ops s5h1432_ops = {
|
||||
|
||||
.info = {
|
||||
.name = "Samsung s5h1432 DVB-T Frontend",
|
||||
.type = FE_OFDM,
|
||||
.frequency_min = 177000000,
|
||||
.frequency_max = 858000000,
|
||||
.frequency_stepsize = 166666,
|
||||
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
||||
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
||||
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
|
||||
FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
|
||||
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
|
||||
},
|
||||
.name = "Samsung s5h1432 DVB-T Frontend",
|
||||
.type = FE_OFDM,
|
||||
.frequency_min = 177000000,
|
||||
.frequency_max = 858000000,
|
||||
.frequency_stepsize = 166666,
|
||||
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
||||
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
||||
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
|
||||
FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
|
||||
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER},
|
||||
|
||||
.init = s5h1432_init,
|
||||
.sleep = s5h1432_sleep,
|
||||
.set_frontend = s5h1432_set_frontend,
|
||||
.get_frontend = s5h1432_get_frontend,
|
||||
.get_tune_settings = s5h1432_get_tune_settings,
|
||||
.read_status = s5h1432_read_status,
|
||||
.read_ber = s5h1432_read_ber,
|
||||
.init = s5h1432_init,
|
||||
.sleep = s5h1432_sleep,
|
||||
.set_frontend = s5h1432_set_frontend,
|
||||
.get_frontend = s5h1432_get_frontend,
|
||||
.get_tune_settings = s5h1432_get_tune_settings,
|
||||
.read_status = s5h1432_read_status,
|
||||
.read_ber = s5h1432_read_ber,
|
||||
.read_signal_strength = s5h1432_read_signal_strength,
|
||||
.read_snr = s5h1432_read_snr,
|
||||
.read_ucblocks = s5h1432_read_ucblocks,
|
||||
.release = s5h1432_release,
|
||||
.read_snr = s5h1432_read_snr,
|
||||
.read_ucblocks = s5h1432_read_ucblocks,
|
||||
.release = s5h1432_release,
|
||||
};
|
||||
|
||||
module_param(debug, int, 0644);
|
||||
|
||||
@ -79,9 +79,9 @@ struct s5h1432_config {
|
||||
extern struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
|
||||
struct i2c_adapter *i2c);
|
||||
#else
|
||||
static inline struct dvb_frontend *s5h1432_attach(
|
||||
const struct s5h1432_config *config,
|
||||
struct i2c_adapter *i2c)
|
||||
static inline struct dvb_frontend *s5h1432_attach(const struct s5h1432_config
|
||||
*config,
|
||||
struct i2c_adapter *i2c)
|
||||
{
|
||||
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
|
||||
return NULL;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user