forked from Minki/linux
[ARM] S3C64XX: Initial support for PM (suspend to RAM)
Add the initial support for the S3C64XX based systems to use suspend-to-RAM to sleep. Includes basic debugging for use with the SMDK6410 usign the LEDs on the baseboard. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks
parent
4b637dc231
commit
bd117bd161
16
arch/arm/mach-s3c6400/include/mach/regs-clock.h
Normal file
16
arch/arm/mach-s3c6400/include/mach/regs-clock.h
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@ -0,0 +1,16 @@
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/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C64XX - clock register compatibility with s3c24xx
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <plat/regs-clock.h>
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@ -71,6 +71,15 @@ config S3C2410_PM_DEBUG
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Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
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for more information.
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config S3C_PM_DEBUG_LED_SMDK
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bool "SMDK LED suspend/resume debugging"
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depends on PM && (MACH_SMDK6410)
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help
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Say Y here to enable the use of the SMDK LEDs on the baseboard
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for debugging of the state of the suspend and resume process.
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Note, this currently only works for S3C64XX based SMDK boards.
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config S3C2410_PM_CHECK
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bool "S3C2410 PM Suspend Memory CRC"
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depends on PM && CRC32
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@ -127,6 +127,18 @@ extern void s3c_pm_dbg(const char *msg, ...);
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#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
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#endif
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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/**
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* s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
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* @set: set bits for the state of the LEDs
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* @clear: clear bits for the state of the LEDs.
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*/
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extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
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#else
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static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
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#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
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/* suspend memory checking */
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#ifdef CONFIG_S3C2410_PM_CHECK
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@ -21,11 +21,10 @@
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-irq.h>
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#include <asm/irq.h>
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@ -326,6 +325,9 @@ static int s3c_pm_enter(suspend_state_t state)
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S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
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/* LEDs should now be 1110 */
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s3c_pm_debug_smdkled(1 << 1, 0);
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s3c_pm_check_restore();
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/* ok, let's return from sleep */
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@ -24,6 +24,11 @@ obj-y += gpiolib.o
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obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
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obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
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# PM support
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_PM) += sleep.o
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# Device setup
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obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
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@ -157,6 +157,7 @@
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#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
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#define IRQ_EINT(x) S3C_EINT(x)
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#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
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/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
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* that they are sourced from the GPIO pins but with a different scheme for
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98
arch/arm/plat-s3c64xx/include/plat/pm-core.h
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98
arch/arm/plat-s3c64xx/include/plat/pm-core.h
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@ -0,0 +1,98 @@
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/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <plat/regs-gpio.h>
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static inline void s3c_pm_debug_init_uart(void)
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{
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u32 tmp = __raw_readl(S3C_PCLK_GATE);
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/* As a note, since the S3C64XX UARTs generally have multiple
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* clock sources, we simply enable PCLK at the moment and hope
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* that the resume settings for the UART are suitable for the
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* use with PCLK.
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*/
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tmp |= S3C_CLKCON_PCLK_UART0;
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tmp |= S3C_CLKCON_PCLK_UART1;
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tmp |= S3C_CLKCON_PCLK_UART2;
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tmp |= S3C_CLKCON_PCLK_UART3;
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__raw_writel(tmp, S3C_PCLK_GATE);
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udelay(10);
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}
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static inline void s3c_pm_arch_prepare_irqs(void)
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{
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/* VIC should have already been taken care of */
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/* clear any pending EINT0 interrupts */
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__raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
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}
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static inline void s3c_pm_arch_stop_clocks(void)
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{
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}
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static inline void s3c_pm_arch_show_resume_irqs(void)
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{
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}
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/* make these defines, we currently do not have any need to change
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* the IRQ wake controls depending on the CPU we are running on */
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#define s3c_irqwake_eintallow ((1 << 28) - 1)
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#define s3c_irqwake_intallow (0)
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static inline void s3c_pm_arch_update_uart(void __iomem *regs,
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struct pm_uart_save *save)
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{
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u32 ucon = __raw_readl(regs + S3C2410_UCON);
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u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
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u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
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u32 new_ucon;
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u32 delta;
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/* S3C64XX UART blocks only support level interrupts, so ensure that
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* when we restore unused UART blocks we force the level interrupt
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* settigs. */
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save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
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/* We have a constraint on changing the clock type of the UART
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* between UCLKx and PCLK, so ensure that when we restore UCON
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* that the CLK field is correctly modified if the bootloader
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* has changed anything.
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*/
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if (ucon_clk != save_clk) {
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new_ucon = save->ucon;
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delta = ucon_clk ^ save_clk;
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/* change from UCLKx => wrong PCLK,
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* either UCLK can be tested for by a bit-test
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* with UCLK0 */
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if (ucon_clk & S3C6400_UCON_UCLK0 &&
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!(save_clk & S3C6400_UCON_UCLK0) &&
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delta & S3C6400_UCON_PCLK2) {
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new_ucon &= ~S3C6400_UCON_UCLK0;
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} else if (delta == S3C6400_UCON_PCLK2) {
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/* as an precaution, don't change from
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* PCLK2 => PCLK or vice-versa */
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new_ucon ^= S3C6400_UCON_PCLK2;
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}
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S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
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ucon, new_ucon, save->ucon);
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save->ucon = new_ucon;
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}
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}
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@ -32,6 +32,7 @@
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#define S3C_HCLK_GATE S3C_CLKREG(0x30)
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#define S3C_PCLK_GATE S3C_CLKREG(0x34)
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#define S3C_SCLK_GATE S3C_CLKREG(0x38)
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#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
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/* CLKDIV0 */
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#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28)
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@ -14,6 +14,7 @@
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/sysdev.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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@ -26,6 +27,7 @@
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#include <mach/map.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#define eint_offset(irq) ((irq) - IRQ_EINT(0))
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#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
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@ -134,6 +136,7 @@ static struct irq_chip s3c_irq_eint = {
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.mask_ack = s3c_irq_eint_maskack,
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.ack = s3c_irq_eint_ack,
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.set_type = s3c_irq_eint_set_type,
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.set_wake = s3c_irqext_wake,
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};
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/* s3c_irq_demux_eint
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186
arch/arm/plat-s3c64xx/pm.c
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186
arch/arm/plat-s3c64xx/pm.c
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@ -0,0 +1,186 @@
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/* linux/arch/arm/plat-s3c64xx/pm.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX CPU PM support.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/pm.h>
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#include <plat/regs-sys.h>
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#include <plat/regs-gpio.h>
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#include <plat/regs-clock.h>
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#include <plat/regs-syscon-power.h>
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#include <plat/regs-gpio-memport.h>
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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#include <plat/gpio-bank-n.h>
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void s3c_pm_debug_smdkled(u32 set, u32 clear)
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{
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unsigned long flags;
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u32 reg;
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local_irq_save(flags);
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reg = __raw_readl(S3C64XX_GPNCON);
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reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
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S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
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reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
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S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
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__raw_writel(reg, S3C64XX_GPNCON);
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reg = __raw_readl(S3C64XX_GPNDAT);
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reg &= ~(clear << 12);
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reg |= set << 12;
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__raw_writel(reg, S3C64XX_GPNDAT);
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local_irq_restore(flags);
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}
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#endif
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static struct sleep_save core_save[] = {
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SAVE_ITEM(S3C_APLL_LOCK),
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SAVE_ITEM(S3C_MPLL_LOCK),
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SAVE_ITEM(S3C_EPLL_LOCK),
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SAVE_ITEM(S3C_CLK_SRC),
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SAVE_ITEM(S3C_CLK_DIV0),
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SAVE_ITEM(S3C_CLK_DIV1),
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SAVE_ITEM(S3C_CLK_DIV2),
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SAVE_ITEM(S3C_CLK_OUT),
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SAVE_ITEM(S3C_HCLK_GATE),
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SAVE_ITEM(S3C_PCLK_GATE),
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SAVE_ITEM(S3C_SCLK_GATE),
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SAVE_ITEM(S3C_MEM0_GATE),
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SAVE_ITEM(S3C_EPLL_CON1),
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SAVE_ITEM(S3C_EPLL_CON0),
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SAVE_ITEM(S3C64XX_MEM0DRVCON),
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SAVE_ITEM(S3C64XX_MEM1DRVCON),
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#ifndef CONFIG_CPU_FREQ
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SAVE_ITEM(S3C_APLL_CON),
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SAVE_ITEM(S3C_MPLL_CON),
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#endif
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};
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static struct sleep_save misc_save[] = {
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SAVE_ITEM(S3C64XX_AHB_CON0),
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SAVE_ITEM(S3C64XX_AHB_CON1),
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SAVE_ITEM(S3C64XX_AHB_CON2),
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SAVE_ITEM(S3C64XX_SPCON),
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SAVE_ITEM(S3C64XX_MEM0CONSTOP),
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SAVE_ITEM(S3C64XX_MEM1CONSTOP),
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SAVE_ITEM(S3C64XX_MEM0CONSLP0),
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SAVE_ITEM(S3C64XX_MEM0CONSLP1),
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SAVE_ITEM(S3C64XX_MEM1CONSLP),
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};
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void s3c_pm_configure_extint(void)
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{
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__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
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}
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void s3c_pm_save_gpios(void)
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{
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/* currently, unless the bootloader does something really stupid
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* the gpio blocks should be maintained over their sleep.
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*/
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}
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void s3c_pm_restore_gpios(void)
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{
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}
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void s3c_pm_restore_core(void)
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{
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__raw_writel(0, S3C64XX_EINT_MASK);
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s3c_pm_debug_smdkled(1 << 2, 0);
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s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
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s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
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}
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void s3c_pm_save_core(void)
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{
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s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
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s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
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}
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/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
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* put the per-cpu code in here until any new cpu comes along and changes
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* this.
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*/
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#include <plat/regs-gpio.h>
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static void s3c64xx_cpu_suspend(void)
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{
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unsigned long tmp;
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/* set our standby method to sleep */
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tmp = __raw_readl(S3C64XX_PWR_CFG);
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tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
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tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
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__raw_writel(tmp, S3C64XX_PWR_CFG);
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/* clear any old wakeup */
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__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
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S3C64XX_WAKEUP_STAT);
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/* set the LED state to 0110 over sleep */
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s3c_pm_debug_smdkled(3 << 1, 0xf);
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/* issue the standby signal into the pm unit. Note, we
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* issue a write-buffer drain just in case */
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tmp = 0;
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asm("b 1f\n\t"
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".align 5\n\t"
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"1:\n\t"
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"mcr p15, 0, %0, c7, c10, 5\n\t"
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"mcr p15, 0, %0, c7, c10, 4\n\t"
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"mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
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/* we should never get past here */
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panic("sleep resumed to originator?");
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}
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static void s3c64xx_pm_prepare(void)
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{
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/* store address of resume. */
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__raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
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/* ensure previous wakeup state is cleared before sleeping */
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__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
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}
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static int s3c64xx_pm_init(void)
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{
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pm_cpu_prep = s3c64xx_pm_prepare;
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pm_cpu_sleep = s3c64xx_cpu_suspend;
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pm_uart_udivslot = 1;
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return 0;
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}
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arch_initcall(s3c64xx_pm_init);
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144
arch/arm/plat-s3c64xx/sleep.S
Normal file
144
arch/arm/plat-s3c64xx/sleep.S
Normal file
@ -0,0 +1,144 @@
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/* linux/0arch/arm/plat-s3c64xx/sleep.S
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
|
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* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64XX CPU sleep code
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#undef S3C64XX_VA_GPIO
|
||||
#define S3C64XX_VA_GPIO (0x0)
|
||||
|
||||
#include <plat/regs-gpio.h>
|
||||
#include <plat/gpio-bank-n.h>
|
||||
|
||||
#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
|
||||
|
||||
.text
|
||||
|
||||
/* s3c_cpu_save
|
||||
*
|
||||
* Save enough processor state to allow the restart of the pm.c
|
||||
* code after resume.
|
||||
*
|
||||
* entry:
|
||||
* r0 = pointer to the save block
|
||||
*/
|
||||
|
||||
ENTRY(s3c_cpu_save)
|
||||
stmfd sp!, { r4 - r12, lr }
|
||||
|
||||
mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
|
||||
mrc p15, 0, r5, c3, c0, 0 @ Domain ID
|
||||
mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
|
||||
mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
|
||||
mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
|
||||
mrc p15, 0, r9, c1, c0, 0 @ Control register
|
||||
mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
|
||||
mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
|
||||
|
||||
stmia r0, { r4 - r13 } @ Save CP registers and SP
|
||||
|
||||
@@ save our state to ram
|
||||
bl s3c_pm_cb_flushcache
|
||||
|
||||
@@ call final suspend code
|
||||
ldr r0, =pm_cpu_sleep
|
||||
ldr pc, [r0]
|
||||
|
||||
@@ return to the caller, after the MMU is turned on.
|
||||
@@ restore the last bits of the stack and return.
|
||||
resume_with_mmu:
|
||||
ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save
|
||||
|
||||
.data
|
||||
|
||||
/* the next bit is code, but it requires easy access to the
|
||||
* s3c_sleep_save_phys data before the MMU is switched on, so
|
||||
* we store the code that needs this variable in the .data where
|
||||
* the value can be written to (the .text segment is RO).
|
||||
*/
|
||||
|
||||
.global s3c_sleep_save_phys
|
||||
s3c_sleep_save_phys:
|
||||
.word 0
|
||||
|
||||
/* Sleep magic, the word before the resume entry point so that the
|
||||
* bootloader can check for a resumeable image. */
|
||||
|
||||
.word 0x2bedf00d
|
||||
|
||||
/* s3c_cpu_reusme
|
||||
*
|
||||
* This is the entry point, stored by whatever method the bootloader
|
||||
* requires to get the kernel runnign again. This code expects to be
|
||||
* entered with no caches live and the MMU disabled. It will then
|
||||
* restore the MMU and other basic CP registers saved and restart
|
||||
* the kernel C code to finish the resume code.
|
||||
*/
|
||||
|
||||
ENTRY(s3c_cpu_resume)
|
||||
msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
|
||||
ldr r2, =LL_UART /* for debug */
|
||||
|
||||
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
|
||||
/* Initialise the GPIO state if we are debugging via the SMDK LEDs,
|
||||
* as the uboot version supplied resets these to inputs during the
|
||||
* resume checks.
|
||||
*/
|
||||
|
||||
ldr r3, =S3C64XX_PA_GPIO
|
||||
ldr r0, [ r3, #S3C64XX_GPNCON ]
|
||||
bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
|
||||
S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
|
||||
orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
|
||||
S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
|
||||
str r0, [ r3, #S3C64XX_GPNCON ]
|
||||
|
||||
ldr r0, [ r3, #S3C64XX_GPNDAT ]
|
||||
bic r0, r0, #0xf << 12 @ GPN12..15
|
||||
orr r0, r0, #1 << 15 @ GPN15
|
||||
str r0, [ r3, #S3C64XX_GPNDAT ]
|
||||
#endif
|
||||
|
||||
/* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
|
||||
* are thoroughly cleaned just in case the bootloader didn't do it
|
||||
* for us. */
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
|
||||
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
|
||||
mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
|
||||
@@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
|
||||
@@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
|
||||
|
||||
ldr r0, s3c_sleep_save_phys
|
||||
ldmia r0, { r4 - r13 }
|
||||
|
||||
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
|
||||
mcr p15, 0, r5, c3, c0, 0 @ Domain ID
|
||||
mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
|
||||
mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
|
||||
mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
|
||||
mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
|
||||
|
||||
mov r0, #0 @ restore copro access controls
|
||||
mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls
|
||||
mcr p15, 0, r0, c7, c5, 4
|
||||
|
||||
ldr r2, =resume_with_mmu
|
||||
mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */
|
||||
nop
|
||||
mov pc, r2 /* jump back */
|
||||
|
||||
.end
|
||||
Loading…
Reference in New Issue
Block a user