From 29af63443003afd41ce3b0e039ae97f0a09a87b8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Feb 2022 17:24:19 +0100 Subject: [PATCH 01/11] pinctrl: renesas: Simplify multiplication/shift logic "a * (1 << b)" == "a << b". Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/31eaa3226c61ecf653e2b031307eea42a9a3d54e.1645460548.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/sh_pfc.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 6b5836ea47de..da05eec97acc 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -132,9 +132,8 @@ struct pinmux_cfg_reg { .reg = r, .reg_width = r_width, \ .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ - (r_width / f_width) * (1 << f_width)), \ - .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ - { ids } + (r_width / f_width) << f_width), \ + .enum_ids = (const u16 [(r_width / f_width) << f_width]) { ids } /* * Describe a config register consisting of several fields of different widths From 74273035c7e486fa046ee7f80fbdb9c19169ef19 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Mar 2022 15:27:16 +0000 Subject: [PATCH 02/11] dt-bindings: pinctrl: renesas: Document RZ/G2UL pinctrl Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is almost identical to RZ/G2L and has lesser pins compared to RZ/G2L. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220315152717.20045-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 9ccf54870aa4..52df1b146174 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -11,8 +11,8 @@ maintainers: - Lad Prabhakar description: - The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO - controller. + The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and + GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function (port mode) or in alternate function mode. @@ -23,6 +23,7 @@ properties: oneOf: - items: - enum: + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - items: From dd035683fd1099729bb284cba967c8ee4a0cd64d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Apr 2022 10:08:32 +0200 Subject: [PATCH 03/11] pinctrl: renesas: checker: Rework drive and bias pin iteration The checker code to iterate over all drive strength and bias register description items is cumbersome, due to the repeated calculation of indices, and the use of hardcoded array sizes. The latter was done under the assumption they would never need to be changed, which turned out to be false. Increase readability by introducing helper macros to access drive strength and bias register description items. Increase maintainability by replacing hardcoded numbers by array sizes calculated at compile-time. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/5051ae56a1388ccf2d283dfc9624de2991cce914.1650355619.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 67 ++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index d0d4714731c1..220a08312c3c 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -1007,7 +1007,18 @@ static void __init sh_pfc_compare_groups(const char *drvname, static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) { const struct pinmux_drive_reg *drive_regs = info->drive_regs; +#define drive_nfields ARRAY_SIZE(drive_regs->fields) +#define drive_ofs(i) drive_regs[(i) / drive_nfields] +#define drive_reg(i) drive_ofs(i).reg +#define drive_bit(i) ((i) % drive_nfields) +#define drive_field(i) drive_ofs(i).fields[drive_bit(i)] const struct pinmux_bias_reg *bias_regs = info->bias_regs; +#define bias_npins ARRAY_SIZE(bias_regs->pins) +#define bias_ofs(i) bias_regs[(i) / bias_npins] +#define bias_puen(i) bias_ofs(i).puen +#define bias_pud(i) bias_ofs(i).pud +#define bias_bit(i) ((i) % bias_npins) +#define bias_pin(i) bias_ofs(i).pins[bias_bit(i)] const char *drvname = info->name; unsigned int *refcnts; unsigned int i, j, k; @@ -1076,17 +1087,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) if (!drive_regs) { sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n"); } else { - for (j = 0; drive_regs[j / 8].reg; j++) { - if (!drive_regs[j / 8].fields[j % 8].pin && - !drive_regs[j / 8].fields[j % 8].offset && - !drive_regs[j / 8].fields[j % 8].size) + for (j = 0; drive_reg(j); j++) { + if (!drive_field(j).pin && + !drive_field(j).offset && + !drive_field(j).size) continue; - if (drive_regs[j / 8].fields[j % 8].pin == pin->pin) + if (drive_field(j).pin == pin->pin) break; } - if (!drive_regs[j / 8].reg) + if (!drive_reg(j)) sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n", pin->name); } @@ -1164,20 +1175,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) for (i = 0; drive_regs && drive_regs[i].reg; i++) sh_pfc_check_drive_reg(info, &drive_regs[i]); - for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) { - if (!drive_regs[i / 8].fields[i % 8].pin && - !drive_regs[i / 8].fields[i % 8].offset && - !drive_regs[i / 8].fields[i % 8].size) + for (i = 0; drive_regs && drive_reg(i); i++) { + if (!drive_field(i).pin && !drive_field(i).offset && + !drive_field(i).size) continue; for (j = 0; j < i; j++) { - if (drive_regs[i / 8].fields[i % 8].pin == - drive_regs[j / 8].fields[j % 8].pin && - drive_regs[j / 8].fields[j % 8].offset && - drive_regs[j / 8].fields[j % 8].size) { - sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n", - drive_regs[i / 8].reg, i % 8, - drive_regs[j / 8].reg, j % 8); + if (drive_field(i).pin == drive_field(j).pin && + drive_field(j).offset && drive_field(j).size) { + sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n", + drive_reg(i), drive_bit(i), + drive_reg(j), drive_bit(j)); } } } @@ -1186,26 +1194,23 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++) sh_pfc_check_bias_reg(info, &bias_regs[i]); - for (i = 0; bias_regs && - (bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) { - if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE) + for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) { + if (bias_pin(i) == SH_PFC_PIN_NONE) continue; for (j = 0; j < i; j++) { - if (bias_regs[i / 32].pins[i % 32] != - bias_regs[j / 32].pins[j % 32]) + if (bias_pin(i) != bias_pin(j)) continue; - if (bias_regs[i / 32].puen && bias_regs[j / 32].puen) - sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", - bias_regs[i / 32].puen, i % 32, - bias_regs[j / 32].puen, j % 32); - if (bias_regs[i / 32].pud && bias_regs[j / 32].pud) - sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", - bias_regs[i / 32].pud, i % 32, - bias_regs[j / 32].pud, j % 32); + if (bias_puen(i) && bias_puen(j)) + sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n", + bias_puen(i), bias_bit(i), + bias_puen(j), bias_bit(j)); + if (bias_pud(i) && bias_pud(j)) + sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n", + bias_pud(i), bias_bit(i), + bias_pud(j), bias_bit(j)); } - } /* Check ioctrl registers */ From 2130ac189251ea479da985142e5cc8f0ee7c6107 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 20 Mar 2022 10:25:41 +0100 Subject: [PATCH 04/11] pinctrl: renesas: Allow up to 10 fields for drive_regs Needed to support R-Car E3 and RZ/G2E drive regs. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220320092542.2308-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/sh_pfc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index da05eec97acc..f33e9f5e83a4 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -161,7 +161,7 @@ struct pinmux_drive_reg_field { struct pinmux_drive_reg { u32 reg; - const struct pinmux_drive_reg_field fields[8]; + const struct pinmux_drive_reg_field fields[10]; }; #define PINMUX_DRIVE_REG(name, r) \ From 843394c61e9a71f0fb340a08b28cb42695baa929 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Sun, 20 Mar 2022 10:25:42 +0100 Subject: [PATCH 05/11] pinctrl: renesas: r8a77990: Add drive-strength According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is introduced to r8a77990. It is also documented for r8a774c0. Add it to the pinctrl driver. Signed-off-by: LUU HOAI Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220320092542.2308-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77990.c | 39 ++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 6c4ba9e16058..e2ca86d69a5a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -22,12 +22,12 @@ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ @@ -5030,6 +5030,39 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { + { RCAR_GP_PIN(3, 0), 18, 2 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 15, 2 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 2 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 9, 2 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 6, 2 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 3, 2 }, /* SD0_DAT3 */ + { RCAR_GP_PIN(3, 6), 0, 2 }, /* SD1_CLK */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { + { RCAR_GP_PIN(3, 7), 29, 2 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 8), 26, 2 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 9), 23, 2 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 10), 20, 2 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 11), 17, 2 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(4, 0), 14, 2 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 1), 11, 2 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 2), 8, 2 }, /* SD3_DAT0 */ + { RCAR_GP_PIN(4, 3), 5, 2 }, /* SD3_DAT1 */ + { RCAR_GP_PIN(4, 4), 2, 2 }, /* SD3_DAT2 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { + { RCAR_GP_PIN(4, 5), 29, 2 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 6), 26, 2 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 7), 23, 2 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 8), 20, 2 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */ + } }, + { }, +}; + enum ioctrl_regs { POCCTRL0, TDSELCTRL, @@ -5286,6 +5319,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, @@ -5312,6 +5346,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, From d43760b30832c1b497dbbd283b1f0593bddd3eb3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 11:48:50 +0200 Subject: [PATCH 06/11] pinctrl: renesas: r8a77990: Add RPC pins, groups, and functions Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77990 PFC driver. They are to be used when an Octal-SPI Flash or HyperFlash is connected. Redefine the QSPI[01] pin groups using the RPC DQ[0:7] pin data, to save memory. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/ec9735bb3468225e04ac6cb95e11a0e237b2b9ed.1648547080.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77990.c | 81 +++++++++++++++++++------- 1 file changed, 61 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index e2ca86d69a5a..c273bb743d3b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2827,16 +2827,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - /* QSPI0_IO2, QSPI0_IO3 */ - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), -}; -static const unsigned int qspi0_data_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK, -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { /* QSPI1_SPCLK, QSPI1_SSL */ @@ -2845,16 +2835,51 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ + +/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk_pins[] = { + /* Octal-SPI flash: C/SCLK */ + /* HyperFlash: CK, CK# */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6), +}; +static const unsigned int rpc_clk_mux[] = { + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, +}; +static const unsigned int rpc_ctrl_pins[] = { + /* Octal-SPI flash: S#/CS, DQS */ + /* HyperFlash: CS#, RDS */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11), +}; +static const unsigned int rpc_ctrl_mux[] = { + QSPI0_SSL_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int rpc_data_pins[] = { + /* DQ[0:7] */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - /* QSPI1_IO2, QSPI1_IO3 */ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), }; -static const unsigned int qspi1_data_mux[] = { +static const unsigned int rpc_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; +static const unsigned int rpc_reset_pins[] = { + /* RPC_RESET# */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int rpc_reset_mux[] = { + RPC_RESET_N_MARK, +}; +static const unsigned int rpc_int_pins[] = { + /* RPC_INT# */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int rpc_int_mux[] = { + RPC_INT_N_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { @@ -3758,7 +3783,7 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[255]; + struct sh_pfc_pin_group common[261]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_pin_group automotive[22]; #endif @@ -3907,11 +3932,17 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - BUS_DATA_PIN_GROUP(qspi0_data, 2), - BUS_DATA_PIN_GROUP(qspi0_data, 4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - BUS_DATA_PIN_GROUP(qspi1_data, 2), - BUS_DATA_PIN_GROUP(qspi1_data, 4), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), + SH_PFC_PIN_GROUP(rpc_ctrl), + SH_PFC_PIN_GROUP(rpc_data), + SH_PFC_PIN_GROUP(rpc_reset), + SH_PFC_PIN_GROUP(rpc_int), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_ctrl_a), @@ -4336,6 +4367,15 @@ static const char * const qspi1_groups[] = { "qspi1_data4", }; +static const char * const rpc_groups[] = { + "rpc_clk1", + "rpc_clk2", + "rpc_ctrl", + "rpc_data", + "rpc_reset", + "rpc_int", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -4492,7 +4532,7 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[49]; + struct sh_pfc_function common[50]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_function automotive[5]; #endif @@ -4531,6 +4571,7 @@ static const struct { SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), From ff06501c1aa30342602e94ccacce167feec92c4b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 11:48:51 +0200 Subject: [PATCH 07/11] pinctrl: renesas: r8a77995: Add QSPI and RPC pins, groups, and functions Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77995 PFC driver. They are to be used when a QSPI Flash, Octal-SPI Flash, or HyperFlash is connected. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/19a3bccd0ec830846578a38b4c80dccb195109a0.1648547080.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77995.c | 98 ++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index 445c903a121a..0cdf70dd9dea 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -1682,6 +1682,68 @@ static const unsigned int pwm3_c_mux[] = { PWM3_C_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; + +/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk_pins[] = { + /* Octal-SPI flash: C/SCLK */ + /* HyperFlash: CK, CK# */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6), +}; +static const unsigned int rpc_clk_mux[] = { + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, +}; +static const unsigned int rpc_ctrl_pins[] = { + /* Octal-SPI flash: S#/CS, DQS */ + /* HyperFlash: CS#, RDS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11), +}; +static const unsigned int rpc_ctrl_mux[] = { + QSPI0_SSL_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int rpc_data_pins[] = { + /* DQ[0:7] */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), + RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8), + RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10), +}; +static const unsigned int rpc_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; +static const unsigned int rpc_reset_pins[] = { + /* RPC_RESET# */ + RCAR_GP_PIN(6, 12), +}; +static const unsigned int rpc_reset_mux[] = { + RPC_RESET_N_MARK, +}; +static const unsigned int rpc_int_pins[] = { + /* RPC_INT# */ + RCAR_GP_PIN(6, 13), +}; +static const unsigned int rpc_int_mux[] = { + RPC_INT_N_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -2085,6 +2147,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_a), SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm3_c), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), + SH_PFC_PIN_GROUP(rpc_ctrl), + SH_PFC_PIN_GROUP(rpc_data), + SH_PFC_PIN_GROUP(rpc_reset), + SH_PFC_PIN_GROUP(rpc_int), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_data_b), @@ -2277,6 +2351,27 @@ static const char * const pwm3_groups[] = { "pwm3_c", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + +static const char * const rpc_groups[] = { + "rpc_clk1", + "rpc_clk2", + "rpc_ctrl", + "rpc_data", + "rpc_reset", + "rpc_int", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -2373,6 +2468,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), From bfc69bdbaad141ac408e6de86b7e0d771c8e3ccb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 1 Apr 2022 19:02:30 +0100 Subject: [PATCH 08/11] pinctrl: renesas: rzg2l: Add RZ/G2UL support RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible to take care of these differences by adding r9a07g043_data with r9a07g043_gpio_configs and rzg2l_dedicated_pins.common. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220401180230.19950-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/Kconfig | 5 +- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 200 ++++++++++++++---------- 2 files changed, 124 insertions(+), 81 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 6b38720c56e3..b9383a75a215 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -38,6 +38,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0 + select PINCTRL_RZG2L if ARCH_R9A07G043 select PINCTRL_RZG2L if ARCH_R9A07G044 select PINCTRL_RZG2L if ARCH_R9A07G054 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 @@ -184,14 +185,14 @@ config PINCTRL_RZA2 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_RZG2L - bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST + bool "pin control support for RZ/{G2L,G2UL,V2L}" if COMPILE_TEST depends on OF select GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help - This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L} + This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L} platforms. config PINCTRL_PFC_R8A77470 diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index cb805502fb0f..86a7096640ad 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -996,83 +996,112 @@ static const u32 rzg2l_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; -static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = { - { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, - (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, - { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, - (PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) }, - { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, - (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, - { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, - { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, - { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, - { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, - { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, - { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, - { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, - { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, - { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, - { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, - (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, - { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, - { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, - { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, - { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, - { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, +static const u32 r9a07g043_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +}; + +static struct { + struct rzg2l_dedicated_configs common[35]; + struct rzg2l_dedicated_configs rzg2l_pins[7]; +} rzg2l_dedicated_pins = { + .common = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, + (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, + (PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, + (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, + { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, + { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, + { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, + { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, + { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, + { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, + { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, + }, + .rzg2l_pins = { + { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + } }; static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) @@ -1250,15 +1279,28 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) return 0; } +static struct rzg2l_pinctrl_data r9a07g043_data = { + .port_pins = rzg2l_gpio_names, + .port_pin_configs = r9a07g043_gpio_configs, + .dedicated_pins = rzg2l_dedicated_pins.common, + .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), +}; + static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = rzg2l_gpio_configs, - .dedicated_pins = rzg2l_dedicated_pins, + .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), - .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins), + .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), }; static const struct of_device_id rzg2l_pinctrl_of_table[] = { + { + .compatible = "renesas,r9a07g043-pinctrl", + .data = &r9a07g043_data, + }, { .compatible = "renesas,r9a07g044-pinctrl", .data = &r9a07g044_data, From 1db28b78b35de7a6828091c9d5d7a179f3681680 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 6 Apr 2022 08:53:18 +0100 Subject: [PATCH 09/11] pinctrl: renesas: Select PINCTRL_RZG2L if ARCH_RZG2L is enabled GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of selecting PINCTRL_RZG2L config for each SoC select PINCTRL_RZG2L config option if ARCH_RZG2L is enabled. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220406075318.14385-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/Kconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index b9383a75a215..961007ce7b3a 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -38,9 +38,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0 - select PINCTRL_RZG2L if ARCH_R9A07G043 - select PINCTRL_RZG2L if ARCH_R9A07G044 - select PINCTRL_RZG2L if ARCH_R9A07G054 + select PINCTRL_RZG2L if ARCH_RZG2L select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 From c3b423fd08a5e9d4a9fe7cc0743a9b6427db2237 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Apr 2022 14:56:40 +0200 Subject: [PATCH 10/11] pinctrl: renesas: Remove unneeded #include The last __init annotations were removed from these source files almost one decade ago. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/fb71c409ea3ad76163496e305dc955ca8e84416d.1649681741.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/gpio.c | 1 - drivers/pinctrl/renesas/pfc-emev2.c | 1 - drivers/pinctrl/renesas/pfc-sh7722.c | 1 - drivers/pinctrl/renesas/pfc-sh7723.c | 1 - drivers/pinctrl/renesas/pfc-sh7724.c | 1 - drivers/pinctrl/renesas/pfc-sh7734.c | 1 - drivers/pinctrl/renesas/pfc-sh7757.c | 1 - drivers/pinctrl/renesas/pfc-sh7785.c | 1 - drivers/pinctrl/renesas/pfc-sh7786.c | 1 - drivers/pinctrl/renesas/pfc-shx3.c | 1 - drivers/pinctrl/renesas/pinctrl.c | 1 - 11 files changed, 11 deletions(-) diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index ad06f5355d1e..ea3d38b4af8d 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include diff --git a/drivers/pinctrl/renesas/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c index 2326d348447d..b3f50853d66e 100644 --- a/drivers/pinctrl/renesas/pfc-emev2.c +++ b/drivers/pinctrl/renesas/pfc-emev2.c @@ -4,7 +4,6 @@ * * Copyright (C) 2015 Niklas Söderlund */ -#include #include #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh7722.c b/drivers/pinctrl/renesas/pfc-sh7722.c index 13d9967dce59..635e3dca2703 100644 --- a/drivers/pinctrl/renesas/pfc-sh7722.c +++ b/drivers/pinctrl/renesas/pfc-sh7722.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 -#include #include #include diff --git a/drivers/pinctrl/renesas/pfc-sh7723.c b/drivers/pinctrl/renesas/pfc-sh7723.c index 6f08f527c010..94c7acf591d6 100644 --- a/drivers/pinctrl/renesas/pfc-sh7723.c +++ b/drivers/pinctrl/renesas/pfc-sh7723.c @@ -5,7 +5,6 @@ * Copyright (C) 2008 Magnus Damm */ -#include #include #include diff --git a/drivers/pinctrl/renesas/pfc-sh7724.c b/drivers/pinctrl/renesas/pfc-sh7724.c index 7a18afecda2c..551da3113ce3 100644 --- a/drivers/pinctrl/renesas/pfc-sh7724.c +++ b/drivers/pinctrl/renesas/pfc-sh7724.c @@ -10,7 +10,6 @@ * Copyright (C) 2008 Magnus Damm */ -#include #include #include diff --git a/drivers/pinctrl/renesas/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c index dbc36079c381..a4e02fc7ea34 100644 --- a/drivers/pinctrl/renesas/pfc-sh7734.c +++ b/drivers/pinctrl/renesas/pfc-sh7734.c @@ -5,7 +5,6 @@ * Copyright (C) 2012 Renesas Solutions Corp. * Copyright (C) 2012 Nobuhiro Iwamatsu */ -#include #include #include diff --git a/drivers/pinctrl/renesas/pfc-sh7757.c b/drivers/pinctrl/renesas/pfc-sh7757.c index 064e987b09cb..79cf7c42c35d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7757.c +++ b/drivers/pinctrl/renesas/pfc-sh7757.c @@ -10,7 +10,6 @@ * Copyright (C) 2008 Magnus Damm */ -#include #include #include diff --git a/drivers/pinctrl/renesas/pfc-sh7785.c b/drivers/pinctrl/renesas/pfc-sh7785.c index c4c1e288c53e..62389f7a1de1 100644 --- a/drivers/pinctrl/renesas/pfc-sh7785.c +++ b/drivers/pinctrl/renesas/pfc-sh7785.c @@ -5,7 +5,6 @@ * Copyright (C) 2008 Magnus Damm */ -#include #include #include diff --git a/drivers/pinctrl/renesas/pfc-sh7786.c b/drivers/pinctrl/renesas/pfc-sh7786.c index b8a098cd7721..4ed31d78fe30 100644 --- a/drivers/pinctrl/renesas/pfc-sh7786.c +++ b/drivers/pinctrl/renesas/pfc-sh7786.c @@ -10,7 +10,6 @@ * Copyright (C) 2008 Magnus Damm */ -#include #include #include diff --git a/drivers/pinctrl/renesas/pfc-shx3.c b/drivers/pinctrl/renesas/pfc-shx3.c index 22e812850964..96a65d83774f 100644 --- a/drivers/pinctrl/renesas/pfc-shx3.c +++ b/drivers/pinctrl/renesas/pfc-shx3.c @@ -4,7 +4,6 @@ * * Copyright (C) 2010 Paul Mundt */ -#include #include #include diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 4c37aebc75b8..b438d24c13b5 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include From f7bc5f52d2354b41d5a111942be7ee01e5560c78 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 13 Apr 2022 15:52:04 +0200 Subject: [PATCH 11/11] pinctrl: renesas: rzg2l: Restore pin config order The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SWDIO" pin definition. Fix the order, to increase uniformity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/f9b18be9e5402531d058bd2479b4881377f9b8b6.1649857772.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 86a7096640ad..a48cac55152c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1026,7 +1026,7 @@ static struct { { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, - (PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) }, + (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },