drm/amdgpu/sienna_cichlid: add SMU i2c support (v2)
Enable SMU i2c bus access for sienna_cichlid asics. v2: change callback name Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
1bc734759f
commit
bc50ca291e
@ -25,6 +25,7 @@
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#include <linux/firmware.h>
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#include <linux/pci.h>
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#include <linux/i2c.h>
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#include "amdgpu.h"
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#include "amdgpu_smu.h"
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#include "atomfirmware.h"
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@ -57,6 +58,8 @@
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#undef pr_info
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#undef pr_debug
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#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
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#define FEATURE_MASK(feature) (1ULL << feature)
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#define SMC_DPM_FEATURE ( \
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FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
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@ -367,6 +370,8 @@ static int sienna_cichlid_tables_init(struct smu_context *smu)
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
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SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
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@ -2425,11 +2430,245 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
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dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
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}
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static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write,
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uint8_t address, uint32_t numbytes,
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uint8_t *data)
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{
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int i;
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BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
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req->I2CcontrollerPort = 0;
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req->I2CSpeed = 2;
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req->SlaveAddress = address;
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req->NumCmds = numbytes;
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for (i = 0; i < numbytes; i++) {
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SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
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/* First 2 bytes are always write for lower 2b EEPROM address */
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if (i < 2)
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cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
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else
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cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
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/* Add RESTART for read after address filled */
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cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
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/* Add STOP in the end */
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cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
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/* Fill with data regardless if read or write to simplify code */
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cmd->ReadWriteData = data[i];
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}
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}
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static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
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uint8_t address,
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uint8_t *data,
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uint32_t numbytes)
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{
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uint32_t i, ret = 0;
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SwI2cRequest_t req;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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struct smu_table_context *smu_table = &adev->smu.smu_table;
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struct smu_table *table = &smu_table->driver_table;
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memset(&req, 0, sizeof(req));
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sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
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mutex_lock(&adev->smu.mutex);
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/* Now read data starting with that address */
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ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
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true);
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mutex_unlock(&adev->smu.mutex);
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if (!ret) {
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SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
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/* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
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for (i = 0; i < numbytes; i++)
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data[i] = res->SwI2cCmds[i].ReadWriteData;
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dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
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(uint16_t)address, numbytes);
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print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
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8, 1, data, numbytes, false);
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} else
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dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
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return ret;
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}
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static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
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uint8_t address,
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uint8_t *data,
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uint32_t numbytes)
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{
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uint32_t ret;
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SwI2cRequest_t req;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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memset(&req, 0, sizeof(req));
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sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
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mutex_lock(&adev->smu.mutex);
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ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
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mutex_unlock(&adev->smu.mutex);
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if (!ret) {
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dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
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(uint16_t)address, numbytes);
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print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
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8, 1, data, numbytes, false);
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/*
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* According to EEPROM spec there is a MAX of 10 ms required for
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* EEPROM to flush internal RX buffer after STOP was issued at the
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* end of write transaction. During this time the EEPROM will not be
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* responsive to any more commands - so wait a bit more.
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*/
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msleep(10);
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} else
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dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
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return ret;
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}
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static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
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struct i2c_msg *msgs, int num)
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{
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uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
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uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
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for (i = 0; i < num; i++) {
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/*
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* SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
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* once and hence the data needs to be spliced into chunks and sent each
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* chunk separately
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*/
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data_size = msgs[i].len - 2;
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data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
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next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
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data_ptr = msgs[i].buf + 2;
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for (j = 0; j < data_size / data_chunk_size; j++) {
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/* Insert the EEPROM dest addess, bits 0-15 */
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data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
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data_chunk[1] = (next_eeprom_addr & 0xff);
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if (msgs[i].flags & I2C_M_RD) {
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ret = sienna_cichlid_i2c_read_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, MAX_SW_I2C_COMMANDS);
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memcpy(data_ptr, data_chunk + 2, data_chunk_size);
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} else {
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memcpy(data_chunk + 2, data_ptr, data_chunk_size);
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ret = sienna_cichlid_i2c_write_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, MAX_SW_I2C_COMMANDS);
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}
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if (ret) {
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num = -EIO;
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goto fail;
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}
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next_eeprom_addr += data_chunk_size;
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data_ptr += data_chunk_size;
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}
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if (data_size % data_chunk_size) {
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data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
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data_chunk[1] = (next_eeprom_addr & 0xff);
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if (msgs[i].flags & I2C_M_RD) {
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ret = sienna_cichlid_i2c_read_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, (data_size % data_chunk_size) + 2);
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memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
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} else {
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memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
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ret = sienna_cichlid_i2c_write_data(i2c_adap,
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(uint8_t)msgs[i].addr,
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data_chunk, (data_size % data_chunk_size) + 2);
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}
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if (ret) {
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num = -EIO;
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goto fail;
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}
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}
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}
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fail:
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return num;
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}
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static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
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.master_xfer = sienna_cichlid_i2c_xfer,
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.functionality = sienna_cichlid_i2c_func,
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};
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static bool sienna_cichlid_i2c_adapter_is_added(struct i2c_adapter *control)
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{
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struct amdgpu_device *adev = to_amdgpu_device(control);
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return control->dev.parent == &adev->pdev->dev;
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}
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static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
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{
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struct amdgpu_device *adev = to_amdgpu_device(control);
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int res;
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/* smu_i2c_eeprom_init may be called twice in sriov */
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if (sienna_cichlid_i2c_adapter_is_added(control))
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return 0;
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control->owner = THIS_MODULE;
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control->class = I2C_CLASS_SPD;
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control->dev.parent = &adev->pdev->dev;
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control->algo = &sienna_cichlid_i2c_algo;
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snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
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res = i2c_add_adapter(control);
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if (res)
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DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
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return res;
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}
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static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
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{
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if (!sienna_cichlid_i2c_adapter_is_added(control))
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return;
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i2c_del_adapter(control);
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}
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static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
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.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
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.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
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.dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
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.dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
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.i2c_init = sienna_cichlid_i2c_control_init,
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.i2c_fini = sienna_cichlid_i2c_control_fini,
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.print_clk_levels = sienna_cichlid_print_clk_levels,
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.force_clk_levels = sienna_cichlid_force_clk_levels,
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.populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
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