forked from Minki/linux
Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue
Tony Nguyen says: ==================== 1GbE Intel Wired LAN Driver Updates 2021-04-16 This series contains updates to igb and igc drivers. Ederson adjusts Tx buffer distributions in Qav mode to improve TSN-aware traffic for igb. He also enable PPS support and auxiliary PHC functions for igc. Grzegorz checks that the MTA register was properly written and retries if not for igb. Sasha adds reporting of EEE low power idle counters to ethtool and fixes a return value being overwritten through looping for igc. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
bc45f524d9
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@ -340,10 +340,10 @@
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#define I210_RXPBSIZE_PB_32KB 0x00000020
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#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
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#define I210_TXPBSIZE_MASK 0xC0FFFFFF
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#define I210_TXPBSIZE_PB0_8KB (8 << 0)
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#define I210_TXPBSIZE_PB1_8KB (8 << 6)
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#define I210_TXPBSIZE_PB2_4KB (4 << 12)
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#define I210_TXPBSIZE_PB3_4KB (4 << 18)
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#define I210_TXPBSIZE_PB0_6KB (6 << 0)
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#define I210_TXPBSIZE_PB1_6KB (6 << 6)
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#define I210_TXPBSIZE_PB2_6KB (6 << 12)
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#define I210_TXPBSIZE_PB3_6KB (6 << 18)
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#define I210_DTXMXPKTSZ_DEFAULT 0x00000098
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@ -483,6 +483,31 @@ static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
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return hash_value;
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}
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/**
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* igb_i21x_hw_doublecheck - double checks potential HW issue in i21X
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* @hw: pointer to the HW structure
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*
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* Checks if multicast array is wrote correctly
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* If not then rewrites again to register
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**/
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static void igb_i21x_hw_doublecheck(struct e1000_hw *hw)
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{
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bool is_failed;
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int i;
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do {
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is_failed = false;
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for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) {
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if (array_rd32(E1000_MTA, i) != hw->mac.mta_shadow[i]) {
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is_failed = true;
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array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
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wrfl();
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break;
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}
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}
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} while (is_failed);
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}
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/**
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* igb_update_mc_addr_list - Update Multicast addresses
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* @hw: pointer to the HW structure
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@ -516,6 +541,8 @@ void igb_update_mc_addr_list(struct e1000_hw *hw,
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for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
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array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
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wrfl();
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if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)
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igb_i21x_hw_doublecheck(hw);
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}
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/**
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@ -1921,8 +1921,8 @@ static void igb_setup_tx_mode(struct igb_adapter *adapter)
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*/
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val = rd32(E1000_TXPBS);
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val &= ~I210_TXPBSIZE_MASK;
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val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB |
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I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB;
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val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
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I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
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wr32(E1000_TXPBS, val);
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val = rd32(E1000_RXPBS);
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@ -28,6 +28,11 @@ void igc_ethtool_set_ops(struct net_device *);
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#define MAX_ETYPE_FILTER 8
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#define IGC_RETA_SIZE 128
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/* SDP support */
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#define IGC_N_EXTTS 2
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#define IGC_N_PEROUT 2
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#define IGC_N_SDP 4
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enum igc_mac_filter_type {
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IGC_MAC_FILTER_TYPE_DST = 0,
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IGC_MAC_FILTER_TYPE_SRC
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@ -223,6 +228,14 @@ struct igc_adapter {
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char fw_version[32];
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struct bpf_prog *xdp_prog;
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bool pps_sys_wrap_on;
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struct ptp_pin_desc sdp_config[IGC_N_SDP];
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struct {
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struct timespec64 start;
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struct timespec64 period;
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} perout[IGC_N_PEROUT];
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};
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void igc_up(struct igc_adapter *adapter);
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@ -8,6 +8,8 @@
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#define REQ_TX_DESCRIPTOR_MULTIPLE 8
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#define REQ_RX_DESCRIPTOR_MULTIPLE 8
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#define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
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#define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */
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#define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
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/* Definitions for power management and wakeup registers */
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@ -96,6 +98,9 @@
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#define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
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#define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
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#define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
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#define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
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/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
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#define MAX_JUMBO_FRAME_SIZE 0x2600
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@ -403,6 +408,64 @@
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#define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
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#define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */
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/* Timer selection bits */
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#define IGC_AUX_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for auxiliary time stamp */
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#define IGC_AUX_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for auxiliary time stamp */
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#define IGC_AUX_IO_TIMER_SEL_SYSTIM2 (2u << 30) /* Select SYSTIM2 for auxiliary time stamp */
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#define IGC_AUX_IO_TIMER_SEL_SYSTIM3 (3u << 30) /* Select SYSTIM3 for auxiliary time stamp */
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#define IGC_TT_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for target time stamp */
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#define IGC_TT_IO_TIMER_SEL_SYSTIM1 (1u << 30) /* Select SYSTIM1 for target time stamp */
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#define IGC_TT_IO_TIMER_SEL_SYSTIM2 (2u << 30) /* Select SYSTIM2 for target time stamp */
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#define IGC_TT_IO_TIMER_SEL_SYSTIM3 (3u << 30) /* Select SYSTIM3 for target time stamp */
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/* TSAUXC Configuration Bits */
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#define IGC_TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
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#define IGC_TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */
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#define IGC_TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
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#define IGC_TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */
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#define IGC_TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
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#define IGC_TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */
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#define IGC_TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
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#define IGC_TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */
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#define IGC_TSAUXC_PLSG BIT(17) /* Generate a pulse. */
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#define IGC_TSAUXC_DISABLE1 BIT(27) /* Disable SYSTIM0 Count Operation. */
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#define IGC_TSAUXC_DISABLE2 BIT(28) /* Disable SYSTIM1 Count Operation. */
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#define IGC_TSAUXC_DISABLE3 BIT(29) /* Disable SYSTIM2 Count Operation. */
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#define IGC_TSAUXC_DIS_TS_CLEAR BIT(30) /* Disable EN_TT0/1 auto clear. */
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#define IGC_TSAUXC_DISABLE0 BIT(31) /* Disable SYSTIM0 Count Operation. */
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/* SDP Configuration Bits */
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#define IGC_AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
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#define IGC_AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
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#define IGC_AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
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#define IGC_AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
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#define IGC_AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
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#define IGC_AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
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#define IGC_AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */
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#define IGC_AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
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#define IGC_AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */
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#define IGC_AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */
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#define IGC_TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
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#define IGC_TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
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#define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
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#define IGC_TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
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#define IGC_TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */
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#define IGC_TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
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#define IGC_TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
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#define IGC_TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
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#define IGC_TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
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#define IGC_TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */
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#define IGC_TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
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#define IGC_TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
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#define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
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#define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
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#define IGC_TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */
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#define IGC_TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
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#define IGC_TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
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#define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
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#define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
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#define IGC_TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */
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/* Transmit Scheduling */
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#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001
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#define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008
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@ -65,6 +65,8 @@ static const struct igc_stats igc_gstrings_stats[] = {
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IGC_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
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IGC_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped),
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IGC_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
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IGC_STAT("tx_lpi_counter", stats.tlpic),
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IGC_STAT("rx_lpi_counter", stats.rlpic),
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};
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#define IGC_NETDEV_STAT(_net_stat) { \
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@ -229,10 +229,11 @@ static s32 igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
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if (offset >= nvm->word_size || (words > (nvm->word_size - offset)) ||
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words == 0) {
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hw_dbg("nvm parameter(s) out of bounds\n");
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goto out;
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return ret_val;
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}
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for (i = 0; i < words; i++) {
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ret_val = -IGC_ERR_NVM;
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eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) |
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(data[i] << IGC_NVM_RW_REG_DATA) |
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IGC_NVM_RW_REG_START;
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@ -254,7 +255,6 @@ static s32 igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
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}
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}
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out:
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return ret_val;
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}
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@ -4250,9 +4250,20 @@ igc_features_check(struct sk_buff *skb, struct net_device *dev,
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static void igc_tsync_interrupt(struct igc_adapter *adapter)
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{
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u32 ack, tsauxc, sec, nsec, tsicr;
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struct igc_hw *hw = &adapter->hw;
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u32 tsicr = rd32(IGC_TSICR);
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u32 ack = 0;
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struct ptp_clock_event event;
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struct timespec64 ts;
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tsicr = rd32(IGC_TSICR);
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ack = 0;
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if (tsicr & IGC_TSICR_SYS_WRAP) {
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event.type = PTP_CLOCK_PPS;
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if (adapter->ptp_caps.pps)
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ptp_clock_event(adapter->ptp_clock, &event);
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ack |= IGC_TSICR_SYS_WRAP;
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}
|
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if (tsicr & IGC_TSICR_TXTS) {
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/* retrieve hardware timestamp */
|
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|
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@ -4260,6 +4271,54 @@ static void igc_tsync_interrupt(struct igc_adapter *adapter)
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ack |= IGC_TSICR_TXTS;
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}
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if (tsicr & IGC_TSICR_TT0) {
|
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spin_lock(&adapter->tmreg_lock);
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ts = timespec64_add(adapter->perout[0].start,
|
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adapter->perout[0].period);
|
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wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
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wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec);
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tsauxc = rd32(IGC_TSAUXC);
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tsauxc |= IGC_TSAUXC_EN_TT0;
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wr32(IGC_TSAUXC, tsauxc);
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adapter->perout[0].start = ts;
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spin_unlock(&adapter->tmreg_lock);
|
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ack |= IGC_TSICR_TT0;
|
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}
|
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|
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if (tsicr & IGC_TSICR_TT1) {
|
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spin_lock(&adapter->tmreg_lock);
|
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ts = timespec64_add(adapter->perout[1].start,
|
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adapter->perout[1].period);
|
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wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
|
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wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec);
|
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tsauxc = rd32(IGC_TSAUXC);
|
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tsauxc |= IGC_TSAUXC_EN_TT1;
|
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wr32(IGC_TSAUXC, tsauxc);
|
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adapter->perout[1].start = ts;
|
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spin_unlock(&adapter->tmreg_lock);
|
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ack |= IGC_TSICR_TT1;
|
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}
|
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|
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if (tsicr & IGC_TSICR_AUTT0) {
|
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nsec = rd32(IGC_AUXSTMPL0);
|
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sec = rd32(IGC_AUXSTMPH0);
|
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event.type = PTP_CLOCK_EXTTS;
|
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event.index = 0;
|
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event.timestamp = sec * NSEC_PER_SEC + nsec;
|
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ptp_clock_event(adapter->ptp_clock, &event);
|
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ack |= IGC_TSICR_AUTT0;
|
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}
|
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|
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if (tsicr & IGC_TSICR_AUTT1) {
|
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nsec = rd32(IGC_AUXSTMPL1);
|
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sec = rd32(IGC_AUXSTMPH1);
|
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event.type = PTP_CLOCK_EXTTS;
|
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event.index = 1;
|
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event.timestamp = sec * NSEC_PER_SEC + nsec;
|
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ptp_clock_event(adapter->ptp_clock, &event);
|
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ack |= IGC_TSICR_AUTT1;
|
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}
|
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|
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/* acknowledge the interrupts */
|
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wr32(IGC_TSICR, ack);
|
||||
}
|
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|
|
|
|||
|
|
@ -120,12 +120,289 @@ static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
|
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return 0;
|
||||
}
|
||||
|
||||
static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
|
||||
{
|
||||
u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
|
||||
static const u32 mask[IGC_N_SDP] = {
|
||||
IGC_CTRL_SDP0_DIR,
|
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IGC_CTRL_SDP1_DIR,
|
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IGC_CTRL_EXT_SDP2_DIR,
|
||||
IGC_CTRL_EXT_SDP3_DIR,
|
||||
};
|
||||
|
||||
if (input)
|
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*ptr &= ~mask[pin];
|
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else
|
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*ptr |= mask[pin];
|
||||
}
|
||||
|
||||
static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
|
||||
{
|
||||
static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
|
||||
IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
|
||||
};
|
||||
static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
|
||||
IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
|
||||
};
|
||||
static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
|
||||
IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
|
||||
};
|
||||
static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
|
||||
IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
|
||||
IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
|
||||
};
|
||||
static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
|
||||
IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
|
||||
IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
|
||||
};
|
||||
static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
|
||||
IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
|
||||
IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
|
||||
};
|
||||
static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
|
||||
IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
|
||||
IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
|
||||
};
|
||||
static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
|
||||
IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
|
||||
IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
|
||||
};
|
||||
struct igc_hw *hw = &igc->hw;
|
||||
u32 ctrl, ctrl_ext, tssdp = 0;
|
||||
|
||||
ctrl = rd32(IGC_CTRL);
|
||||
ctrl_ext = rd32(IGC_CTRL_EXT);
|
||||
tssdp = rd32(IGC_TSSDP);
|
||||
|
||||
igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
|
||||
|
||||
/* Make sure this pin is not enabled as an input. */
|
||||
if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
|
||||
tssdp &= ~IGC_AUX0_TS_SDP_EN;
|
||||
|
||||
if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
|
||||
tssdp &= ~IGC_AUX1_TS_SDP_EN;
|
||||
|
||||
tssdp &= ~igc_ts_sdp_sel_clr[pin];
|
||||
if (freq) {
|
||||
if (chan == 1)
|
||||
tssdp |= igc_ts_sdp_sel_fc1[pin];
|
||||
else
|
||||
tssdp |= igc_ts_sdp_sel_fc0[pin];
|
||||
} else {
|
||||
if (chan == 1)
|
||||
tssdp |= igc_ts_sdp_sel_tt1[pin];
|
||||
else
|
||||
tssdp |= igc_ts_sdp_sel_tt0[pin];
|
||||
}
|
||||
tssdp |= igc_ts_sdp_en[pin];
|
||||
|
||||
wr32(IGC_TSSDP, tssdp);
|
||||
wr32(IGC_CTRL, ctrl);
|
||||
wr32(IGC_CTRL_EXT, ctrl_ext);
|
||||
}
|
||||
|
||||
static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
|
||||
{
|
||||
static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
|
||||
IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
|
||||
};
|
||||
static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
|
||||
IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
|
||||
};
|
||||
static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
|
||||
IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
|
||||
};
|
||||
struct igc_hw *hw = &igc->hw;
|
||||
u32 ctrl, ctrl_ext, tssdp = 0;
|
||||
|
||||
ctrl = rd32(IGC_CTRL);
|
||||
ctrl_ext = rd32(IGC_CTRL_EXT);
|
||||
tssdp = rd32(IGC_TSSDP);
|
||||
|
||||
igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
|
||||
|
||||
/* Make sure this pin is not enabled as an output. */
|
||||
tssdp &= ~igc_ts_sdp_en[pin];
|
||||
|
||||
if (chan == 1) {
|
||||
tssdp &= ~IGC_AUX1_SEL_SDP3;
|
||||
tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
|
||||
} else {
|
||||
tssdp &= ~IGC_AUX0_SEL_SDP3;
|
||||
tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
|
||||
}
|
||||
|
||||
wr32(IGC_TSSDP, tssdp);
|
||||
wr32(IGC_CTRL, ctrl);
|
||||
wr32(IGC_CTRL_EXT, ctrl_ext);
|
||||
}
|
||||
|
||||
static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
struct igc_adapter *igc =
|
||||
container_of(ptp, struct igc_adapter, ptp_caps);
|
||||
struct igc_hw *hw = &igc->hw;
|
||||
unsigned long flags;
|
||||
struct timespec64 ts;
|
||||
int use_freq = 0, pin = -1;
|
||||
u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
|
||||
s64 ns;
|
||||
|
||||
switch (rq->type) {
|
||||
case PTP_CLK_REQ_EXTTS:
|
||||
/* Reject requests with unsupported flags */
|
||||
if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
|
||||
PTP_RISING_EDGE |
|
||||
PTP_FALLING_EDGE |
|
||||
PTP_STRICT_FLAGS))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
/* Reject requests failing to enable both edges. */
|
||||
if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
|
||||
(rq->extts.flags & PTP_ENABLE_FEATURE) &&
|
||||
(rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (on) {
|
||||
pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
|
||||
rq->extts.index);
|
||||
if (pin < 0)
|
||||
return -EBUSY;
|
||||
}
|
||||
if (rq->extts.index == 1) {
|
||||
tsauxc_mask = IGC_TSAUXC_EN_TS1;
|
||||
tsim_mask = IGC_TSICR_AUTT1;
|
||||
} else {
|
||||
tsauxc_mask = IGC_TSAUXC_EN_TS0;
|
||||
tsim_mask = IGC_TSICR_AUTT0;
|
||||
}
|
||||
spin_lock_irqsave(&igc->tmreg_lock, flags);
|
||||
tsauxc = rd32(IGC_TSAUXC);
|
||||
tsim = rd32(IGC_TSIM);
|
||||
if (on) {
|
||||
igc_pin_extts(igc, rq->extts.index, pin);
|
||||
tsauxc |= tsauxc_mask;
|
||||
tsim |= tsim_mask;
|
||||
} else {
|
||||
tsauxc &= ~tsauxc_mask;
|
||||
tsim &= ~tsim_mask;
|
||||
}
|
||||
wr32(IGC_TSAUXC, tsauxc);
|
||||
wr32(IGC_TSIM, tsim);
|
||||
spin_unlock_irqrestore(&igc->tmreg_lock, flags);
|
||||
return 0;
|
||||
|
||||
case PTP_CLK_REQ_PEROUT:
|
||||
/* Reject requests with unsupported flags */
|
||||
if (rq->perout.flags)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (on) {
|
||||
pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
|
||||
rq->perout.index);
|
||||
if (pin < 0)
|
||||
return -EBUSY;
|
||||
}
|
||||
ts.tv_sec = rq->perout.period.sec;
|
||||
ts.tv_nsec = rq->perout.period.nsec;
|
||||
ns = timespec64_to_ns(&ts);
|
||||
ns = ns >> 1;
|
||||
if (on && (ns <= 70000000LL || ns == 125000000LL ||
|
||||
ns == 250000000LL || ns == 500000000LL)) {
|
||||
if (ns < 8LL)
|
||||
return -EINVAL;
|
||||
use_freq = 1;
|
||||
}
|
||||
ts = ns_to_timespec64(ns);
|
||||
if (rq->perout.index == 1) {
|
||||
if (use_freq) {
|
||||
tsauxc_mask = IGC_TSAUXC_EN_CLK1;
|
||||
tsim_mask = 0;
|
||||
} else {
|
||||
tsauxc_mask = IGC_TSAUXC_EN_TT1;
|
||||
tsim_mask = IGC_TSICR_TT1;
|
||||
}
|
||||
trgttiml = IGC_TRGTTIML1;
|
||||
trgttimh = IGC_TRGTTIMH1;
|
||||
freqout = IGC_FREQOUT1;
|
||||
} else {
|
||||
if (use_freq) {
|
||||
tsauxc_mask = IGC_TSAUXC_EN_CLK0;
|
||||
tsim_mask = 0;
|
||||
} else {
|
||||
tsauxc_mask = IGC_TSAUXC_EN_TT0;
|
||||
tsim_mask = IGC_TSICR_TT0;
|
||||
}
|
||||
trgttiml = IGC_TRGTTIML0;
|
||||
trgttimh = IGC_TRGTTIMH0;
|
||||
freqout = IGC_FREQOUT0;
|
||||
}
|
||||
spin_lock_irqsave(&igc->tmreg_lock, flags);
|
||||
tsauxc = rd32(IGC_TSAUXC);
|
||||
tsim = rd32(IGC_TSIM);
|
||||
if (rq->perout.index == 1) {
|
||||
tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1);
|
||||
tsim &= ~IGC_TSICR_TT1;
|
||||
} else {
|
||||
tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0);
|
||||
tsim &= ~IGC_TSICR_TT0;
|
||||
}
|
||||
if (on) {
|
||||
int i = rq->perout.index;
|
||||
|
||||
igc_pin_perout(igc, i, pin, use_freq);
|
||||
igc->perout[i].start.tv_sec = rq->perout.start.sec;
|
||||
igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
|
||||
igc->perout[i].period.tv_sec = ts.tv_sec;
|
||||
igc->perout[i].period.tv_nsec = ts.tv_nsec;
|
||||
wr32(trgttimh, rq->perout.start.sec);
|
||||
/* For now, always select timer 0 as source. */
|
||||
wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
|
||||
if (use_freq)
|
||||
wr32(freqout, ns);
|
||||
tsauxc |= tsauxc_mask;
|
||||
tsim |= tsim_mask;
|
||||
}
|
||||
wr32(IGC_TSAUXC, tsauxc);
|
||||
wr32(IGC_TSIM, tsim);
|
||||
spin_unlock_irqrestore(&igc->tmreg_lock, flags);
|
||||
return 0;
|
||||
|
||||
case PTP_CLK_REQ_PPS:
|
||||
spin_lock_irqsave(&igc->tmreg_lock, flags);
|
||||
tsim = rd32(IGC_TSIM);
|
||||
if (on)
|
||||
tsim |= IGC_TSICR_SYS_WRAP;
|
||||
else
|
||||
tsim &= ~IGC_TSICR_SYS_WRAP;
|
||||
igc->pps_sys_wrap_on = on;
|
||||
wr32(IGC_TSIM, tsim);
|
||||
spin_unlock_irqrestore(&igc->tmreg_lock, flags);
|
||||
return 0;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
|
||||
enum ptp_pin_function func, unsigned int chan)
|
||||
{
|
||||
switch (func) {
|
||||
case PTP_PF_NONE:
|
||||
case PTP_PF_EXTTS:
|
||||
case PTP_PF_PEROUT:
|
||||
break;
|
||||
case PTP_PF_PHYSYNC:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
|
||||
* @adapter: board private structure
|
||||
|
|
@ -486,9 +763,17 @@ void igc_ptp_init(struct igc_adapter *adapter)
|
|||
{
|
||||
struct net_device *netdev = adapter->netdev;
|
||||
struct igc_hw *hw = &adapter->hw;
|
||||
int i;
|
||||
|
||||
switch (hw->mac.type) {
|
||||
case igc_i225:
|
||||
for (i = 0; i < IGC_N_SDP; i++) {
|
||||
struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
|
||||
|
||||
snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
|
||||
ppd->index = i;
|
||||
ppd->func = PTP_PF_NONE;
|
||||
}
|
||||
snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
|
||||
adapter->ptp_caps.owner = THIS_MODULE;
|
||||
adapter->ptp_caps.max_adj = 62499999;
|
||||
|
|
@ -497,6 +782,12 @@ void igc_ptp_init(struct igc_adapter *adapter)
|
|||
adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
|
||||
adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
|
||||
adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
|
||||
adapter->ptp_caps.pps = 1;
|
||||
adapter->ptp_caps.pin_config = adapter->sdp_config;
|
||||
adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
|
||||
adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
|
||||
adapter->ptp_caps.n_pins = IGC_N_SDP;
|
||||
adapter->ptp_caps.verify = igc_ptp_verify_pin;
|
||||
break;
|
||||
default:
|
||||
adapter->ptp_clock = NULL;
|
||||
|
|
@ -598,7 +889,9 @@ void igc_ptp_reset(struct igc_adapter *adapter)
|
|||
case igc_i225:
|
||||
wr32(IGC_TSAUXC, 0x0);
|
||||
wr32(IGC_TSSDP, 0x0);
|
||||
wr32(IGC_TSIM, IGC_TSICR_INTERRUPTS);
|
||||
wr32(IGC_TSIM,
|
||||
IGC_TSICR_INTERRUPTS |
|
||||
(adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
|
||||
wr32(IGC_IMS, IGC_IMS_TS);
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -192,6 +192,16 @@
|
|||
#define IGC_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
|
||||
#define IGC_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
|
||||
#define IGC_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */
|
||||
#define IGC_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
|
||||
#define IGC_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
|
||||
#define IGC_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
|
||||
#define IGC_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
|
||||
#define IGC_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
|
||||
#define IGC_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
|
||||
#define IGC_AUXSTMPL0 0x0B65C /* Auxiliary Time Stamp 0 Register Low - RO */
|
||||
#define IGC_AUXSTMPH0 0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */
|
||||
#define IGC_AUXSTMPL1 0x0B664 /* Auxiliary Time Stamp 1 Register Low - RO */
|
||||
#define IGC_AUXSTMPH1 0x0B668 /* Auxiliary Time Stamp 1 Register High - RO */
|
||||
|
||||
#define IGC_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
|
||||
#define IGC_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user