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drm/i915: s/intel_infoframe/gm45_infoframe

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These two functions are actually hw-specific and only valid for gm45
thru gen7. HSW completely changes how this works, so label them
accordingly.

v2: s/gm45/g4x/ like for the previous patch.

Acked-by: Paulo Zanoni <przanoni@gmail.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2012-05-08 15:18:32 +02:00
parent a3da1df7bd
commit bc2481f313
1 changed files with 14 additions and 14 deletions
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28
drivers/gpu/drm/i915/intel_hdmi.c
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@ -75,7 +75,7 @@ void intel_dip_infoframe_csum(struct dip_infoframe *frame)
frame->checksum = 0x100 - sum; frame->checksum = 0x100 - sum;
} }
static u32 intel_infoframe_index(struct dip_infoframe *frame) static u32 g4x_infoframe_index(struct dip_infoframe *frame)
{ {
u32 flags = 0; u32 flags = 0;
@ -94,7 +94,7 @@ static u32 intel_infoframe_index(struct dip_infoframe *frame)
return flags; return flags;
} }
static u32 intel_infoframe_enable(struct dip_infoframe *frame) static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
{ {
u32 flags = 0; u32 flags = 0;
@ -134,9 +134,9 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
return; return;
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
val |= intel_infoframe_index(frame); val |= g4x_infoframe_index(frame);
val &= ~intel_infoframe_enable(frame); val &= ~g4x_infoframe_enable(frame);
val |= VIDEO_DIP_ENABLE; val |= VIDEO_DIP_ENABLE;
I915_WRITE(VIDEO_DIP_CTL, val); I915_WRITE(VIDEO_DIP_CTL, val);
@ -146,7 +146,7 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
data++; data++;
} }
val |= intel_infoframe_enable(frame); val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK; val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC; val |= VIDEO_DIP_FREQ_VSYNC;
@ -184,9 +184,9 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
intel_wait_for_vblank(dev, intel_crtc->pipe); intel_wait_for_vblank(dev, intel_crtc->pipe);
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
val |= intel_infoframe_index(frame); val |= g4x_infoframe_index(frame);
val &= ~intel_infoframe_enable(frame); val &= ~g4x_infoframe_enable(frame);
val |= VIDEO_DIP_ENABLE; val |= VIDEO_DIP_ENABLE;
I915_WRITE(reg, val); I915_WRITE(reg, val);
@ -196,7 +196,7 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
data++; data++;
} }
val |= intel_infoframe_enable(frame); val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK; val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC; val |= VIDEO_DIP_FREQ_VSYNC;
@ -218,14 +218,14 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
intel_wait_for_vblank(dev, intel_crtc->pipe); intel_wait_for_vblank(dev, intel_crtc->pipe);
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
val |= intel_infoframe_index(frame); val |= g4x_infoframe_index(frame);
/* The DIP control register spec says that we need to update the AVI /* The DIP control register spec says that we need to update the AVI
* infoframe without clearing its enable bit */ * infoframe without clearing its enable bit */
if (frame->type == DIP_TYPE_AVI) if (frame->type == DIP_TYPE_AVI)
val |= VIDEO_DIP_ENABLE_AVI; val |= VIDEO_DIP_ENABLE_AVI;
else else
val &= ~intel_infoframe_enable(frame); val &= ~g4x_infoframe_enable(frame);
val |= VIDEO_DIP_ENABLE; val |= VIDEO_DIP_ENABLE;
@ -236,7 +236,7 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
data++; data++;
} }
val |= intel_infoframe_enable(frame); val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK; val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC; val |= VIDEO_DIP_FREQ_VSYNC;
@ -258,9 +258,9 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
intel_wait_for_vblank(dev, intel_crtc->pipe); intel_wait_for_vblank(dev, intel_crtc->pipe);
val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
val |= intel_infoframe_index(frame); val |= g4x_infoframe_index(frame);
val &= ~intel_infoframe_enable(frame); val &= ~g4x_infoframe_enable(frame);
val |= VIDEO_DIP_ENABLE; val |= VIDEO_DIP_ENABLE;
I915_WRITE(reg, val); I915_WRITE(reg, val);
@ -270,7 +270,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
data++; data++;
} }
val |= intel_infoframe_enable(frame); val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK; val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC; val |= VIDEO_DIP_FREQ_VSYNC;