forked from Minki/linux
Merge branches 'clk-imx', 'clk-samsung', 'clk-zynq', 'clk-rockchip' and 'clk-uniphier' into clk-next
- Simplify Zynq Kconfig dependencies * clk-imx: clk: imx: Reference preceded by free clk: imx8mq: Correct the pcie1 sels clk: imx8mp: Remove the none exist pcie clocks clk: imx: Fix reparenting of UARTs not associated with stdout * clk-samsung: clk: samsung: Remove redundant dev_err calls clk: exynos7: Mark aclk_fsys1_200 as critical * clk-zynq: clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback clk: zynqmp: Drop dependency on ARCH_ZYNQMP clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected * clk-rockchip: clk: rockchip: drop MODULE_ALIAS from rk3399 clock controller clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends clk: rockchip: add clock controller for rk3568 clk: rockchip: support more core div setting dt-binding: clock: Document rockchip, rk3568-cru bindings clk: rockchip: add dt-binding header for rk3568 * clk-uniphier: clk: uniphier: Fix potential infinite loop
This commit is contained in:
Stephen Boyd
commit
bbc3b403b0
@ -0,0 +1,60 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ROCKCHIP rk3568 Family Clock Control Module Binding
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maintainers:
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- Elaine Zhang <zhangqing@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |
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The RK3568 clock controller generates the clock and also implements a
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reset controller for SoC peripherals.
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(examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
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used in device tree sources.
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properties:
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compatible:
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enum:
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- rockchip,rk3568-cru
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- rockchip,rk3568-pmucru
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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# Clock Control Module node:
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- |
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pmucru: clock-controller@fdd00000 {
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compatible = "rockchip,rk3568-pmucru";
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reg = <0xfdd00000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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- |
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cru: clock-controller@fdd20000 {
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compatible = "rockchip,rk3568-cru";
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reg = <0xfdd20000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -73,16 +73,6 @@ enum mx25_clks {
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static struct clk *clk[clk_max];
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static struct clk ** const uart_clks[] __initconst = {
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&clk[uart_ipg_per],
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&clk[uart1_ipg],
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&clk[uart2_ipg],
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&clk[uart3_ipg],
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&clk[uart4_ipg],
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&clk[uart5_ipg],
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NULL
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};
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static int __init __mx25_clocks_init(void __iomem *ccm_base)
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{
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BUG_ON(!ccm_base);
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@ -228,7 +218,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
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*/
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clk_set_parent(clk[cko_sel], clk[ipg]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(6);
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return 0;
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}
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@ -49,17 +49,6 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
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static struct clk *clk[IMX27_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks[] __initconst = {
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&clk[IMX27_CLK_PER1_GATE],
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&clk[IMX27_CLK_UART1_IPG_GATE],
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&clk[IMX27_CLK_UART2_IPG_GATE],
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&clk[IMX27_CLK_UART3_IPG_GATE],
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&clk[IMX27_CLK_UART4_IPG_GATE],
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&clk[IMX27_CLK_UART5_IPG_GATE],
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&clk[IMX27_CLK_UART6_IPG_GATE],
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NULL
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};
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static void __init _mx27_clocks_init(unsigned long fref)
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{
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BUG_ON(!ccm);
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@ -176,7 +165,7 @@ static void __init _mx27_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(7);
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imx_print_silicon_rev("i.MX27", mx27_revision());
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}
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@ -82,14 +82,6 @@ enum mx35_clks {
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static struct clk *clk[clk_max];
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static struct clk ** const uart_clks[] __initconst = {
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&clk[ipg],
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&clk[uart1_gate],
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&clk[uart2_gate],
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&clk[uart3_gate],
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NULL
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};
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static void __init _mx35_clocks_init(void)
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{
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void __iomem *base;
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@ -243,7 +235,7 @@ static void __init _mx35_clocks_init(void)
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*/
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clk_prepare_enable(clk[scc_gate]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(4);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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}
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@ -128,30 +128,6 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_
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static struct clk *clk[IMX5_CLK_END];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks_mx51[] __initconst = {
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&clk[IMX5_CLK_UART1_IPG_GATE],
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&clk[IMX5_CLK_UART1_PER_GATE],
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&clk[IMX5_CLK_UART2_IPG_GATE],
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&clk[IMX5_CLK_UART2_PER_GATE],
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&clk[IMX5_CLK_UART3_IPG_GATE],
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&clk[IMX5_CLK_UART3_PER_GATE],
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NULL
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};
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static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
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&clk[IMX5_CLK_UART1_IPG_GATE],
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&clk[IMX5_CLK_UART1_PER_GATE],
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&clk[IMX5_CLK_UART2_IPG_GATE],
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&clk[IMX5_CLK_UART2_PER_GATE],
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&clk[IMX5_CLK_UART3_IPG_GATE],
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&clk[IMX5_CLK_UART3_PER_GATE],
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&clk[IMX5_CLK_UART4_IPG_GATE],
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&clk[IMX5_CLK_UART4_PER_GATE],
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&clk[IMX5_CLK_UART5_IPG_GATE],
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&clk[IMX5_CLK_UART5_PER_GATE],
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NULL
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};
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static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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{
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clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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@ -382,7 +358,7 @@ static void __init mx50_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(uart_clks_mx50_mx53);
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imx_register_uart_clocks(5);
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}
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CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
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@ -488,7 +464,7 @@ static void __init mx51_clocks_init(struct device_node *np)
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val |= 1 << 23;
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writel(val, MXC_CCM_CLPCR);
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imx_register_uart_clocks(uart_clks_mx51);
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imx_register_uart_clocks(3);
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}
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CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
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@ -633,6 +609,6 @@ static void __init mx53_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(uart_clks_mx50_mx53);
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imx_register_uart_clocks(5);
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}
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CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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@ -140,13 +140,6 @@ static inline int clk_on_imx6dl(void)
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return of_machine_is_compatible("fsl,imx6dl");
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}
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static const int uart_clk_ids[] __initconst = {
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IMX6QDL_CLK_UART_IPG,
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IMX6QDL_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static int ldb_di_sel_by_clock_id(int clock_id)
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{
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switch (clock_id) {
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@ -440,7 +433,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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struct device_node *np;
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void __iomem *anatop_base, *base;
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int ret;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6QDL_CLK_END), GFP_KERNEL);
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@ -982,12 +974,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
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}
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(1);
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}
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CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
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@ -179,19 +179,11 @@ void imx6sl_set_wait_clk(bool enter)
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imx6sl_enable_pll_arm(false);
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}
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static const int uart_clk_ids[] __initconst = {
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IMX6SL_CLK_UART,
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IMX6SL_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int ret;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SL_CLK_END), GFP_KERNEL);
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@ -448,12 +440,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
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hws[IMX6SL_CLK_PLL2_PFD2]->clk);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(2);
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}
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CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
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@ -76,26 +76,10 @@ static u32 share_count_ssi1;
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static u32 share_count_ssi2;
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static u32 share_count_ssi3;
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static const int uart_clk_ids[] __initconst = {
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IMX6SLL_CLK_UART1_IPG,
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IMX6SLL_CLK_UART1_SERIAL,
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IMX6SLL_CLK_UART2_IPG,
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IMX6SLL_CLK_UART2_SERIAL,
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IMX6SLL_CLK_UART3_IPG,
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IMX6SLL_CLK_UART3_SERIAL,
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IMX6SLL_CLK_UART4_IPG,
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IMX6SLL_CLK_UART4_SERIAL,
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IMX6SLL_CLK_UART5_IPG,
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IMX6SLL_CLK_UART5_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SLL_CLK_END), GFP_KERNEL);
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@ -356,13 +340,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(5);
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/* Lower the AHB clock rate before changing the clock source. */
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clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);
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@ -117,18 +117,10 @@ static u32 share_count_ssi3;
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static u32 share_count_sai1;
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static u32 share_count_sai2;
|
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|
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static const int uart_clk_ids[] __initconst = {
|
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IMX6SX_CLK_UART_IPG,
|
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IMX6SX_CLK_UART_SERIAL,
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};
|
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
|
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static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
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{
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struct device_node *np;
|
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void __iomem *base;
|
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int i;
|
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|
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
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IMX6SX_CLK_CLK_END), GFP_KERNEL);
|
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@ -556,12 +548,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
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clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
|
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clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
|
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|
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
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int index = uart_clk_ids[i];
|
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|
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uart_clks[i] = &hws[index]->clk;
|
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}
|
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|
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imx_register_uart_clocks(uart_clks);
|
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imx_register_uart_clocks(2);
|
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}
|
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CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
|
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|
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@ -377,23 +377,10 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
|
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static struct clk_hw **hws;
|
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static struct clk_hw_onecell_data *clk_hw_data;
|
||||
|
||||
static const int uart_clk_ids[] __initconst = {
|
||||
IMX7D_UART1_ROOT_CLK,
|
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IMX7D_UART2_ROOT_CLK,
|
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IMX7D_UART3_ROOT_CLK,
|
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IMX7D_UART4_ROOT_CLK,
|
||||
IMX7D_UART5_ROOT_CLK,
|
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IMX7D_UART6_ROOT_CLK,
|
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IMX7D_UART7_ROOT_CLK,
|
||||
};
|
||||
|
||||
static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
|
||||
|
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static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX7D_CLK_END), GFP_KERNEL);
|
||||
@ -897,14 +884,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
|
||||
hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
imx_register_uart_clocks(7);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
|
||||
|
||||
@ -43,19 +43,6 @@ static const struct clk_div_table ulp_div_table[] = {
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const int pcc2_uart_clk_ids[] __initconst = {
|
||||
IMX7ULP_CLK_LPUART4,
|
||||
IMX7ULP_CLK_LPUART5,
|
||||
};
|
||||
|
||||
static const int pcc3_uart_clk_ids[] __initconst = {
|
||||
IMX7ULP_CLK_LPUART6,
|
||||
IMX7ULP_CLK_LPUART7,
|
||||
};
|
||||
|
||||
static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
|
||||
static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
|
||||
|
||||
static void __init imx7ulp_clk_scg1_init(struct device_node *np)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
@ -150,7 +137,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **hws;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
|
||||
GFP_KERNEL);
|
||||
@ -190,13 +176,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
|
||||
int index = pcc2_uart_clk_ids[i];
|
||||
|
||||
pcc2_uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(pcc2_uart_clks);
|
||||
imx_register_uart_clocks(2);
|
||||
}
|
||||
CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
|
||||
|
||||
@ -205,7 +185,6 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **hws;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
|
||||
GFP_KERNEL);
|
||||
@ -244,13 +223,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
|
||||
int index = pcc3_uart_clk_ids[i];
|
||||
|
||||
pcc3_uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(pcc3_uart_clks);
|
||||
imx_register_uart_clocks(7);
|
||||
}
|
||||
CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
|
||||
|
||||
|
||||
@ -296,20 +296,12 @@ static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MM_CLK_UART1_ROOT,
|
||||
IMX8MM_CLK_UART2_ROOT,
|
||||
IMX8MM_CLK_UART3_ROOT,
|
||||
IMX8MM_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mm_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MM_CLK_END), GFP_KERNEL);
|
||||
@ -634,13 +626,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@ -289,20 +289,12 @@ static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MN_CLK_UART1_ROOT,
|
||||
IMX8MN_CLK_UART2_ROOT,
|
||||
IMX8MN_CLK_UART3_ROOT,
|
||||
IMX8MN_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mn_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MN_CLK_END), GFP_KERNEL);
|
||||
@ -585,13 +577,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "sys_pll1_400m", };
|
||||
|
||||
static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
|
||||
"sys_pll1_160m", "sys_pll1_200m", };
|
||||
@ -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m",
|
||||
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
|
||||
"sys_pll2_333m", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "sys_pll1_400m", };
|
||||
|
||||
static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "sys_pll2_100m",
|
||||
"sys_pll1_80m", "sys_pll1_160m",
|
||||
@ -414,20 +402,11 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r
|
||||
static struct clk_hw **hws;
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MP_CLK_UART1_ROOT,
|
||||
IMX8MP_CLK_UART2_ROOT,
|
||||
IMX8MP_CLK_UART3_ROOT,
|
||||
IMX8MP_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np;
|
||||
void __iomem *anatop_base, *ccm_base;
|
||||
int i;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
|
||||
anatop_base = of_iomap(np, 0);
|
||||
@ -585,7 +564,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
|
||||
hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
|
||||
hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280);
|
||||
hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380);
|
||||
hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400);
|
||||
hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480);
|
||||
hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500);
|
||||
@ -643,8 +621,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
|
||||
hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
|
||||
hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80);
|
||||
hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
|
||||
hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
|
||||
hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
|
||||
hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180);
|
||||
hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ccm_base + 0xc200);
|
||||
@ -737,13 +713,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -113,12 +113,12 @@ static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "
|
||||
static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", };
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
|
||||
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
|
||||
|
||||
static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
|
||||
@ -281,20 +281,12 @@ static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy"
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MQ_CLK_UART1_ROOT,
|
||||
IMX8MQ_CLK_UART2_ROOT,
|
||||
IMX8MQ_CLK_UART3_ROOT,
|
||||
IMX8MQ_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int err, i;
|
||||
int err;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MQ_CLK_END), GFP_KERNEL);
|
||||
@ -629,13 +621,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@ -114,6 +114,7 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
|
||||
if (ret) {
|
||||
kfree(clk);
|
||||
hw = ERR_PTR(ret);
|
||||
return hw;
|
||||
}
|
||||
|
||||
if (dev)
|
||||
|
||||
@ -426,6 +426,7 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
|
||||
if (ret) {
|
||||
kfree(clk);
|
||||
hw = ERR_PTR(ret);
|
||||
return hw;
|
||||
}
|
||||
|
||||
if (dev)
|
||||
|
||||
@ -147,8 +147,10 @@ void imx_cscmr1_fixup(u32 *val)
|
||||
}
|
||||
|
||||
#ifndef MODULE
|
||||
static int imx_keep_uart_clocks;
|
||||
static struct clk ** const *imx_uart_clocks;
|
||||
|
||||
static bool imx_keep_uart_clocks;
|
||||
static int imx_enabled_uart_clocks;
|
||||
static struct clk **imx_uart_clocks;
|
||||
|
||||
static int __init imx_keep_uart_clocks_param(char *str)
|
||||
{
|
||||
@ -161,24 +163,45 @@ __setup_param("earlycon", imx_keep_uart_earlycon,
|
||||
__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
|
||||
imx_keep_uart_clocks_param, 0);
|
||||
|
||||
void imx_register_uart_clocks(struct clk ** const clks[])
|
||||
void imx_register_uart_clocks(unsigned int clk_count)
|
||||
{
|
||||
imx_enabled_uart_clocks = 0;
|
||||
|
||||
/* i.MX boards use device trees now. For build tests without CONFIG_OF, do nothing */
|
||||
#ifdef CONFIG_OF
|
||||
if (imx_keep_uart_clocks) {
|
||||
int i;
|
||||
|
||||
imx_uart_clocks = clks;
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_prepare_enable(*imx_uart_clocks[i]);
|
||||
imx_uart_clocks = kcalloc(clk_count, sizeof(struct clk *), GFP_KERNEL);
|
||||
|
||||
if (!of_stdout)
|
||||
return;
|
||||
|
||||
for (i = 0; i < clk_count; i++) {
|
||||
imx_uart_clocks[imx_enabled_uart_clocks] = of_clk_get(of_stdout, i);
|
||||
|
||||
/* Stop if there are no more of_stdout references */
|
||||
if (IS_ERR(imx_uart_clocks[imx_enabled_uart_clocks]))
|
||||
return;
|
||||
|
||||
/* Only enable the clock if it's not NULL */
|
||||
if (imx_uart_clocks[imx_enabled_uart_clocks])
|
||||
clk_prepare_enable(imx_uart_clocks[imx_enabled_uart_clocks++]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static int __init imx_clk_disable_uart(void)
|
||||
{
|
||||
if (imx_keep_uart_clocks && imx_uart_clocks) {
|
||||
if (imx_keep_uart_clocks && imx_enabled_uart_clocks) {
|
||||
int i;
|
||||
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_disable_unprepare(*imx_uart_clocks[i]);
|
||||
for (i = 0; i < imx_enabled_uart_clocks; i++) {
|
||||
clk_disable_unprepare(imx_uart_clocks[i]);
|
||||
clk_put(imx_uart_clocks[i]);
|
||||
}
|
||||
kfree(imx_uart_clocks);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -11,9 +11,9 @@ extern spinlock_t imx_ccm_lock;
|
||||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
||||
#ifndef MODULE
|
||||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
void imx_register_uart_clocks(unsigned int clk_count);
|
||||
#else
|
||||
static inline void imx_register_uart_clocks(struct clk ** const clks[])
|
||||
static inline void imx_register_uart_clocks(unsigned int clk_count)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -11,78 +11,85 @@ config COMMON_CLK_ROCKCHIP
|
||||
if COMMON_CLK_ROCKCHIP
|
||||
config CLK_PX30
|
||||
bool "Rockchip PX30 clock controller support"
|
||||
depends on (ARM64 || COMPILE_TEST)
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for PX30 Clock Driver.
|
||||
|
||||
config CLK_RV110X
|
||||
bool "Rockchip RV110x clock controller support"
|
||||
depends on (ARM || COMPILE_TEST)
|
||||
depends on ARM || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RV110x Clock Driver.
|
||||
|
||||
config CLK_RK3036
|
||||
bool "Rockchip RK3036 clock controller support"
|
||||
depends on (ARM || COMPILE_TEST)
|
||||
depends on ARM || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3036 Clock Driver.
|
||||
|
||||
config CLK_RK312X
|
||||
bool "Rockchip RK312x clock controller support"
|
||||
depends on (ARM || COMPILE_TEST)
|
||||
depends on ARM || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK312x Clock Driver.
|
||||
|
||||
config CLK_RK3188
|
||||
bool "Rockchip RK3188 clock controller support"
|
||||
depends on (ARM || COMPILE_TEST)
|
||||
depends on ARM || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3188 Clock Driver.
|
||||
|
||||
config CLK_RK322X
|
||||
bool "Rockchip RK322x clock controller support"
|
||||
depends on (ARM || COMPILE_TEST)
|
||||
depends on ARM || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK322x Clock Driver.
|
||||
|
||||
config CLK_RK3288
|
||||
bool "Rockchip RK3288 clock controller support"
|
||||
depends on (ARM || COMPILE_TEST)
|
||||
depends on ARM || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3288 Clock Driver.
|
||||
|
||||
config CLK_RK3308
|
||||
bool "Rockchip RK3308 clock controller support"
|
||||
depends on (ARM64 || COMPILE_TEST)
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3308 Clock Driver.
|
||||
|
||||
config CLK_RK3328
|
||||
bool "Rockchip RK3328 clock controller support"
|
||||
depends on (ARM64 || COMPILE_TEST)
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3328 Clock Driver.
|
||||
|
||||
config CLK_RK3368
|
||||
bool "Rockchip RK3368 clock controller support"
|
||||
depends on (ARM64 || COMPILE_TEST)
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3368 Clock Driver.
|
||||
|
||||
config CLK_RK3399
|
||||
tristate "Rockchip RK3399 clock controller support"
|
||||
depends on (ARM64 || COMPILE_TEST)
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3399 Clock Driver.
|
||||
|
||||
config CLK_RK3568
|
||||
tristate "Rockchip RK3568 clock controller support"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default y
|
||||
help
|
||||
Build the driver for RK3568 Clock Driver.
|
||||
endif
|
||||
|
||||
@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
|
||||
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
|
||||
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
|
||||
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
|
||||
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
|
||||
|
||||
@ -84,10 +84,10 @@ static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,
|
||||
{
|
||||
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
|
||||
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
|
||||
u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
|
||||
u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
|
||||
clksel0 >>= reg_data->div_core_shift;
|
||||
clksel0 &= reg_data->div_core_mask;
|
||||
clksel0 >>= reg_data->div_core_shift[0];
|
||||
clksel0 &= reg_data->div_core_mask[0];
|
||||
return parent_rate / (clksel0 + 1);
|
||||
}
|
||||
|
||||
@ -120,6 +120,7 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
|
||||
const struct rockchip_cpuclk_rate_table *rate;
|
||||
unsigned long alt_prate, alt_div;
|
||||
unsigned long flags;
|
||||
int i = 0;
|
||||
|
||||
/* check validity of the new rate */
|
||||
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
|
||||
@ -142,10 +143,10 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
|
||||
if (alt_prate > ndata->old_rate) {
|
||||
/* calculate dividers */
|
||||
alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
|
||||
if (alt_div > reg_data->div_core_mask) {
|
||||
if (alt_div > reg_data->div_core_mask[0]) {
|
||||
pr_warn("%s: limiting alt-divider %lu to %d\n",
|
||||
__func__, alt_div, reg_data->div_core_mask);
|
||||
alt_div = reg_data->div_core_mask;
|
||||
__func__, alt_div, reg_data->div_core_mask[0]);
|
||||
alt_div = reg_data->div_core_mask[0];
|
||||
}
|
||||
|
||||
/*
|
||||
@ -158,19 +159,17 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
|
||||
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
|
||||
__func__, alt_div, alt_prate, ndata->old_rate);
|
||||
|
||||
writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
|
||||
reg_data->div_core_shift) |
|
||||
HIWORD_UPDATE(reg_data->mux_core_alt,
|
||||
reg_data->mux_core_mask,
|
||||
reg_data->mux_core_shift),
|
||||
cpuclk->reg_base + reg_data->core_reg);
|
||||
} else {
|
||||
/* select alternate parent */
|
||||
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
|
||||
reg_data->mux_core_mask,
|
||||
reg_data->mux_core_shift),
|
||||
cpuclk->reg_base + reg_data->core_reg);
|
||||
for (i = 0; i < reg_data->num_cores; i++) {
|
||||
writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
|
||||
reg_data->div_core_shift[i]),
|
||||
cpuclk->reg_base + reg_data->core_reg[i]);
|
||||
}
|
||||
}
|
||||
/* select alternate parent */
|
||||
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
|
||||
reg_data->mux_core_mask,
|
||||
reg_data->mux_core_shift),
|
||||
cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
|
||||
spin_unlock_irqrestore(cpuclk->lock, flags);
|
||||
return 0;
|
||||
@ -182,6 +181,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
|
||||
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
|
||||
const struct rockchip_cpuclk_rate_table *rate;
|
||||
unsigned long flags;
|
||||
int i = 0;
|
||||
|
||||
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
|
||||
if (!rate) {
|
||||
@ -202,12 +202,17 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
|
||||
* primary parent by the extra dividers that were needed for the alt.
|
||||
*/
|
||||
|
||||
writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
|
||||
reg_data->div_core_shift) |
|
||||
HIWORD_UPDATE(reg_data->mux_core_main,
|
||||
reg_data->mux_core_mask,
|
||||
reg_data->mux_core_shift),
|
||||
cpuclk->reg_base + reg_data->core_reg);
|
||||
writel(HIWORD_UPDATE(reg_data->mux_core_main,
|
||||
reg_data->mux_core_mask,
|
||||
reg_data->mux_core_shift),
|
||||
cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
|
||||
/* remove dividers */
|
||||
for (i = 0; i < reg_data->num_cores; i++) {
|
||||
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
|
||||
reg_data->div_core_shift[i]),
|
||||
cpuclk->reg_base + reg_data->core_reg[i]);
|
||||
}
|
||||
|
||||
if (ndata->old_rate > ndata->new_rate)
|
||||
rockchip_cpuclk_set_dividers(cpuclk, rate);
|
||||
|
||||
@ -124,9 +124,10 @@ static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
|
||||
.core_reg = PX30_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0xf,
|
||||
.core_reg[0] = PX30_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0xf,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 7,
|
||||
|
||||
@ -102,9 +102,10 @@ static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
|
||||
.core_reg = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 7,
|
||||
|
||||
@ -117,9 +117,10 @@ static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {
|
||||
.core_reg = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 7,
|
||||
|
||||
@ -145,9 +145,10 @@ static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
|
||||
.core_reg = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 8,
|
||||
@ -184,9 +185,10 @@ static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
|
||||
.core_reg = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift = 9,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 9,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 8,
|
||||
|
||||
@ -119,9 +119,10 @@ static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
|
||||
.core_reg = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK2928_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 6,
|
||||
|
||||
@ -179,9 +179,10 @@ static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
|
||||
.core_reg = RK3288_CLKSEL_CON(0),
|
||||
.div_core_shift = 8,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK3288_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 8,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 15,
|
||||
|
||||
@ -109,9 +109,10 @@ static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
|
||||
.core_reg = RK3308_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0xf,
|
||||
.core_reg[0] = RK3308_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0xf,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 6,
|
||||
|
||||
@ -130,9 +130,10 @@ static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
|
||||
.core_reg = RK3328_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK3328_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 3,
|
||||
.mux_core_shift = 6,
|
||||
|
||||
@ -154,9 +154,10 @@ static struct clk_div_table div_ddrphy_t[] = {
|
||||
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
|
||||
.core_reg = RK3368_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK3368_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 7,
|
||||
@ -164,11 +165,12 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
|
||||
.core_reg = RK3368_CLKSEL_CON(2),
|
||||
.div_core_shift = 0,
|
||||
.core_reg[0] = RK3368_CLKSEL_CON(2),
|
||||
.div_core_shift[0] = 0,
|
||||
.mux_core_alt = 1,
|
||||
.num_cores = 1,
|
||||
.mux_core_main = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.mux_core_shift = 7,
|
||||
.mux_core_mask = 0x1,
|
||||
};
|
||||
|
||||
@ -291,9 +291,10 @@ static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
|
||||
RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
|
||||
.core_reg = RK3399_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK3399_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 3,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 6,
|
||||
@ -301,9 +302,10 @@ static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
|
||||
.core_reg = RK3399_CLKSEL_CON(2),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RK3399_CLKSEL_CON(2),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 3,
|
||||
.mux_core_main = 1,
|
||||
.mux_core_shift = 6,
|
||||
@ -1655,4 +1657,3 @@ builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
|
||||
|
||||
MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:clk-rk3399");
|
||||
|
||||
1725
drivers/clk/rockchip/clk-rk3568.c
Normal file
1725
drivers/clk/rockchip/clk-rk3568.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -106,9 +106,10 @@ static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
|
||||
};
|
||||
|
||||
static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
|
||||
.core_reg = RV1108_CLKSEL_CON(0),
|
||||
.div_core_shift = 0,
|
||||
.div_core_mask = 0x1f,
|
||||
.core_reg[0] = RV1108_CLKSEL_CON(0),
|
||||
.div_core_shift[0] = 0,
|
||||
.div_core_mask[0] = 0x1f,
|
||||
.num_cores = 1,
|
||||
.mux_core_alt = 1,
|
||||
.mux_core_main = 0,
|
||||
.mux_core_shift = 8,
|
||||
|
||||
@ -188,6 +188,34 @@ struct clk;
|
||||
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
|
||||
|
||||
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3568_MODE_CON0 0xc0
|
||||
#define RK3568_MISC_CON0 0xc4
|
||||
#define RK3568_MISC_CON1 0xc8
|
||||
#define RK3568_MISC_CON2 0xcc
|
||||
#define RK3568_GLB_CNT_TH 0xd0
|
||||
#define RK3568_GLB_SRST_FST 0xd4
|
||||
#define RK3568_GLB_SRST_SND 0xd8
|
||||
#define RK3568_GLB_RST_CON 0xdc
|
||||
#define RK3568_GLB_RST_ST 0xe0
|
||||
#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
|
||||
#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
|
||||
#define RK3568_SDMMC0_CON0 0x580
|
||||
#define RK3568_SDMMC0_CON1 0x584
|
||||
#define RK3568_SDMMC1_CON0 0x588
|
||||
#define RK3568_SDMMC1_CON1 0x58c
|
||||
#define RK3568_SDMMC2_CON0 0x590
|
||||
#define RK3568_SDMMC2_CON1 0x594
|
||||
#define RK3568_EMMC_CON0 0x598
|
||||
#define RK3568_EMMC_CON1 0x59c
|
||||
|
||||
#define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
|
||||
#define RK3568_PMU_MODE_CON0 0x80
|
||||
#define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
|
||||
#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
|
||||
#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
|
||||
|
||||
enum rockchip_pll_type {
|
||||
pll_rk3036,
|
||||
pll_rk3066,
|
||||
@ -322,7 +350,8 @@ struct rockchip_cpuclk_clksel {
|
||||
u32 val;
|
||||
};
|
||||
|
||||
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
|
||||
#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 5
|
||||
#define ROCKCHIP_CPUCLK_MAX_CORES 4
|
||||
struct rockchip_cpuclk_rate_table {
|
||||
unsigned long prate;
|
||||
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
|
||||
@ -330,22 +359,23 @@ struct rockchip_cpuclk_rate_table {
|
||||
|
||||
/**
|
||||
* struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
|
||||
* @core_reg: register offset of the core settings register
|
||||
* @div_core_shift: core divider offset used to divide the pll value
|
||||
* @div_core_mask: core divider mask
|
||||
* @mux_core_alt: mux value to select alternate parent
|
||||
* @core_reg[]: register offset of the cores setting register
|
||||
* @div_core_shift[]: cores divider offset used to divide the pll value
|
||||
* @div_core_mask[]: cores divider mask
|
||||
* @num_cores: number of cpu cores
|
||||
* @mux_core_main: mux value to select main parent of core
|
||||
* @mux_core_shift: offset of the core multiplexer
|
||||
* @mux_core_mask: core multiplexer mask
|
||||
*/
|
||||
struct rockchip_cpuclk_reg_data {
|
||||
int core_reg;
|
||||
u8 div_core_shift;
|
||||
u32 div_core_mask;
|
||||
u8 mux_core_alt;
|
||||
u8 mux_core_main;
|
||||
u8 mux_core_shift;
|
||||
u32 mux_core_mask;
|
||||
int core_reg[ROCKCHIP_CPUCLK_MAX_CORES];
|
||||
u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
|
||||
u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
|
||||
int num_cores;
|
||||
u8 mux_core_alt;
|
||||
u8 mux_core_main;
|
||||
u8 mux_core_shift;
|
||||
u32 mux_core_mask;
|
||||
};
|
||||
|
||||
struct clk *rockchip_clk_register_cpuclk(const char *name,
|
||||
|
||||
@ -115,10 +115,8 @@ static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
reg_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(reg_base)) {
|
||||
dev_err(dev, "failed to map registers\n");
|
||||
if (IS_ERR(reg_base))
|
||||
return PTR_ERR(reg_base);
|
||||
}
|
||||
|
||||
exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
|
||||
ARRAY_SIZE(exynos4x12_clk_isp_save));
|
||||
|
||||
@ -537,8 +537,13 @@ static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
|
||||
GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
|
||||
ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
|
||||
CLK_IS_CRITICAL, 0),
|
||||
/*
|
||||
* This clock is required for the CMU_FSYS1 registers access, keep it
|
||||
* enabled permanently until proper runtime PM support is added.
|
||||
*/
|
||||
GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
|
||||
ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
|
||||
ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
|
||||
CLK_IS_CRITICAL, 0),
|
||||
|
||||
GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
|
||||
"dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
|
||||
|
||||
@ -72,10 +72,8 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(reg_base)) {
|
||||
dev_err(&pdev->dev, "failed to map audss registers\n");
|
||||
if (IS_ERR(reg_base))
|
||||
return PTR_ERR(reg_base);
|
||||
}
|
||||
|
||||
clk_data = devm_kzalloc(&pdev->dev,
|
||||
struct_size(clk_data, hws, AUDSS_MAX_CLKS),
|
||||
|
||||
@ -31,10 +31,10 @@ static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
|
||||
int num_parents = clk_hw_get_num_parents(hw);
|
||||
unsigned int num_parents = clk_hw_get_num_parents(hw);
|
||||
int ret;
|
||||
unsigned int val;
|
||||
u8 i;
|
||||
unsigned int i;
|
||||
|
||||
ret = regmap_read(mux->regmap, mux->reg, &val);
|
||||
if (ret)
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
|
||||
config COMMON_CLK_ZYNQMP
|
||||
bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
|
||||
depends on ARCH_ZYNQMP || COMPILE_TEST
|
||||
depends on ZYNQMP_FIRMWARE
|
||||
depends on ZYNQMP_FIRMWARE || COMPILE_TEST
|
||||
default ZYNQMP_FIRMWARE
|
||||
help
|
||||
Support for the Zynqmp Ultrascale clock controller.
|
||||
It has a dependency on the PMU firmware.
|
||||
|
||||
@ -14,10 +14,12 @@
|
||||
* struct zynqmp_pll - PLL clock
|
||||
* @hw: Handle between common and hardware-specific interfaces
|
||||
* @clk_id: PLL clock ID
|
||||
* @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF
|
||||
*/
|
||||
struct zynqmp_pll {
|
||||
struct clk_hw hw;
|
||||
u32 clk_id;
|
||||
bool set_pll_mode;
|
||||
};
|
||||
|
||||
#define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
|
||||
@ -81,6 +83,8 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
|
||||
if (ret)
|
||||
pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
|
||||
__func__, clk_name, ret);
|
||||
else
|
||||
clk->set_pll_mode = true;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -100,9 +104,7 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
/* Enable the fractional mode if needed */
|
||||
rate_div = (rate * FRAC_DIV) / *prate;
|
||||
f = rate_div % FRAC_DIV;
|
||||
zynqmp_pll_set_mode(hw, !!f);
|
||||
|
||||
if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
|
||||
if (f) {
|
||||
if (rate > PS_PLL_VCO_MAX) {
|
||||
fbdiv = rate / PS_PLL_VCO_MAX;
|
||||
rate = rate / (fbdiv + 1);
|
||||
@ -173,10 +175,12 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
long rate_div, frac, m, f;
|
||||
int ret;
|
||||
|
||||
if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
|
||||
rate_div = (rate * FRAC_DIV) / parent_rate;
|
||||
rate_div = (rate * FRAC_DIV) / parent_rate;
|
||||
f = rate_div % FRAC_DIV;
|
||||
zynqmp_pll_set_mode(hw, !!f);
|
||||
|
||||
if (f) {
|
||||
m = rate_div / FRAC_DIV;
|
||||
f = rate_div % FRAC_DIV;
|
||||
m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
|
||||
rate = parent_rate * m;
|
||||
frac = (parent_rate * f) / FRAC_DIV;
|
||||
@ -240,9 +244,15 @@ static int zynqmp_pll_enable(struct clk_hw *hw)
|
||||
u32 clk_id = clk->clk_id;
|
||||
int ret;
|
||||
|
||||
if (zynqmp_pll_is_enabled(hw))
|
||||
/*
|
||||
* Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request
|
||||
* that has been sent to ATF.
|
||||
*/
|
||||
if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))
|
||||
return 0;
|
||||
|
||||
clk->set_pll_mode = false;
|
||||
|
||||
ret = zynqmp_pm_clock_enable(clk_id);
|
||||
if (ret)
|
||||
pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
|
||||
|
||||
@ -125,7 +125,6 @@
|
||||
#define IMX8MP_CLK_CAN1 116
|
||||
#define IMX8MP_CLK_CAN2 117
|
||||
#define IMX8MP_CLK_MEMREPAIR 118
|
||||
#define IMX8MP_CLK_PCIE_PHY 119
|
||||
#define IMX8MP_CLK_PCIE_AUX 120
|
||||
#define IMX8MP_CLK_I2C5 121
|
||||
#define IMX8MP_CLK_I2C6 122
|
||||
@ -182,8 +181,6 @@
|
||||
#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
|
||||
#define IMX8MP_CLK_MEDIA_LDB 174
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
|
||||
#define IMX8MP_CLK_PCIE2_CTRL 176
|
||||
#define IMX8MP_CLK_PCIE2_PHY 177
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
|
||||
#define IMX8MP_CLK_ECSPI3 179
|
||||
#define IMX8MP_CLK_PDM 180
|
||||
|
||||
926
include/dt-bindings/clock/rk3568-cru.h
Normal file
926
include/dt-bindings/clock/rk3568-cru.h
Normal file
@ -0,0 +1,926 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
|
||||
/* pmucru-clocks indices */
|
||||
|
||||
/* pmucru plls */
|
||||
#define PLL_PPLL 1
|
||||
#define PLL_HPLL 2
|
||||
|
||||
/* pmucru clocks */
|
||||
#define XIN_OSC0_DIV 4
|
||||
#define CLK_RTC_32K 5
|
||||
#define CLK_PMU 6
|
||||
#define CLK_I2C0 7
|
||||
#define CLK_RTC32K_FRAC 8
|
||||
#define CLK_UART0_DIV 9
|
||||
#define CLK_UART0_FRAC 10
|
||||
#define SCLK_UART0 11
|
||||
#define DBCLK_GPIO0 12
|
||||
#define CLK_PWM0 13
|
||||
#define CLK_CAPTURE_PWM0_NDFT 14
|
||||
#define CLK_PMUPVTM 15
|
||||
#define CLK_CORE_PMUPVTM 16
|
||||
#define CLK_REF24M 17
|
||||
#define XIN_OSC0_USBPHY0_G 18
|
||||
#define CLK_USBPHY0_REF 19
|
||||
#define XIN_OSC0_USBPHY1_G 20
|
||||
#define CLK_USBPHY1_REF 21
|
||||
#define XIN_OSC0_MIPIDSIPHY0_G 22
|
||||
#define CLK_MIPIDSIPHY0_REF 23
|
||||
#define XIN_OSC0_MIPIDSIPHY1_G 24
|
||||
#define CLK_MIPIDSIPHY1_REF 25
|
||||
#define CLK_WIFI_DIV 26
|
||||
#define CLK_WIFI_OSC0 27
|
||||
#define CLK_WIFI 28
|
||||
#define CLK_PCIEPHY0_DIV 29
|
||||
#define CLK_PCIEPHY0_OSC0 30
|
||||
#define CLK_PCIEPHY0_REF 31
|
||||
#define CLK_PCIEPHY1_DIV 32
|
||||
#define CLK_PCIEPHY1_OSC0 33
|
||||
#define CLK_PCIEPHY1_REF 34
|
||||
#define CLK_PCIEPHY2_DIV 35
|
||||
#define CLK_PCIEPHY2_OSC0 36
|
||||
#define CLK_PCIEPHY2_REF 37
|
||||
#define CLK_PCIE30PHY_REF_M 38
|
||||
#define CLK_PCIE30PHY_REF_N 39
|
||||
#define CLK_HDMI_REF 40
|
||||
#define XIN_OSC0_EDPPHY_G 41
|
||||
#define PCLK_PDPMU 42
|
||||
#define PCLK_PMU 43
|
||||
#define PCLK_UART0 44
|
||||
#define PCLK_I2C0 45
|
||||
#define PCLK_GPIO0 46
|
||||
#define PCLK_PMUPVTM 47
|
||||
#define PCLK_PWM0 48
|
||||
#define CLK_PDPMU 49
|
||||
#define SCLK_32K_IOE 50
|
||||
|
||||
#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
/* cru plls */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define PLL_VPLL 5
|
||||
#define PLL_NPLL 6
|
||||
|
||||
/* cru clocks */
|
||||
#define CPLL_333M 9
|
||||
#define ARMCLK 10
|
||||
#define USB480M 11
|
||||
#define ACLK_CORE_NIU2BUS 18
|
||||
#define CLK_CORE_PVTM 19
|
||||
#define CLK_CORE_PVTM_CORE 20
|
||||
#define CLK_CORE_PVTPLL 21
|
||||
#define CLK_GPU_SRC 22
|
||||
#define CLK_GPU_PRE_NDFT 23
|
||||
#define CLK_GPU_PRE_MUX 24
|
||||
#define ACLK_GPU_PRE 25
|
||||
#define PCLK_GPU_PRE 26
|
||||
#define CLK_GPU 27
|
||||
#define CLK_GPU_NP5 28
|
||||
#define PCLK_GPU_PVTM 29
|
||||
#define CLK_GPU_PVTM 30
|
||||
#define CLK_GPU_PVTM_CORE 31
|
||||
#define CLK_GPU_PVTPLL 32
|
||||
#define CLK_NPU_SRC 33
|
||||
#define CLK_NPU_PRE_NDFT 34
|
||||
#define CLK_NPU 35
|
||||
#define CLK_NPU_NP5 36
|
||||
#define HCLK_NPU_PRE 37
|
||||
#define PCLK_NPU_PRE 38
|
||||
#define ACLK_NPU_PRE 39
|
||||
#define ACLK_NPU 40
|
||||
#define HCLK_NPU 41
|
||||
#define PCLK_NPU_PVTM 42
|
||||
#define CLK_NPU_PVTM 43
|
||||
#define CLK_NPU_PVTM_CORE 44
|
||||
#define CLK_NPU_PVTPLL 45
|
||||
#define CLK_DDRPHY1X_SRC 46
|
||||
#define CLK_DDRPHY1X_HWFFC_SRC 47
|
||||
#define CLK_DDR1X 48
|
||||
#define CLK_MSCH 49
|
||||
#define CLK24_DDRMON 50
|
||||
#define ACLK_GIC_AUDIO 51
|
||||
#define HCLK_GIC_AUDIO 52
|
||||
#define HCLK_SDMMC_BUFFER 53
|
||||
#define DCLK_SDMMC_BUFFER 54
|
||||
#define ACLK_GIC600 55
|
||||
#define ACLK_SPINLOCK 56
|
||||
#define HCLK_I2S0_8CH 57
|
||||
#define HCLK_I2S1_8CH 58
|
||||
#define HCLK_I2S2_2CH 59
|
||||
#define HCLK_I2S3_2CH 60
|
||||
#define CLK_I2S0_8CH_TX_SRC 61
|
||||
#define CLK_I2S0_8CH_TX_FRAC 62
|
||||
#define MCLK_I2S0_8CH_TX 63
|
||||
#define I2S0_MCLKOUT_TX 64
|
||||
#define CLK_I2S0_8CH_RX_SRC 65
|
||||
#define CLK_I2S0_8CH_RX_FRAC 66
|
||||
#define MCLK_I2S0_8CH_RX 67
|
||||
#define I2S0_MCLKOUT_RX 68
|
||||
#define CLK_I2S1_8CH_TX_SRC 69
|
||||
#define CLK_I2S1_8CH_TX_FRAC 70
|
||||
#define MCLK_I2S1_8CH_TX 71
|
||||
#define I2S1_MCLKOUT_TX 72
|
||||
#define CLK_I2S1_8CH_RX_SRC 73
|
||||
#define CLK_I2S1_8CH_RX_FRAC 74
|
||||
#define MCLK_I2S1_8CH_RX 75
|
||||
#define I2S1_MCLKOUT_RX 76
|
||||
#define CLK_I2S2_2CH_SRC 77
|
||||
#define CLK_I2S2_2CH_FRAC 78
|
||||
#define MCLK_I2S2_2CH 79
|
||||
#define I2S2_MCLKOUT 80
|
||||
#define CLK_I2S3_2CH_TX_SRC 81
|
||||
#define CLK_I2S3_2CH_TX_FRAC 82
|
||||
#define MCLK_I2S3_2CH_TX 83
|
||||
#define I2S3_MCLKOUT_TX 84
|
||||
#define CLK_I2S3_2CH_RX_SRC 85
|
||||
#define CLK_I2S3_2CH_RX_FRAC 86
|
||||
#define MCLK_I2S3_2CH_RX 87
|
||||
#define I2S3_MCLKOUT_RX 88
|
||||
#define HCLK_PDM 89
|
||||
#define MCLK_PDM 90
|
||||
#define HCLK_VAD 91
|
||||
#define HCLK_SPDIF_8CH 92
|
||||
#define MCLK_SPDIF_8CH_SRC 93
|
||||
#define MCLK_SPDIF_8CH_FRAC 94
|
||||
#define MCLK_SPDIF_8CH 95
|
||||
#define HCLK_AUDPWM 96
|
||||
#define SCLK_AUDPWM_SRC 97
|
||||
#define SCLK_AUDPWM_FRAC 98
|
||||
#define SCLK_AUDPWM 99
|
||||
#define HCLK_ACDCDIG 100
|
||||
#define CLK_ACDCDIG_I2C 101
|
||||
#define CLK_ACDCDIG_DAC 102
|
||||
#define CLK_ACDCDIG_ADC 103
|
||||
#define ACLK_SECURE_FLASH 104
|
||||
#define HCLK_SECURE_FLASH 105
|
||||
#define ACLK_CRYPTO_NS 106
|
||||
#define HCLK_CRYPTO_NS 107
|
||||
#define CLK_CRYPTO_NS_CORE 108
|
||||
#define CLK_CRYPTO_NS_PKA 109
|
||||
#define CLK_CRYPTO_NS_RNG 110
|
||||
#define HCLK_TRNG_NS 111
|
||||
#define CLK_TRNG_NS 112
|
||||
#define PCLK_OTPC_NS 113
|
||||
#define CLK_OTPC_NS_SBPI 114
|
||||
#define CLK_OTPC_NS_USR 115
|
||||
#define HCLK_NANDC 116
|
||||
#define NCLK_NANDC 117
|
||||
#define HCLK_SFC 118
|
||||
#define HCLK_SFC_XIP 119
|
||||
#define SCLK_SFC 120
|
||||
#define ACLK_EMMC 121
|
||||
#define HCLK_EMMC 122
|
||||
#define BCLK_EMMC 123
|
||||
#define CCLK_EMMC 124
|
||||
#define TCLK_EMMC 125
|
||||
#define ACLK_PIPE 126
|
||||
#define PCLK_PIPE 127
|
||||
#define PCLK_PIPE_GRF 128
|
||||
#define ACLK_PCIE20_MST 129
|
||||
#define ACLK_PCIE20_SLV 130
|
||||
#define ACLK_PCIE20_DBI 131
|
||||
#define PCLK_PCIE20 132
|
||||
#define CLK_PCIE20_AUX_NDFT 133
|
||||
#define CLK_PCIE20_AUX_DFT 134
|
||||
#define CLK_PCIE20_PIPE_DFT 135
|
||||
#define ACLK_PCIE30X1_MST 136
|
||||
#define ACLK_PCIE30X1_SLV 137
|
||||
#define ACLK_PCIE30X1_DBI 138
|
||||
#define PCLK_PCIE30X1 139
|
||||
#define CLK_PCIE30X1_AUX_NDFT 140
|
||||
#define CLK_PCIE30X1_AUX_DFT 141
|
||||
#define CLK_PCIE30X1_PIPE_DFT 142
|
||||
#define ACLK_PCIE30X2_MST 143
|
||||
#define ACLK_PCIE30X2_SLV 144
|
||||
#define ACLK_PCIE30X2_DBI 145
|
||||
#define PCLK_PCIE30X2 146
|
||||
#define CLK_PCIE30X2_AUX_NDFT 147
|
||||
#define CLK_PCIE30X2_AUX_DFT 148
|
||||
#define CLK_PCIE30X2_PIPE_DFT 149
|
||||
#define ACLK_SATA0 150
|
||||
#define CLK_SATA0_PMALIVE 151
|
||||
#define CLK_SATA0_RXOOB 152
|
||||
#define CLK_SATA0_PIPE_NDFT 153
|
||||
#define CLK_SATA0_PIPE_DFT 154
|
||||
#define ACLK_SATA1 155
|
||||
#define CLK_SATA1_PMALIVE 156
|
||||
#define CLK_SATA1_RXOOB 157
|
||||
#define CLK_SATA1_PIPE_NDFT 158
|
||||
#define CLK_SATA1_PIPE_DFT 159
|
||||
#define ACLK_SATA2 160
|
||||
#define CLK_SATA2_PMALIVE 161
|
||||
#define CLK_SATA2_RXOOB 162
|
||||
#define CLK_SATA2_PIPE_NDFT 163
|
||||
#define CLK_SATA2_PIPE_DFT 164
|
||||
#define ACLK_USB3OTG0 165
|
||||
#define CLK_USB3OTG0_REF 166
|
||||
#define CLK_USB3OTG0_SUSPEND 167
|
||||
#define ACLK_USB3OTG1 168
|
||||
#define CLK_USB3OTG1_REF 169
|
||||
#define CLK_USB3OTG1_SUSPEND 170
|
||||
#define CLK_XPCS_EEE 171
|
||||
#define PCLK_XPCS 172
|
||||
#define ACLK_PHP 173
|
||||
#define HCLK_PHP 174
|
||||
#define PCLK_PHP 175
|
||||
#define HCLK_SDMMC0 176
|
||||
#define CLK_SDMMC0 177
|
||||
#define HCLK_SDMMC1 178
|
||||
#define CLK_SDMMC1 179
|
||||
#define ACLK_GMAC0 180
|
||||
#define PCLK_GMAC0 181
|
||||
#define CLK_MAC0_2TOP 182
|
||||
#define CLK_MAC0_OUT 183
|
||||
#define CLK_MAC0_REFOUT 184
|
||||
#define CLK_GMAC0_PTP_REF 185
|
||||
#define ACLK_USB 186
|
||||
#define HCLK_USB 187
|
||||
#define PCLK_USB 188
|
||||
#define HCLK_USB2HOST0 189
|
||||
#define HCLK_USB2HOST0_ARB 190
|
||||
#define HCLK_USB2HOST1 191
|
||||
#define HCLK_USB2HOST1_ARB 192
|
||||
#define HCLK_SDMMC2 193
|
||||
#define CLK_SDMMC2 194
|
||||
#define ACLK_GMAC1 195
|
||||
#define PCLK_GMAC1 196
|
||||
#define CLK_MAC1_2TOP 197
|
||||
#define CLK_MAC1_OUT 198
|
||||
#define CLK_MAC1_REFOUT 199
|
||||
#define CLK_GMAC1_PTP_REF 200
|
||||
#define ACLK_PERIMID 201
|
||||
#define HCLK_PERIMID 202
|
||||
#define ACLK_VI 203
|
||||
#define HCLK_VI 204
|
||||
#define PCLK_VI 205
|
||||
#define ACLK_VICAP 206
|
||||
#define HCLK_VICAP 207
|
||||
#define DCLK_VICAP 208
|
||||
#define ICLK_VICAP_G 209
|
||||
#define ACLK_ISP 210
|
||||
#define HCLK_ISP 211
|
||||
#define CLK_ISP 212
|
||||
#define PCLK_CSI2HOST1 213
|
||||
#define CLK_CIF_OUT 214
|
||||
#define CLK_CAM0_OUT 215
|
||||
#define CLK_CAM1_OUT 216
|
||||
#define ACLK_VO 217
|
||||
#define HCLK_VO 218
|
||||
#define PCLK_VO 219
|
||||
#define ACLK_VOP_PRE 220
|
||||
#define ACLK_VOP 221
|
||||
#define HCLK_VOP 222
|
||||
#define DCLK_VOP0 223
|
||||
#define DCLK_VOP1 224
|
||||
#define DCLK_VOP2 225
|
||||
#define CLK_VOP_PWM 226
|
||||
#define ACLK_HDCP 227
|
||||
#define HCLK_HDCP 228
|
||||
#define PCLK_HDCP 229
|
||||
#define PCLK_HDMI_HOST 230
|
||||
#define CLK_HDMI_SFR 231
|
||||
#define PCLK_DSITX_0 232
|
||||
#define PCLK_DSITX_1 233
|
||||
#define PCLK_EDP_CTRL 234
|
||||
#define CLK_EDP_200M 235
|
||||
#define ACLK_VPU_PRE 236
|
||||
#define HCLK_VPU_PRE 237
|
||||
#define ACLK_VPU 238
|
||||
#define HCLK_VPU 239
|
||||
#define ACLK_RGA_PRE 240
|
||||
#define HCLK_RGA_PRE 241
|
||||
#define PCLK_RGA_PRE 242
|
||||
#define ACLK_RGA 243
|
||||
#define HCLK_RGA 244
|
||||
#define CLK_RGA_CORE 245
|
||||
#define ACLK_IEP 246
|
||||
#define HCLK_IEP 247
|
||||
#define CLK_IEP_CORE 248
|
||||
#define HCLK_EBC 249
|
||||
#define DCLK_EBC 250
|
||||
#define ACLK_JDEC 251
|
||||
#define HCLK_JDEC 252
|
||||
#define ACLK_JENC 253
|
||||
#define HCLK_JENC 254
|
||||
#define PCLK_EINK 255
|
||||
#define HCLK_EINK 256
|
||||
#define ACLK_RKVENC_PRE 257
|
||||
#define HCLK_RKVENC_PRE 258
|
||||
#define ACLK_RKVENC 259
|
||||
#define HCLK_RKVENC 260
|
||||
#define CLK_RKVENC_CORE 261
|
||||
#define ACLK_RKVDEC_PRE 262
|
||||
#define HCLK_RKVDEC_PRE 263
|
||||
#define ACLK_RKVDEC 264
|
||||
#define HCLK_RKVDEC 265
|
||||
#define CLK_RKVDEC_CA 266
|
||||
#define CLK_RKVDEC_CORE 267
|
||||
#define CLK_RKVDEC_HEVC_CA 268
|
||||
#define ACLK_BUS 269
|
||||
#define PCLK_BUS 270
|
||||
#define PCLK_TSADC 271
|
||||
#define CLK_TSADC_TSEN 272
|
||||
#define CLK_TSADC 273
|
||||
#define PCLK_SARADC 274
|
||||
#define CLK_SARADC 275
|
||||
#define PCLK_SCR 276
|
||||
#define PCLK_WDT_NS 277
|
||||
#define TCLK_WDT_NS 278
|
||||
#define ACLK_DMAC0 279
|
||||
#define ACLK_DMAC1 280
|
||||
#define ACLK_MCU 281
|
||||
#define PCLK_INTMUX 282
|
||||
#define PCLK_MAILBOX 283
|
||||
#define PCLK_UART1 284
|
||||
#define CLK_UART1_SRC 285
|
||||
#define CLK_UART1_FRAC 286
|
||||
#define SCLK_UART1 287
|
||||
#define PCLK_UART2 288
|
||||
#define CLK_UART2_SRC 289
|
||||
#define CLK_UART2_FRAC 290
|
||||
#define SCLK_UART2 291
|
||||
#define PCLK_UART3 292
|
||||
#define CLK_UART3_SRC 293
|
||||
#define CLK_UART3_FRAC 294
|
||||
#define SCLK_UART3 295
|
||||
#define PCLK_UART4 296
|
||||
#define CLK_UART4_SRC 297
|
||||
#define CLK_UART4_FRAC 298
|
||||
#define SCLK_UART4 299
|
||||
#define PCLK_UART5 300
|
||||
#define CLK_UART5_SRC 301
|
||||
#define CLK_UART5_FRAC 302
|
||||
#define SCLK_UART5 303
|
||||
#define PCLK_UART6 304
|
||||
#define CLK_UART6_SRC 305
|
||||
#define CLK_UART6_FRAC 306
|
||||
#define SCLK_UART6 307
|
||||
#define PCLK_UART7 308
|
||||
#define CLK_UART7_SRC 309
|
||||
#define CLK_UART7_FRAC 310
|
||||
#define SCLK_UART7 311
|
||||
#define PCLK_UART8 312
|
||||
#define CLK_UART8_SRC 313
|
||||
#define CLK_UART8_FRAC 314
|
||||
#define SCLK_UART8 315
|
||||
#define PCLK_UART9 316
|
||||
#define CLK_UART9_SRC 317
|
||||
#define CLK_UART9_FRAC 318
|
||||
#define SCLK_UART9 319
|
||||
#define PCLK_CAN0 320
|
||||
#define CLK_CAN0 321
|
||||
#define PCLK_CAN1 322
|
||||
#define CLK_CAN1 323
|
||||
#define PCLK_CAN2 324
|
||||
#define CLK_CAN2 325
|
||||
#define CLK_I2C 326
|
||||
#define PCLK_I2C1 327
|
||||
#define CLK_I2C1 328
|
||||
#define PCLK_I2C2 329
|
||||
#define CLK_I2C2 330
|
||||
#define PCLK_I2C3 331
|
||||
#define CLK_I2C3 332
|
||||
#define PCLK_I2C4 333
|
||||
#define CLK_I2C4 334
|
||||
#define PCLK_I2C5 335
|
||||
#define CLK_I2C5 336
|
||||
#define PCLK_SPI0 337
|
||||
#define CLK_SPI0 338
|
||||
#define PCLK_SPI1 339
|
||||
#define CLK_SPI1 340
|
||||
#define PCLK_SPI2 341
|
||||
#define CLK_SPI2 342
|
||||
#define PCLK_SPI3 343
|
||||
#define CLK_SPI3 344
|
||||
#define PCLK_PWM1 345
|
||||
#define CLK_PWM1 346
|
||||
#define CLK_PWM1_CAPTURE 347
|
||||
#define PCLK_PWM2 348
|
||||
#define CLK_PWM2 349
|
||||
#define CLK_PWM2_CAPTURE 350
|
||||
#define PCLK_PWM3 351
|
||||
#define CLK_PWM3 352
|
||||
#define CLK_PWM3_CAPTURE 353
|
||||
#define DBCLK_GPIO 354
|
||||
#define PCLK_GPIO1 355
|
||||
#define DBCLK_GPIO1 356
|
||||
#define PCLK_GPIO2 357
|
||||
#define DBCLK_GPIO2 358
|
||||
#define PCLK_GPIO3 359
|
||||
#define DBCLK_GPIO3 360
|
||||
#define PCLK_GPIO4 361
|
||||
#define DBCLK_GPIO4 362
|
||||
#define OCC_SCAN_CLK_GPIO 363
|
||||
#define PCLK_TIMER 364
|
||||
#define CLK_TIMER0 365
|
||||
#define CLK_TIMER1 366
|
||||
#define CLK_TIMER2 367
|
||||
#define CLK_TIMER3 368
|
||||
#define CLK_TIMER4 369
|
||||
#define CLK_TIMER5 370
|
||||
#define ACLK_TOP_HIGH 371
|
||||
#define ACLK_TOP_LOW 372
|
||||
#define HCLK_TOP 373
|
||||
#define PCLK_TOP 374
|
||||
#define PCLK_PCIE30PHY 375
|
||||
#define CLK_OPTC_ARB 376
|
||||
#define PCLK_MIPICSIPHY 377
|
||||
#define PCLK_MIPIDSIPHY0 378
|
||||
#define PCLK_MIPIDSIPHY1 379
|
||||
#define PCLK_PIPEPHY0 380
|
||||
#define PCLK_PIPEPHY1 381
|
||||
#define PCLK_PIPEPHY2 382
|
||||
#define PCLK_CPU_BOOST 383
|
||||
#define CLK_CPU_BOOST 384
|
||||
#define PCLK_OTPPHY 385
|
||||
#define SCLK_GMAC0 386
|
||||
#define SCLK_GMAC0_RGMII_SPEED 387
|
||||
#define SCLK_GMAC0_RMII_SPEED 388
|
||||
#define SCLK_GMAC0_RX_TX 389
|
||||
#define SCLK_GMAC1 390
|
||||
#define SCLK_GMAC1_RGMII_SPEED 391
|
||||
#define SCLK_GMAC1_RMII_SPEED 392
|
||||
#define SCLK_GMAC1_RX_TX 393
|
||||
#define SCLK_SDMMC0_DRV 394
|
||||
#define SCLK_SDMMC0_SAMPLE 395
|
||||
#define SCLK_SDMMC1_DRV 396
|
||||
#define SCLK_SDMMC1_SAMPLE 397
|
||||
#define SCLK_SDMMC2_DRV 398
|
||||
#define SCLK_SDMMC2_SAMPLE 399
|
||||
#define SCLK_EMMC_DRV 400
|
||||
#define SCLK_EMMC_SAMPLE 401
|
||||
#define PCLK_EDPPHY_GRF 402
|
||||
#define CLK_HDMI_CEC 403
|
||||
#define CLK_I2S0_8CH_TX 404
|
||||
#define CLK_I2S0_8CH_RX 405
|
||||
#define CLK_I2S1_8CH_TX 406
|
||||
#define CLK_I2S1_8CH_RX 407
|
||||
#define CLK_I2S2_2CH 408
|
||||
#define CLK_I2S3_2CH_TX 409
|
||||
#define CLK_I2S3_2CH_RX 410
|
||||
#define CPLL_500M 411
|
||||
#define CPLL_250M 412
|
||||
#define CPLL_125M 413
|
||||
#define CPLL_62P5M 414
|
||||
#define CPLL_50M 415
|
||||
#define CPLL_25M 416
|
||||
#define CPLL_100M 417
|
||||
#define SCLK_DDRCLK 418
|
||||
|
||||
#define PCLK_CORE_PVTM 450
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
|
||||
|
||||
/* pmu soft-reset indices */
|
||||
/* pmucru_softrst_con0 */
|
||||
#define SRST_P_PDPMU_NIU 0
|
||||
#define SRST_P_PMUCRU 1
|
||||
#define SRST_P_PMUGRF 2
|
||||
#define SRST_P_I2C0 3
|
||||
#define SRST_I2C0 4
|
||||
#define SRST_P_UART0 5
|
||||
#define SRST_S_UART0 6
|
||||
#define SRST_P_PWM0 7
|
||||
#define SRST_PWM0 8
|
||||
#define SRST_P_GPIO0 9
|
||||
#define SRST_GPIO0 10
|
||||
#define SRST_P_PMUPVTM 11
|
||||
#define SRST_PMUPVTM 12
|
||||
|
||||
/* soft-reset indices */
|
||||
|
||||
/* cru_softrst_con0 */
|
||||
#define SRST_NCORERESET0 0
|
||||
#define SRST_NCORERESET1 1
|
||||
#define SRST_NCORERESET2 2
|
||||
#define SRST_NCORERESET3 3
|
||||
#define SRST_NCPUPORESET0 4
|
||||
#define SRST_NCPUPORESET1 5
|
||||
#define SRST_NCPUPORESET2 6
|
||||
#define SRST_NCPUPORESET3 7
|
||||
#define SRST_NSRESET 8
|
||||
#define SRST_NSPORESET 9
|
||||
#define SRST_NATRESET 10
|
||||
#define SRST_NGICRESET 11
|
||||
#define SRST_NPRESET 12
|
||||
#define SRST_NPERIPHRESET 13
|
||||
|
||||
/* cru_softrst_con1 */
|
||||
#define SRST_A_CORE_NIU2DDR 16
|
||||
#define SRST_A_CORE_NIU2BUS 17
|
||||
#define SRST_P_DBG_NIU 18
|
||||
#define SRST_P_DBG 19
|
||||
#define SRST_P_DBG_DAPLITE 20
|
||||
#define SRST_DAP 21
|
||||
#define SRST_A_ADB400_CORE2GIC 22
|
||||
#define SRST_A_ADB400_GIC2CORE 23
|
||||
#define SRST_P_CORE_GRF 24
|
||||
#define SRST_P_CORE_PVTM 25
|
||||
#define SRST_CORE_PVTM 26
|
||||
#define SRST_CORE_PVTPLL 27
|
||||
|
||||
/* cru_softrst_con2 */
|
||||
#define SRST_GPU 32
|
||||
#define SRST_A_GPU_NIU 33
|
||||
#define SRST_P_GPU_NIU 34
|
||||
#define SRST_P_GPU_PVTM 35
|
||||
#define SRST_GPU_PVTM 36
|
||||
#define SRST_GPU_PVTPLL 37
|
||||
#define SRST_A_NPU_NIU 40
|
||||
#define SRST_H_NPU_NIU 41
|
||||
#define SRST_P_NPU_NIU 42
|
||||
#define SRST_A_NPU 43
|
||||
#define SRST_H_NPU 44
|
||||
#define SRST_P_NPU_PVTM 45
|
||||
#define SRST_NPU_PVTM 46
|
||||
#define SRST_NPU_PVTPLL 47
|
||||
|
||||
/* cru_softrst_con3 */
|
||||
#define SRST_A_MSCH 51
|
||||
#define SRST_HWFFC_CTRL 52
|
||||
#define SRST_DDR_ALWAYSON 53
|
||||
#define SRST_A_DDRSPLIT 54
|
||||
#define SRST_DDRDFI_CTL 55
|
||||
#define SRST_A_DMA2DDR 57
|
||||
|
||||
/* cru_softrst_con4 */
|
||||
#define SRST_A_PERIMID_NIU 64
|
||||
#define SRST_H_PERIMID_NIU 65
|
||||
#define SRST_A_GIC_AUDIO_NIU 66
|
||||
#define SRST_H_GIC_AUDIO_NIU 67
|
||||
#define SRST_A_GIC600 68
|
||||
#define SRST_A_GIC600_DEBUG 69
|
||||
#define SRST_A_GICADB_CORE2GIC 70
|
||||
#define SRST_A_GICADB_GIC2CORE 71
|
||||
#define SRST_A_SPINLOCK 72
|
||||
#define SRST_H_SDMMC_BUFFER 73
|
||||
#define SRST_D_SDMMC_BUFFER 74
|
||||
#define SRST_H_I2S0_8CH 75
|
||||
#define SRST_H_I2S1_8CH 76
|
||||
#define SRST_H_I2S2_2CH 77
|
||||
#define SRST_H_I2S3_2CH 78
|
||||
|
||||
/* cru_softrst_con5 */
|
||||
#define SRST_M_I2S0_8CH_TX 80
|
||||
#define SRST_M_I2S0_8CH_RX 81
|
||||
#define SRST_M_I2S1_8CH_TX 82
|
||||
#define SRST_M_I2S1_8CH_RX 83
|
||||
#define SRST_M_I2S2_2CH 84
|
||||
#define SRST_M_I2S3_2CH_TX 85
|
||||
#define SRST_M_I2S3_2CH_RX 86
|
||||
#define SRST_H_PDM 87
|
||||
#define SRST_M_PDM 88
|
||||
#define SRST_H_VAD 89
|
||||
#define SRST_H_SPDIF_8CH 90
|
||||
#define SRST_M_SPDIF_8CH 91
|
||||
#define SRST_H_AUDPWM 92
|
||||
#define SRST_S_AUDPWM 93
|
||||
#define SRST_H_ACDCDIG 94
|
||||
#define SRST_ACDCDIG 95
|
||||
|
||||
/* cru_softrst_con6 */
|
||||
#define SRST_A_SECURE_FLASH_NIU 96
|
||||
#define SRST_H_SECURE_FLASH_NIU 97
|
||||
#define SRST_A_CRYPTO_NS 103
|
||||
#define SRST_H_CRYPTO_NS 104
|
||||
#define SRST_CRYPTO_NS_CORE 105
|
||||
#define SRST_CRYPTO_NS_PKA 106
|
||||
#define SRST_CRYPTO_NS_RNG 107
|
||||
#define SRST_H_TRNG_NS 108
|
||||
#define SRST_TRNG_NS 109
|
||||
|
||||
/* cru_softrst_con7 */
|
||||
#define SRST_H_NANDC 112
|
||||
#define SRST_N_NANDC 113
|
||||
#define SRST_H_SFC 114
|
||||
#define SRST_H_SFC_XIP 115
|
||||
#define SRST_S_SFC 116
|
||||
#define SRST_A_EMMC 117
|
||||
#define SRST_H_EMMC 118
|
||||
#define SRST_B_EMMC 119
|
||||
#define SRST_C_EMMC 120
|
||||
#define SRST_T_EMMC 121
|
||||
|
||||
/* cru_softrst_con8 */
|
||||
#define SRST_A_PIPE_NIU 128
|
||||
#define SRST_P_PIPE_NIU 130
|
||||
#define SRST_P_PIPE_GRF 133
|
||||
#define SRST_A_SATA0 134
|
||||
#define SRST_SATA0_PIPE 135
|
||||
#define SRST_SATA0_PMALIVE 136
|
||||
#define SRST_SATA0_RXOOB 137
|
||||
#define SRST_A_SATA1 138
|
||||
#define SRST_SATA1_PIPE 139
|
||||
#define SRST_SATA1_PMALIVE 140
|
||||
#define SRST_SATA1_RXOOB 141
|
||||
|
||||
/* cru_softrst_con9 */
|
||||
#define SRST_A_SATA2 144
|
||||
#define SRST_SATA2_PIPE 145
|
||||
#define SRST_SATA2_PMALIVE 146
|
||||
#define SRST_SATA2_RXOOB 147
|
||||
#define SRST_USB3OTG0 148
|
||||
#define SRST_USB3OTG1 149
|
||||
#define SRST_XPCS 150
|
||||
#define SRST_XPCS_TX_DIV10 151
|
||||
#define SRST_XPCS_RX_DIV10 152
|
||||
#define SRST_XPCS_XGXS_RX 153
|
||||
|
||||
/* cru_softrst_con10 */
|
||||
#define SRST_P_PCIE20 160
|
||||
#define SRST_PCIE20_POWERUP 161
|
||||
#define SRST_MSTR_ARESET_PCIE20 162
|
||||
#define SRST_SLV_ARESET_PCIE20 163
|
||||
#define SRST_DBI_ARESET_PCIE20 164
|
||||
#define SRST_BRESET_PCIE20 165
|
||||
#define SRST_PERST_PCIE20 166
|
||||
#define SRST_CORE_RST_PCIE20 167
|
||||
#define SRST_NSTICKY_RST_PCIE20 168
|
||||
#define SRST_STICKY_RST_PCIE20 169
|
||||
#define SRST_PWR_RST_PCIE20 170
|
||||
|
||||
/* cru_softrst_con11 */
|
||||
#define SRST_P_PCIE30X1 176
|
||||
#define SRST_PCIE30X1_POWERUP 177
|
||||
#define SRST_M_ARESET_PCIE30X1 178
|
||||
#define SRST_S_ARESET_PCIE30X1 179
|
||||
#define SRST_D_ARESET_PCIE30X1 180
|
||||
#define SRST_BRESET_PCIE30X1 181
|
||||
#define SRST_PERST_PCIE30X1 182
|
||||
#define SRST_CORE_RST_PCIE30X1 183
|
||||
#define SRST_NSTC_RST_PCIE30X1 184
|
||||
#define SRST_STC_RST_PCIE30X1 185
|
||||
#define SRST_PWR_RST_PCIE30X1 186
|
||||
|
||||
/* cru_softrst_con12 */
|
||||
#define SRST_P_PCIE30X2 192
|
||||
#define SRST_PCIE30X2_POWERUP 193
|
||||
#define SRST_M_ARESET_PCIE30X2 194
|
||||
#define SRST_S_ARESET_PCIE30X2 195
|
||||
#define SRST_D_ARESET_PCIE30X2 196
|
||||
#define SRST_BRESET_PCIE30X2 197
|
||||
#define SRST_PERST_PCIE30X2 198
|
||||
#define SRST_CORE_RST_PCIE30X2 199
|
||||
#define SRST_NSTC_RST_PCIE30X2 200
|
||||
#define SRST_STC_RST_PCIE30X2 201
|
||||
#define SRST_PWR_RST_PCIE30X2 202
|
||||
|
||||
/* cru_softrst_con13 */
|
||||
#define SRST_A_PHP_NIU 208
|
||||
#define SRST_H_PHP_NIU 209
|
||||
#define SRST_P_PHP_NIU 210
|
||||
#define SRST_H_SDMMC0 211
|
||||
#define SRST_SDMMC0 212
|
||||
#define SRST_H_SDMMC1 213
|
||||
#define SRST_SDMMC1 214
|
||||
#define SRST_A_GMAC0 215
|
||||
#define SRST_GMAC0_TIMESTAMP 216
|
||||
|
||||
/* cru_softrst_con14 */
|
||||
#define SRST_A_USB_NIU 224
|
||||
#define SRST_H_USB_NIU 225
|
||||
#define SRST_P_USB_NIU 226
|
||||
#define SRST_P_USB_GRF 227
|
||||
#define SRST_H_USB2HOST0 228
|
||||
#define SRST_H_USB2HOST0_ARB 229
|
||||
#define SRST_USB2HOST0_UTMI 230
|
||||
#define SRST_H_USB2HOST1 231
|
||||
#define SRST_H_USB2HOST1_ARB 232
|
||||
#define SRST_USB2HOST1_UTMI 233
|
||||
#define SRST_H_SDMMC2 234
|
||||
#define SRST_SDMMC2 235
|
||||
#define SRST_A_GMAC1 236
|
||||
#define SRST_GMAC1_TIMESTAMP 237
|
||||
|
||||
/* cru_softrst_con15 */
|
||||
#define SRST_A_VI_NIU 240
|
||||
#define SRST_H_VI_NIU 241
|
||||
#define SRST_P_VI_NIU 242
|
||||
#define SRST_A_VICAP 247
|
||||
#define SRST_H_VICAP 248
|
||||
#define SRST_D_VICAP 249
|
||||
#define SRST_I_VICAP 250
|
||||
#define SRST_P_VICAP 251
|
||||
#define SRST_H_ISP 252
|
||||
#define SRST_ISP 253
|
||||
#define SRST_P_CSI2HOST1 255
|
||||
|
||||
/* cru_softrst_con16 */
|
||||
#define SRST_A_VO_NIU 256
|
||||
#define SRST_H_VO_NIU 257
|
||||
#define SRST_P_VO_NIU 258
|
||||
#define SRST_A_VOP_NIU 259
|
||||
#define SRST_A_VOP 260
|
||||
#define SRST_H_VOP 261
|
||||
#define SRST_VOP0 262
|
||||
#define SRST_VOP1 263
|
||||
#define SRST_VOP2 264
|
||||
#define SRST_VOP_PWM 265
|
||||
#define SRST_A_HDCP 266
|
||||
#define SRST_H_HDCP 267
|
||||
#define SRST_P_HDCP 268
|
||||
#define SRST_P_HDMI_HOST 270
|
||||
#define SRST_HDMI_HOST 271
|
||||
|
||||
/* cru_softrst_con17 */
|
||||
#define SRST_P_DSITX_0 272
|
||||
#define SRST_P_DSITX_1 273
|
||||
#define SRST_P_EDP_CTRL 274
|
||||
#define SRST_EDP_24M 275
|
||||
#define SRST_A_VPU_NIU 280
|
||||
#define SRST_H_VPU_NIU 281
|
||||
#define SRST_A_VPU 282
|
||||
#define SRST_H_VPU 283
|
||||
#define SRST_H_EINK 286
|
||||
#define SRST_P_EINK 287
|
||||
|
||||
/* cru_softrst_con18 */
|
||||
#define SRST_A_RGA_NIU 288
|
||||
#define SRST_H_RGA_NIU 289
|
||||
#define SRST_P_RGA_NIU 290
|
||||
#define SRST_A_RGA 292
|
||||
#define SRST_H_RGA 293
|
||||
#define SRST_RGA_CORE 294
|
||||
#define SRST_A_IEP 295
|
||||
#define SRST_H_IEP 296
|
||||
#define SRST_IEP_CORE 297
|
||||
#define SRST_H_EBC 298
|
||||
#define SRST_D_EBC 299
|
||||
#define SRST_A_JDEC 300
|
||||
#define SRST_H_JDEC 301
|
||||
#define SRST_A_JENC 302
|
||||
#define SRST_H_JENC 303
|
||||
|
||||
/* cru_softrst_con19 */
|
||||
#define SRST_A_VENC_NIU 304
|
||||
#define SRST_H_VENC_NIU 305
|
||||
#define SRST_A_RKVENC 307
|
||||
#define SRST_H_RKVENC 308
|
||||
#define SRST_RKVENC_CORE 309
|
||||
|
||||
/* cru_softrst_con20 */
|
||||
#define SRST_A_RKVDEC_NIU 320
|
||||
#define SRST_H_RKVDEC_NIU 321
|
||||
#define SRST_A_RKVDEC 322
|
||||
#define SRST_H_RKVDEC 323
|
||||
#define SRST_RKVDEC_CA 324
|
||||
#define SRST_RKVDEC_CORE 325
|
||||
#define SRST_RKVDEC_HEVC_CA 326
|
||||
|
||||
/* cru_softrst_con21 */
|
||||
#define SRST_A_BUS_NIU 336
|
||||
#define SRST_P_BUS_NIU 338
|
||||
#define SRST_P_CAN0 340
|
||||
#define SRST_CAN0 341
|
||||
#define SRST_P_CAN1 342
|
||||
#define SRST_CAN1 343
|
||||
#define SRST_P_CAN2 344
|
||||
#define SRST_CAN2 345
|
||||
#define SRST_P_GPIO1 346
|
||||
#define SRST_GPIO1 347
|
||||
#define SRST_P_GPIO2 348
|
||||
#define SRST_GPIO2 349
|
||||
#define SRST_P_GPIO3 350
|
||||
#define SRST_GPIO3 351
|
||||
|
||||
/* cru_softrst_con22 */
|
||||
#define SRST_P_GPIO4 352
|
||||
#define SRST_GPIO4 353
|
||||
#define SRST_P_I2C1 354
|
||||
#define SRST_I2C1 355
|
||||
#define SRST_P_I2C2 356
|
||||
#define SRST_I2C2 357
|
||||
#define SRST_P_I2C3 358
|
||||
#define SRST_I2C3 359
|
||||
#define SRST_P_I2C4 360
|
||||
#define SRST_I2C4 361
|
||||
#define SRST_P_I2C5 362
|
||||
#define SRST_I2C5 363
|
||||
#define SRST_P_OTPC_NS 364
|
||||
#define SRST_OTPC_NS_SBPI 365
|
||||
#define SRST_OTPC_NS_USR 366
|
||||
|
||||
/* cru_softrst_con23 */
|
||||
#define SRST_P_PWM1 368
|
||||
#define SRST_PWM1 369
|
||||
#define SRST_P_PWM2 370
|
||||
#define SRST_PWM2 371
|
||||
#define SRST_P_PWM3 372
|
||||
#define SRST_PWM3 373
|
||||
#define SRST_P_SPI0 374
|
||||
#define SRST_SPI0 375
|
||||
#define SRST_P_SPI1 376
|
||||
#define SRST_SPI1 377
|
||||
#define SRST_P_SPI2 378
|
||||
#define SRST_SPI2 379
|
||||
#define SRST_P_SPI3 380
|
||||
#define SRST_SPI3 381
|
||||
|
||||
/* cru_softrst_con24 */
|
||||
#define SRST_P_SARADC 384
|
||||
#define SRST_P_TSADC 385
|
||||
#define SRST_TSADC 386
|
||||
#define SRST_P_TIMER 387
|
||||
#define SRST_TIMER0 388
|
||||
#define SRST_TIMER1 389
|
||||
#define SRST_TIMER2 390
|
||||
#define SRST_TIMER3 391
|
||||
#define SRST_TIMER4 392
|
||||
#define SRST_TIMER5 393
|
||||
#define SRST_P_UART1 394
|
||||
#define SRST_S_UART1 395
|
||||
|
||||
/* cru_softrst_con25 */
|
||||
#define SRST_P_UART2 400
|
||||
#define SRST_S_UART2 401
|
||||
#define SRST_P_UART3 402
|
||||
#define SRST_S_UART3 403
|
||||
#define SRST_P_UART4 404
|
||||
#define SRST_S_UART4 405
|
||||
#define SRST_P_UART5 406
|
||||
#define SRST_S_UART5 407
|
||||
#define SRST_P_UART6 408
|
||||
#define SRST_S_UART6 409
|
||||
#define SRST_P_UART7 410
|
||||
#define SRST_S_UART7 411
|
||||
#define SRST_P_UART8 412
|
||||
#define SRST_S_UART8 413
|
||||
#define SRST_P_UART9 414
|
||||
#define SRST_S_UART9 415
|
||||
|
||||
/* cru_softrst_con26 */
|
||||
#define SRST_P_GRF 416
|
||||
#define SRST_P_GRF_VCCIO12 417
|
||||
#define SRST_P_GRF_VCCIO34 418
|
||||
#define SRST_P_GRF_VCCIO567 419
|
||||
#define SRST_P_SCR 420
|
||||
#define SRST_P_WDT_NS 421
|
||||
#define SRST_T_WDT_NS 422
|
||||
#define SRST_P_DFT2APB 423
|
||||
#define SRST_A_MCU 426
|
||||
#define SRST_P_INTMUX 427
|
||||
#define SRST_P_MAILBOX 428
|
||||
|
||||
/* cru_softrst_con27 */
|
||||
#define SRST_A_TOP_HIGH_NIU 432
|
||||
#define SRST_A_TOP_LOW_NIU 433
|
||||
#define SRST_H_TOP_NIU 434
|
||||
#define SRST_P_TOP_NIU 435
|
||||
#define SRST_P_TOP_CRU 438
|
||||
#define SRST_P_DDRPHY 439
|
||||
#define SRST_DDRPHY 440
|
||||
#define SRST_P_MIPICSIPHY 442
|
||||
#define SRST_P_MIPIDSIPHY0 443
|
||||
#define SRST_P_MIPIDSIPHY1 444
|
||||
#define SRST_P_PCIE30PHY 445
|
||||
#define SRST_PCIE30PHY 446
|
||||
#define SRST_P_PCIE30PHY_GRF 447
|
||||
|
||||
/* cru_softrst_con28 */
|
||||
#define SRST_P_APB2ASB_LEFT 448
|
||||
#define SRST_P_APB2ASB_BOTTOM 449
|
||||
#define SRST_P_ASB2APB_LEFT 450
|
||||
#define SRST_P_ASB2APB_BOTTOM 451
|
||||
#define SRST_P_PIPEPHY0 452
|
||||
#define SRST_PIPEPHY0 453
|
||||
#define SRST_P_PIPEPHY1 454
|
||||
#define SRST_PIPEPHY1 455
|
||||
#define SRST_P_PIPEPHY2 456
|
||||
#define SRST_PIPEPHY2 457
|
||||
#define SRST_P_USB2PHY0_GRF 458
|
||||
#define SRST_P_USB2PHY1_GRF 459
|
||||
#define SRST_P_CPU_BOOST 460
|
||||
#define SRST_CPU_BOOST 461
|
||||
#define SRST_P_OTPPHY 462
|
||||
#define SRST_OTPPHY 463
|
||||
|
||||
/* cru_softrst_con29 */
|
||||
#define SRST_USB2PHY0_POR 464
|
||||
#define SRST_USB2PHY0_USB3OTG0 465
|
||||
#define SRST_USB2PHY0_USB3OTG1 466
|
||||
#define SRST_USB2PHY1_POR 467
|
||||
#define SRST_USB2PHY1_USB2HOST0 468
|
||||
#define SRST_USB2PHY1_USB2HOST1 469
|
||||
#define SRST_P_EDPPHY_GRF 470
|
||||
#define SRST_TSADCPHY 471
|
||||
#define SRST_GMAC0_DELAYLINE 472
|
||||
#define SRST_GMAC1_DELAYLINE 473
|
||||
#define SRST_OTPC_ARB 474
|
||||
#define SRST_P_PIPEPHY0_GRF 475
|
||||
#define SRST_P_PIPEPHY1_GRF 476
|
||||
#define SRST_P_PIPEPHY2_GRF 477
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user