forked from Minki/linux
ARM: davinci: da850: add ECAP & EHRPWM clock nodes
Add ECAP and EHRPWM module clock nodes. Also add a clock node for TBCLK for EHRWPM. Signed-off-by: Philip Avinash <avinashphilip@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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c6007ffe84
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@ -383,6 +383,49 @@ static struct clk dsp_clk = {
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.flags = PSC_LRST | PSC_FORCE,
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.flags = PSC_LRST | PSC_FORCE,
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};
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};
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static struct clk ehrpwm_clk = {
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.name = "ehrpwm",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC1_PWM,
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.gpsc = 1,
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.flags = DA850_CLK_ASYNC3,
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};
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#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
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static void ehrpwm_tblck_enable(struct clk *clk)
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{
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u32 val;
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
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val |= DA8XX_EHRPWM_TBCLKSYNC;
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writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
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}
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static void ehrpwm_tblck_disable(struct clk *clk)
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{
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u32 val;
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
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val &= ~DA8XX_EHRPWM_TBCLKSYNC;
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writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
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}
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static struct clk ehrpwm_tbclk = {
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.name = "ehrpwm_tbclk",
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.parent = &ehrpwm_clk,
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.clk_enable = ehrpwm_tblck_enable,
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.clk_disable = ehrpwm_tblck_disable,
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};
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static struct clk ecap_clk = {
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.name = "ecap",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC1_ECAP,
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.gpsc = 1,
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.flags = DA850_CLK_ASYNC3,
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};
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static struct clk_lookup da850_clks[] = {
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static struct clk_lookup da850_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll0", &pll0_clk),
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CLK(NULL, "pll0", &pll0_clk),
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@ -430,6 +473,9 @@ static struct clk_lookup da850_clks[] = {
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CLK("vpif", NULL, &vpif_clk),
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CLK("vpif", NULL, &vpif_clk),
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CLK("ahci", NULL, &sata_clk),
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CLK("ahci", NULL, &sata_clk),
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CLK("davinci-rproc.0", NULL, &dsp_clk),
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CLK("davinci-rproc.0", NULL, &dsp_clk),
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CLK("ehrpwm", "fck", &ehrpwm_clk),
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CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
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CLK("ecap", "fck", &ecap_clk),
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CLK(NULL, NULL, NULL),
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CLK(NULL, NULL, NULL),
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};
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};
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@ -55,6 +55,7 @@ extern unsigned int da850_max_speed;
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#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
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#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
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#define DA8XX_JTAG_ID_REG 0x18
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#define DA8XX_JTAG_ID_REG 0x18
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#define DA8XX_CFGCHIP0_REG 0x17c
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#define DA8XX_CFGCHIP0_REG 0x17c
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#define DA8XX_CFGCHIP1_REG 0x180
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#define DA8XX_CFGCHIP2_REG 0x184
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#define DA8XX_CFGCHIP2_REG 0x184
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#define DA8XX_CFGCHIP3_REG 0x188
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#define DA8XX_CFGCHIP3_REG 0x188
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