drm/msm/dsi/phy: fix 7nm v4.0 settings for C-PHY mode
The dsi_7nm_phy_enable() disagrees with downstream for
glbl_str_swi_cal_sel_ctrl and glbl_hstx_str_ctrl_0 values. Update
programmed settings to match downstream driver. To remove the
possibility for such errors in future drop less_than_1500_mhz
assignment and specify settings explicitly.
Fixes: 5ac178381d
("drm/msm/dsi: support CPHY mode for 7nm pll/phy")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Link: https://lore.kernel.org/r/20220217000837.435340-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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@ -864,20 +864,26 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
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/* Alter PHY configurations if data rate less than 1.5GHZ*/
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less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
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/* For C-PHY, no low power settings for lower clk rate */
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if (phy->cphy_mode)
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less_than_1500_mhz = false;
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if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
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vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
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glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
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glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
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if (phy->cphy_mode) {
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glbl_rescode_top_ctrl = 0x00;
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glbl_rescode_bot_ctrl = 0x3c;
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} else {
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glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
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glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
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}
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glbl_str_swi_cal_sel_ctrl = 0x00;
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glbl_hstx_str_ctrl_0 = 0x88;
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} else {
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vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
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glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
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glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
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if (phy->cphy_mode) {
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glbl_str_swi_cal_sel_ctrl = 0x03;
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glbl_hstx_str_ctrl_0 = 0x66;
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} else {
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glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
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glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
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}
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glbl_rescode_top_ctrl = 0x03;
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glbl_rescode_bot_ctrl = 0x3c;
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}
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