x86: apic - use pr_ macros for logging
Impact: cleanup It saves us some source lines and shift the code a bit righter. And a multiline comment style is fixed too :-) Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Acked-by: "Maciej W. Rozycki" <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -559,13 +559,13 @@ static int __init calibrate_by_pmtimer(long deltapm, long *delta)
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} else {
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res = (((u64)deltapm) * mult) >> 22;
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do_div(res, 1000000);
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printk(KERN_WARNING "APIC calibration not consistent "
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pr_warning("APIC calibration not consistent "
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"with PM Timer: %ldms instead of 100ms\n",
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(long)res);
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/* Correct the lapic counter value */
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res = (((u64)(*delta)) * pm_100ms);
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do_div(res, deltapm);
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printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
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pr_info("APIC delta adjusted to PM-Timer: "
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"%lu (%ld)\n", (unsigned long)res, *delta);
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*delta = (long)res;
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}
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@ -645,8 +645,7 @@ static int __init calibrate_APIC_clock(void)
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*/
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if (calibration_result < (1000000 / HZ)) {
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local_irq_enable();
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printk(KERN_WARNING
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"APIC frequency too slow, disabling apic timer\n");
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pr_warning("APIC frequency too slow, disabling apic timer\n");
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return -1;
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}
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@ -688,8 +687,7 @@ static int __init calibrate_APIC_clock(void)
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local_irq_enable();
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if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
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printk(KERN_WARNING
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"APIC timer disabled due to verification failure.\n");
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pr_warning("APIC timer disabled due to verification failure.\n");
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return -1;
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}
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@ -710,7 +708,7 @@ void __init setup_boot_APIC_clock(void)
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* broadcast mechanism is used. On UP systems simply ignore it.
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*/
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if (disable_apic_timer) {
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printk(KERN_INFO "Disabling APIC timer\n");
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pr_info("Disabling APIC timer\n");
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/* No broadcast on UP ! */
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if (num_possible_cpus() > 1) {
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lapic_clockevent.mult = 1;
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@ -737,7 +735,7 @@ void __init setup_boot_APIC_clock(void)
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if (nmi_watchdog != NMI_IO_APIC)
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lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
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else
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printk(KERN_WARNING "APIC timer registered as dummy,"
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pr_warning("APIC timer registered as dummy,"
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" due to nmi_watchdog=%d!\n", nmi_watchdog);
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/* Setup the lapic or request the broadcast */
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@ -769,8 +767,7 @@ static void local_apic_timer_interrupt(void)
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* spurious.
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*/
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if (!evt->event_handler) {
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printk(KERN_WARNING
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"Spurious LAPIC timer interrupt on cpu %d\n", cpu);
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pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
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/* Switch it off */
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lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
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return;
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@ -1089,7 +1086,7 @@ static void __cpuinit lapic_setup_esr(void)
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unsigned int oldvalue, value, maxlvt;
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if (!lapic_is_integrated()) {
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printk(KERN_INFO "No ESR for 82489DX.\n");
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pr_info("No ESR for 82489DX.\n");
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return;
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}
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@ -1100,7 +1097,7 @@ static void __cpuinit lapic_setup_esr(void)
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* ESR disabled - we can't do anything useful with the
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* errors anyway - mbligh
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*/
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printk(KERN_INFO "Leaving ESR disabled.\n");
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pr_info("Leaving ESR disabled.\n");
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return;
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}
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@ -1294,7 +1291,7 @@ void check_x2apic(void)
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rdmsr(MSR_IA32_APICBASE, msr, msr2);
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if (msr & X2APIC_ENABLE) {
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printk("x2apic enabled by BIOS, switching to x2apic ops\n");
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pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
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x2apic_preenabled = x2apic = 1;
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apic_ops = &x2apic_ops;
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}
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@ -1306,7 +1303,7 @@ void enable_x2apic(void)
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rdmsr(MSR_IA32_APICBASE, msr, msr2);
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if (!(msr & X2APIC_ENABLE)) {
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printk("Enabling x2apic\n");
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pr_info("Enabling x2apic\n");
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wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
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}
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}
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@ -1321,9 +1318,8 @@ void enable_IR_x2apic(void)
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return;
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if (!x2apic_preenabled && disable_x2apic) {
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printk(KERN_INFO
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"Skipped enabling x2apic and Interrupt-remapping "
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"because of nox2apic\n");
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pr_info("Skipped enabling x2apic and Interrupt-remapping "
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"because of nox2apic\n");
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return;
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}
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@ -1331,22 +1327,19 @@ void enable_IR_x2apic(void)
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panic("Bios already enabled x2apic, can't enforce nox2apic");
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if (!x2apic_preenabled && skip_ioapic_setup) {
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printk(KERN_INFO
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"Skipped enabling x2apic and Interrupt-remapping "
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"because of skipping io-apic setup\n");
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pr_info("Skipped enabling x2apic and Interrupt-remapping "
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"because of skipping io-apic setup\n");
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return;
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}
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ret = dmar_table_init();
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if (ret) {
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printk(KERN_INFO
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"dmar_table_init() failed with %d:\n", ret);
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pr_info("dmar_table_init() failed with %d:\n", ret);
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if (x2apic_preenabled)
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panic("x2apic enabled by bios. But IR enabling failed");
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else
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printk(KERN_INFO
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"Not enabling x2apic,Intr-remapping\n");
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pr_info("Not enabling x2apic,Intr-remapping\n");
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return;
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}
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@ -1355,7 +1348,7 @@ void enable_IR_x2apic(void)
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ret = save_mask_IO_APIC_setup();
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if (ret) {
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printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret);
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pr_info("Saving IO-APIC state failed: %d\n", ret);
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goto end;
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}
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@ -1390,14 +1383,11 @@ end:
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if (!ret) {
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if (!x2apic_preenabled)
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printk(KERN_INFO
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"Enabled x2apic and interrupt-remapping\n");
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pr_info("Enabled x2apic and interrupt-remapping\n");
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else
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printk(KERN_INFO
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"Enabled Interrupt-remapping\n");
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pr_info("Enabled Interrupt-remapping\n");
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} else
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printk(KERN_ERR
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"Failed to enable Interrupt-remapping and x2apic\n");
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pr_err("Failed to enable Interrupt-remapping and x2apic\n");
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#else
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if (!cpu_has_x2apic)
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return;
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@ -1406,8 +1396,8 @@ end:
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panic("x2apic enabled prior OS handover,"
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" enable CONFIG_INTR_REMAP");
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printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
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" and x2apic\n");
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pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
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" and x2apic\n");
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#endif
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return;
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@ -1424,7 +1414,7 @@ end:
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static int __init detect_init_APIC(void)
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{
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if (!cpu_has_apic) {
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printk(KERN_INFO "No local APIC present\n");
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pr_info("No local APIC present\n");
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return -1;
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}
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@ -1465,8 +1455,8 @@ static int __init detect_init_APIC(void)
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* "lapic" specified.
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*/
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if (!force_enable_local_apic) {
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printk(KERN_INFO "Local APIC disabled by BIOS -- "
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"you can enable it with \"lapic\"\n");
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pr_info("Local APIC disabled by BIOS -- "
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"you can enable it with \"lapic\"\n");
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return -1;
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}
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/*
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@ -1476,8 +1466,7 @@ static int __init detect_init_APIC(void)
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*/
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rdmsr(MSR_IA32_APICBASE, l, h);
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if (!(l & MSR_IA32_APICBASE_ENABLE)) {
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printk(KERN_INFO
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"Local APIC disabled by BIOS -- reenabling.\n");
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pr_info("Local APIC disabled by BIOS -- reenabling.\n");
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l &= ~MSR_IA32_APICBASE_BASE;
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l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
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wrmsr(MSR_IA32_APICBASE, l, h);
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@ -1490,7 +1479,7 @@ static int __init detect_init_APIC(void)
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*/
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features = cpuid_edx(1);
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if (!(features & (1 << X86_FEATURE_APIC))) {
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printk(KERN_WARNING "Could not enable APIC!\n");
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pr_warning("Could not enable APIC!\n");
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return -1;
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}
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set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
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@ -1501,14 +1490,14 @@ static int __init detect_init_APIC(void)
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if (l & MSR_IA32_APICBASE_ENABLE)
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mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
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printk(KERN_INFO "Found and enabled local APIC!\n");
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pr_info("Found and enabled local APIC!\n");
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apic_pm_activate();
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return 0;
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no_apic:
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printk(KERN_INFO "No local APIC present or hardware disabled\n");
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pr_info("No local APIC present or hardware disabled\n");
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return -1;
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}
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#endif
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@ -1584,12 +1573,12 @@ int __init APIC_init_uniprocessor(void)
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{
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#ifdef CONFIG_X86_64
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if (disable_apic) {
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printk(KERN_INFO "Apic disabled\n");
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pr_info("Apic disabled\n");
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return -1;
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}
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if (!cpu_has_apic) {
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disable_apic = 1;
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printk(KERN_INFO "Apic disabled by BIOS\n");
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pr_info("Apic disabled by BIOS\n");
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return -1;
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}
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#else
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@ -1601,8 +1590,8 @@ int __init APIC_init_uniprocessor(void)
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*/
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if (!cpu_has_apic &&
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APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
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printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n",
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boot_cpu_physical_apicid);
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pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
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boot_cpu_physical_apicid);
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clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
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return -1;
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}
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@ -1695,8 +1684,8 @@ void smp_spurious_interrupt(struct pt_regs *regs)
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add_pda(irq_spurious_count, 1);
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#else
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/* see sw-dev-man vol 3, chapter 7.4.13.5 */
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printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
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"should never happen.\n", smp_processor_id());
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pr_info("spurious APIC interrupt on CPU#%d, "
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"should never happen.\n", smp_processor_id());
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__get_cpu_var(irq_stat).irq_spurious_count++;
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#endif
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irq_exit();
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@ -1720,17 +1709,18 @@ void smp_error_interrupt(struct pt_regs *regs)
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ack_APIC_irq();
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atomic_inc(&irq_err_count);
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/* Here is what the APIC error bits mean:
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0: Send CS error
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1: Receive CS error
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2: Send accept error
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3: Receive accept error
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4: Reserved
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5: Send illegal vector
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6: Received illegal vector
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7: Illegal register address
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*/
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printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
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/*
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* Here is what the APIC error bits mean:
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* 0: Send CS error
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* 1: Receive CS error
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* 2: Send accept error
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* 3: Receive accept error
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* 4: Reserved
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* 5: Send illegal vector
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* 6: Received illegal vector
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* 7: Illegal register address
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*/
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pr_debug("APIC error on CPU%d: %02x(%02x)\n",
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smp_processor_id(), v , v1);
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irq_exit();
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}
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@ -1834,15 +1824,15 @@ void __cpuinit generic_processor_info(int apicid, int version)
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* Validate version
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*/
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if (version == 0x0) {
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printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
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"fixing up to 0x10. (tell your hw vendor)\n",
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version);
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pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
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"fixing up to 0x10. (tell your hw vendor)\n",
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version);
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version = 0x10;
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}
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apic_version[apicid] = version;
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if (num_processors >= NR_CPUS) {
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printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
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pr_warning("WARNING: NR_CPUS limit of %i reached."
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" Processor ignored.\n", NR_CPUS);
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return;
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}
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@ -2205,7 +2195,7 @@ static int __init apic_set_verbosity(char *arg)
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else if (strcmp("verbose", arg) == 0)
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apic_verbosity = APIC_VERBOSE;
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else {
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printk(KERN_WARNING "APIC Verbosity level %s not recognised"
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pr_warning("APIC Verbosity level %s not recognised"
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" use apic=verbose or apic=debug\n", arg);
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return -EINVAL;
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}
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