Merge branch 'remotes/lorenzo/pci/dwc'
- Simplify computation of msix_tbl (Jiri Slaby)
- Make hisi_pcie_platform_ops static (Zou Wei)
- Warn about resources above 4G (Alan Mikhak)
- Make intel_pcie_cpu_addr() static (Jason Yan)
- Use devm_platform_ioremap_resource_byname() to simplify code and
improve error checking (Wei Yongjun)
- Fix inner MSI IRQ domain registration so it doesn't confuse debugfs
(Marc Zyngier)
- Don't use FAST_LINK_MODE on meson (Marc Zyngier)
- Add Socionext UniPhier Pro5 PCIe endpoint controller driver and DT
description (Kunihiko Hayashi)
* remotes/lorenzo/pci/dwc:
PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver
dt-bindings: PCI: Add UniPhier PCIe endpoint controller description
PCI: dwc: Use private data pointer of "struct irq_domain" to get pcie_port
PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link
PCI: dwc: Fix inner MSI IRQ domain registration
PCI: dwc: pci-dra7xx: Use devm_platform_ioremap_resource_byname()
PCI: dwc: intel: Make intel_pcie_cpu_addr() static
PCI: dwc: Program outbound ATU upper limit register
PCI: dwc: Make hisi_pcie_platform_ops static
PCI: dwc: Clean up computing of msix_tbl
This commit is contained in:
Bjorn Helgaas
commit
b9fcf4910b
@ -0,0 +1,92 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Socionext UniPhier PCIe endpoint controller
|
||||
|
||||
description: |
|
||||
UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
|
||||
PCI core. It shares common features with the PCIe DesignWare core and
|
||||
inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/designware-pcie.txt.
|
||||
|
||||
maintainers:
|
||||
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "pci-ep.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: socionext,uniphier-pro5-pcie-ep
|
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|
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reg:
|
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maxItems: 4
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|
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reg-names:
|
||||
items:
|
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- const: dbi
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- const: dbi2
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- const: link
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- const: addr_space
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|
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clocks:
|
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maxItems: 2
|
||||
|
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clock-names:
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items:
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- const: gio
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- const: link
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|
||||
resets:
|
||||
maxItems: 2
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||||
|
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reset-names:
|
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items:
|
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- const: gio
|
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- const: link
|
||||
|
||||
num-ib-windows:
|
||||
const: 16
|
||||
|
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num-ob-windows:
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const: 16
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|
||||
num-lanes: true
|
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|
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phys:
|
||||
maxItems: 1
|
||||
|
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phy-names:
|
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const: pcie-phy
|
||||
|
||||
required:
|
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- compatible
|
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- reg
|
||||
- reg-names
|
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- clocks
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- clock-names
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- resets
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- reset-names
|
||||
|
||||
additionalProperties: false
|
||||
|
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examples:
|
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- |
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pcie_ep: pcie-ep@66000000 {
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compatible = "socionext,uniphier-pro5-pcie-ep";
|
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reg-names = "dbi", "dbi2", "link", "addr_space";
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reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
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<0x66010000 0x10000>, <0x67000000 0x400000>;
|
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clock-names = "gio", "link";
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clocks = <&sys_clk 12>, <&sys_clk 24>;
|
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reset-names = "gio", "link";
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resets = <&sys_rst 12>, <&sys_rst 24>;
|
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num-ib-windows = <16>;
|
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num-ob-windows = <16>;
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num-lanes = <4>;
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phy-names = "pcie-phy";
|
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phys = <&pcie_phy>;
|
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};
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@ -13142,8 +13142,8 @@ PCIE DRIVER FOR SOCIONEXT UNIPHIER
|
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M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
|
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L: linux-pci@vger.kernel.org
|
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S: Maintained
|
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F: Documentation/devicetree/bindings/pci/uniphier-pcie.txt
|
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F: drivers/pci/controller/dwc/pcie-uniphier.c
|
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F: Documentation/devicetree/bindings/pci/uniphier-pcie*
|
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F: drivers/pci/controller/dwc/pcie-uniphier*
|
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|
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PCIE DRIVER FOR ST SPEAR13XX
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M: Pratyush Anand <pratyush.anand@gmail.com>
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@ -280,15 +280,25 @@ config PCIE_TEGRA194_EP
|
||||
selected. This uses the DesignWare core.
|
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|
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config PCIE_UNIPHIER
|
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bool "Socionext UniPhier PCIe controllers"
|
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bool "Socionext UniPhier PCIe host controllers"
|
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depends on ARCH_UNIPHIER || COMPILE_TEST
|
||||
depends on OF && HAS_IOMEM
|
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depends on PCI_MSI_IRQ_DOMAIN
|
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select PCIE_DW_HOST
|
||||
help
|
||||
Say Y here if you want PCIe controller support on UniPhier SoCs.
|
||||
Say Y here if you want PCIe host controller support on UniPhier SoCs.
|
||||
This driver supports LD20 and PXs3 SoCs.
|
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|
||||
config PCIE_UNIPHIER_EP
|
||||
bool "Socionext UniPhier PCIe endpoint controllers"
|
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depends on ARCH_UNIPHIER || COMPILE_TEST
|
||||
depends on OF && HAS_IOMEM
|
||||
depends on PCI_ENDPOINT
|
||||
select PCIE_DW_EP
|
||||
help
|
||||
Say Y here if you want PCIe endpoint controller support on
|
||||
UniPhier SoCs. This driver supports Pro5 SoC.
|
||||
|
||||
config PCIE_AL
|
||||
bool "Amazon Annapurna Labs PCIe controller"
|
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depends on OF && (ARM64 || COMPILE_TEST)
|
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|
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@ -19,6 +19,7 @@ obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
|
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obj-$(CONFIG_PCI_MESON) += pci-meson.o
|
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obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
|
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obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
|
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obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
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|
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# The following drivers are for devices that use the generic ACPI
|
||||
# pci_root.c driver but don't support standard ECAM config access.
|
||||
|
||||
@ -840,7 +840,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
|
||||
struct phy **phy;
|
||||
struct device_link **link;
|
||||
void __iomem *base;
|
||||
struct resource *res;
|
||||
struct dw_pcie *pci;
|
||||
struct dra7xx_pcie *dra7xx;
|
||||
struct device *dev = &pdev->dev;
|
||||
@ -877,10 +876,9 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
|
||||
return irq;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
|
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base = devm_ioremap(dev, res->start, resource_size(res));
|
||||
if (!base)
|
||||
return -ENOMEM;
|
||||
base = devm_platform_ioremap_resource_byname(pdev, "ti_conf");
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
phy_count = of_property_count_strings(np, "phy-names");
|
||||
if (phy_count < 0) {
|
||||
|
||||
@ -289,11 +289,11 @@ static void meson_pcie_init_dw(struct meson_pcie *mp)
|
||||
meson_cfg_writel(mp, val, PCIE_CFG0);
|
||||
|
||||
val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
|
||||
val &= ~LINK_CAPABLE_MASK;
|
||||
val &= ~(LINK_CAPABLE_MASK | FAST_LINK_MODE);
|
||||
meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
|
||||
|
||||
val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
|
||||
val |= LINK_CAPABLE_X1 | FAST_LINK_MODE;
|
||||
val |= LINK_CAPABLE_X1;
|
||||
meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
|
||||
|
||||
val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
|
||||
|
||||
@ -433,7 +433,6 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
struct pci_epf_msix_tbl *msix_tbl;
|
||||
struct pci_epc *epc = ep->epc;
|
||||
struct pci_epf_bar *epf_bar;
|
||||
u32 reg, msg_data, vec_ctrl;
|
||||
unsigned int aligned_offset;
|
||||
u32 tbl_offset;
|
||||
@ -446,10 +445,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
|
||||
tbl_offset &= PCI_MSIX_TABLE_OFFSET;
|
||||
|
||||
epf_bar = ep->epf_bar[bir];
|
||||
msix_tbl = epf_bar->addr;
|
||||
msix_tbl = (struct pci_epf_msix_tbl *)((char *)msix_tbl + tbl_offset);
|
||||
|
||||
msix_tbl = ep->epf_bar[bir]->addr + tbl_offset;
|
||||
msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;
|
||||
msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
|
||||
vec_ctrl = msix_tbl[(interrupt_num - 1)].vector_ctrl;
|
||||
|
||||
@ -236,7 +236,7 @@ static void dw_pcie_irq_domain_free(struct irq_domain *domain,
|
||||
unsigned int virq, unsigned int nr_irqs)
|
||||
{
|
||||
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
||||
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
|
||||
struct pcie_port *pp = domain->host_data;
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&pp->lock, flags);
|
||||
@ -264,6 +264,8 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
|
||||
|
||||
pp->msi_domain = pci_msi_create_irq_domain(fwnode,
|
||||
&dw_pcie_msi_domain_info,
|
||||
pp->irq_domain);
|
||||
|
||||
@ -244,13 +244,16 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
|
||||
u64 pci_addr, u32 size)
|
||||
{
|
||||
u32 retries, val;
|
||||
u64 limit_addr = cpu_addr + size - 1;
|
||||
|
||||
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
|
||||
lower_32_bits(cpu_addr));
|
||||
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
|
||||
upper_32_bits(cpu_addr));
|
||||
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
|
||||
lower_32_bits(cpu_addr + size - 1));
|
||||
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
|
||||
lower_32_bits(limit_addr));
|
||||
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
|
||||
upper_32_bits(limit_addr));
|
||||
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
|
||||
lower_32_bits(pci_addr));
|
||||
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
|
||||
|
||||
@ -112,9 +112,10 @@
|
||||
#define PCIE_ATU_UNR_REGION_CTRL2 0x04
|
||||
#define PCIE_ATU_UNR_LOWER_BASE 0x08
|
||||
#define PCIE_ATU_UNR_UPPER_BASE 0x0C
|
||||
#define PCIE_ATU_UNR_LIMIT 0x10
|
||||
#define PCIE_ATU_UNR_LOWER_LIMIT 0x10
|
||||
#define PCIE_ATU_UNR_LOWER_TARGET 0x14
|
||||
#define PCIE_ATU_UNR_UPPER_TARGET 0x18
|
||||
#define PCIE_ATU_UNR_UPPER_LIMIT 0x20
|
||||
|
||||
/*
|
||||
* The default address offset between dbi_base and atu_base. Root controller
|
||||
|
||||
@ -362,7 +362,7 @@ static int hisi_pcie_platform_init(struct pci_config_window *cfg)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct pci_ecam_ops hisi_pcie_platform_ops = {
|
||||
static struct pci_ecam_ops hisi_pcie_platform_ops = {
|
||||
.bus_shift = 20,
|
||||
.init = hisi_pcie_platform_init,
|
||||
.pci_ops = {
|
||||
|
||||
@ -453,7 +453,7 @@ static int intel_pcie_msi_init(struct pcie_port *pp)
|
||||
return 0;
|
||||
}
|
||||
|
||||
u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr)
|
||||
static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr)
|
||||
{
|
||||
return cpu_addr + BUS_IATU_OFFSET;
|
||||
}
|
||||
|
||||
383
drivers/pci/controller/dwc/pcie-uniphier-ep.c
Normal file
383
drivers/pci/controller/dwc/pcie-uniphier-ep.c
Normal file
@ -0,0 +1,383 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* PCIe endpoint controller driver for UniPhier SoCs
|
||||
* Copyright 2018 Socionext Inc.
|
||||
* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
#include "pcie-designware.h"
|
||||
|
||||
/* Link Glue registers */
|
||||
#define PCL_RSTCTRL0 0x0010
|
||||
#define PCL_RSTCTRL_AXI_REG BIT(3)
|
||||
#define PCL_RSTCTRL_AXI_SLAVE BIT(2)
|
||||
#define PCL_RSTCTRL_AXI_MASTER BIT(1)
|
||||
#define PCL_RSTCTRL_PIPE3 BIT(0)
|
||||
|
||||
#define PCL_RSTCTRL1 0x0020
|
||||
#define PCL_RSTCTRL_PERST BIT(0)
|
||||
|
||||
#define PCL_RSTCTRL2 0x0024
|
||||
#define PCL_RSTCTRL_PHY_RESET BIT(0)
|
||||
|
||||
#define PCL_MODE 0x8000
|
||||
#define PCL_MODE_REGEN BIT(8)
|
||||
#define PCL_MODE_REGVAL BIT(0)
|
||||
|
||||
#define PCL_APP_CLK_CTRL 0x8004
|
||||
#define PCL_APP_CLK_REQ BIT(0)
|
||||
|
||||
#define PCL_APP_READY_CTRL 0x8008
|
||||
#define PCL_APP_LTSSM_ENABLE BIT(0)
|
||||
|
||||
#define PCL_APP_MSI0 0x8040
|
||||
#define PCL_APP_VEN_MSI_TC_MASK GENMASK(10, 8)
|
||||
#define PCL_APP_VEN_MSI_VECTOR_MASK GENMASK(4, 0)
|
||||
|
||||
#define PCL_APP_MSI1 0x8044
|
||||
#define PCL_APP_MSI_REQ BIT(0)
|
||||
|
||||
#define PCL_APP_INTX 0x8074
|
||||
#define PCL_APP_INTX_SYS_INT BIT(0)
|
||||
|
||||
/* assertion time of INTx in usec */
|
||||
#define PCL_INTX_WIDTH_USEC 30
|
||||
|
||||
struct uniphier_pcie_ep_priv {
|
||||
void __iomem *base;
|
||||
struct dw_pcie pci;
|
||||
struct clk *clk, *clk_gio;
|
||||
struct reset_control *rst, *rst_gio;
|
||||
struct phy *phy;
|
||||
const struct pci_epc_features *features;
|
||||
};
|
||||
|
||||
#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
|
||||
|
||||
static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_ep_priv *priv,
|
||||
bool enable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(priv->base + PCL_APP_READY_CTRL);
|
||||
if (enable)
|
||||
val |= PCL_APP_LTSSM_ENABLE;
|
||||
else
|
||||
val &= ~PCL_APP_LTSSM_ENABLE;
|
||||
writel(val, priv->base + PCL_APP_READY_CTRL);
|
||||
}
|
||||
|
||||
static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
|
||||
bool assert)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(priv->base + PCL_RSTCTRL2);
|
||||
if (assert)
|
||||
val |= PCL_RSTCTRL_PHY_RESET;
|
||||
else
|
||||
val &= ~PCL_RSTCTRL_PHY_RESET;
|
||||
writel(val, priv->base + PCL_RSTCTRL2);
|
||||
}
|
||||
|
||||
static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* set EP mode */
|
||||
val = readl(priv->base + PCL_MODE);
|
||||
val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
|
||||
writel(val, priv->base + PCL_MODE);
|
||||
|
||||
/* clock request */
|
||||
val = readl(priv->base + PCL_APP_CLK_CTRL);
|
||||
val &= ~PCL_APP_CLK_REQ;
|
||||
writel(val, priv->base + PCL_APP_CLK_CTRL);
|
||||
|
||||
/* deassert PIPE3 and AXI reset */
|
||||
val = readl(priv->base + PCL_RSTCTRL0);
|
||||
val |= PCL_RSTCTRL_AXI_REG | PCL_RSTCTRL_AXI_SLAVE
|
||||
| PCL_RSTCTRL_AXI_MASTER | PCL_RSTCTRL_PIPE3;
|
||||
writel(val, priv->base + PCL_RSTCTRL0);
|
||||
|
||||
uniphier_pcie_ltssm_enable(priv, false);
|
||||
|
||||
msleep(100);
|
||||
}
|
||||
|
||||
static int uniphier_pcie_start_link(struct dw_pcie *pci)
|
||||
{
|
||||
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
|
||||
|
||||
uniphier_pcie_ltssm_enable(priv, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void uniphier_pcie_stop_link(struct dw_pcie *pci)
|
||||
{
|
||||
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
|
||||
|
||||
uniphier_pcie_ltssm_enable(priv, false);
|
||||
}
|
||||
|
||||
static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
enum pci_barno bar;
|
||||
|
||||
for (bar = BAR_0; bar <= BAR_5; bar++)
|
||||
dw_pcie_ep_reset_bar(pci, bar);
|
||||
}
|
||||
|
||||
static int uniphier_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* This makes pulse signal to send INTx to the RC, so this should
|
||||
* be cleared as soon as possible. This sequence is covered with
|
||||
* mutex in pci_epc_raise_irq().
|
||||
*/
|
||||
/* assert INTx */
|
||||
val = readl(priv->base + PCL_APP_INTX);
|
||||
val |= PCL_APP_INTX_SYS_INT;
|
||||
writel(val, priv->base + PCL_APP_INTX);
|
||||
|
||||
udelay(PCL_INTX_WIDTH_USEC);
|
||||
|
||||
/* deassert INTx */
|
||||
val &= ~PCL_APP_INTX_SYS_INT;
|
||||
writel(val, priv->base + PCL_APP_INTX);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
|
||||
u8 func_no, u16 interrupt_num)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
|
||||
u32 val;
|
||||
|
||||
val = FIELD_PREP(PCL_APP_VEN_MSI_TC_MASK, func_no)
|
||||
| FIELD_PREP(PCL_APP_VEN_MSI_VECTOR_MASK, interrupt_num - 1);
|
||||
writel(val, priv->base + PCL_APP_MSI0);
|
||||
|
||||
val = readl(priv->base + PCL_APP_MSI1);
|
||||
val |= PCL_APP_MSI_REQ;
|
||||
writel(val, priv->base + PCL_APP_MSI1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
enum pci_epc_irq_type type,
|
||||
u16 interrupt_num)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
|
||||
switch (type) {
|
||||
case PCI_EPC_IRQ_LEGACY:
|
||||
return uniphier_pcie_ep_raise_legacy_irq(ep);
|
||||
case PCI_EPC_IRQ_MSI:
|
||||
return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
|
||||
interrupt_num);
|
||||
default:
|
||||
dev_err(pci->dev, "UNKNOWN IRQ type (%d)\n", type);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pci_epc_features*
|
||||
uniphier_pcie_get_features(struct dw_pcie_ep *ep)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
|
||||
|
||||
return priv->features;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
|
||||
.ep_init = uniphier_pcie_ep_init,
|
||||
.raise_irq = uniphier_pcie_ep_raise_irq,
|
||||
.get_features = uniphier_pcie_get_features,
|
||||
};
|
||||
|
||||
static int uniphier_add_pcie_ep(struct uniphier_pcie_ep_priv *priv,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct dw_pcie *pci = &priv->pci;
|
||||
struct dw_pcie_ep *ep = &pci->ep;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
ep->ops = &uniphier_pcie_ep_ops;
|
||||
|
||||
pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
|
||||
if (IS_ERR(pci->dbi_base2))
|
||||
return PTR_ERR(pci->dbi_base2);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
|
||||
if (!res)
|
||||
return -EINVAL;
|
||||
|
||||
ep->phys_base = res->start;
|
||||
ep->addr_size = resource_size(res);
|
||||
|
||||
ret = dw_pcie_ep_init(ep);
|
||||
if (ret)
|
||||
dev_err(dev, "Failed to initialize endpoint (%d)\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(priv->clk_gio);
|
||||
if (ret)
|
||||
goto out_clk_disable;
|
||||
|
||||
ret = reset_control_deassert(priv->rst);
|
||||
if (ret)
|
||||
goto out_clk_gio_disable;
|
||||
|
||||
ret = reset_control_deassert(priv->rst_gio);
|
||||
if (ret)
|
||||
goto out_rst_assert;
|
||||
|
||||
uniphier_pcie_init_ep(priv);
|
||||
|
||||
uniphier_pcie_phy_reset(priv, true);
|
||||
|
||||
ret = phy_init(priv->phy);
|
||||
if (ret)
|
||||
goto out_rst_gio_assert;
|
||||
|
||||
uniphier_pcie_phy_reset(priv, false);
|
||||
|
||||
return 0;
|
||||
|
||||
out_rst_gio_assert:
|
||||
reset_control_assert(priv->rst_gio);
|
||||
out_rst_assert:
|
||||
reset_control_assert(priv->rst);
|
||||
out_clk_gio_disable:
|
||||
clk_disable_unprepare(priv->clk_gio);
|
||||
out_clk_disable:
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.start_link = uniphier_pcie_start_link,
|
||||
.stop_link = uniphier_pcie_stop_link,
|
||||
};
|
||||
|
||||
static int uniphier_pcie_ep_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct uniphier_pcie_ep_priv *priv;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->features = of_device_get_match_data(dev);
|
||||
if (WARN_ON(!priv->features))
|
||||
return -EINVAL;
|
||||
|
||||
priv->pci.dev = dev;
|
||||
priv->pci.ops = &dw_pcie_ops;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
|
||||
if (IS_ERR(priv->pci.dbi_base))
|
||||
return PTR_ERR(priv->pci.dbi_base);
|
||||
|
||||
priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
priv->clk_gio = devm_clk_get(dev, "gio");
|
||||
if (IS_ERR(priv->clk_gio))
|
||||
return PTR_ERR(priv->clk_gio);
|
||||
|
||||
priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
|
||||
if (IS_ERR(priv->rst_gio))
|
||||
return PTR_ERR(priv->rst_gio);
|
||||
|
||||
priv->clk = devm_clk_get(dev, "link");
|
||||
if (IS_ERR(priv->clk))
|
||||
return PTR_ERR(priv->clk);
|
||||
|
||||
priv->rst = devm_reset_control_get_shared(dev, "link");
|
||||
if (IS_ERR(priv->rst))
|
||||
return PTR_ERR(priv->rst);
|
||||
|
||||
priv->phy = devm_phy_optional_get(dev, "pcie-phy");
|
||||
if (IS_ERR(priv->phy)) {
|
||||
ret = PTR_ERR(priv->phy);
|
||||
dev_err(dev, "Failed to get phy (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
ret = uniphier_pcie_ep_enable(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return uniphier_add_pcie_ep(priv, pdev);
|
||||
}
|
||||
|
||||
static const struct pci_epc_features uniphier_pro5_data = {
|
||||
.linkup_notifier = false,
|
||||
.msi_capable = true,
|
||||
.msix_capable = false,
|
||||
.align = 1 << 16,
|
||||
.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
|
||||
.reserved_bar = BIT(BAR_4),
|
||||
};
|
||||
|
||||
static const struct of_device_id uniphier_pcie_ep_match[] = {
|
||||
{
|
||||
.compatible = "socionext,uniphier-pro5-pcie-ep",
|
||||
.data = &uniphier_pro5_data,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct platform_driver uniphier_pcie_ep_driver = {
|
||||
.probe = uniphier_pcie_ep_probe,
|
||||
.driver = {
|
||||
.name = "uniphier-pcie-ep",
|
||||
.of_match_table = uniphier_pcie_ep_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(uniphier_pcie_ep_driver);
|
||||
Loading…
Reference in New Issue
Block a user