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drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE field

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max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE
field is programmed in units of two entries, but 6 bits is insufficient
to hold value 128/2 = 64, so set this field as 0 which is interpreted by
the hardware as maximum physical fifo size(128).

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jack Xiao 2019-05-28 13:27:11 +08:00 committed by Alex Deucher
parent 3ddec51511
commit b8cb98cd3e
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -1103,7 +1103,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x0;
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
break;