forked from Minki/linux
[BNX2]: Reduce spurious INTA interrupts.
Spurious interrupts are often encountered especially on systems using the 8259 PIC mode. This is because the I/O write to deassert the interrupt is posted and won't get to the chip immediately. As a result, the IRQ may remain asserted after the IRQ handler exits, causing spurious interrupts. Add read back to flush the I/O write to deassert the IRQ immediately. We also store the last_status_idx immediately in the IRQ handler to help detect whether the interrupt is ours or not when the IRQ is entered again before ->poll gets called. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2547,6 +2547,7 @@ bnx2_interrupt(int irq, void *dev_instance)
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{
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struct net_device *dev = dev_instance;
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struct bnx2 *bp = netdev_priv(dev);
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struct status_block *sblk = bp->status_blk;
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/* When using INTx, it is possible for the interrupt to arrive
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* at the CPU before the status block posted prior to the
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@ -2554,7 +2555,7 @@ bnx2_interrupt(int irq, void *dev_instance)
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* When using MSI, the MSI message will always complete after
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* the status block write.
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*/
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if ((bp->status_blk->status_idx == bp->last_status_idx) &&
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if ((sblk->status_idx == bp->last_status_idx) &&
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(REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
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BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
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return IRQ_NONE;
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@ -2563,11 +2564,19 @@ bnx2_interrupt(int irq, void *dev_instance)
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BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
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BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
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/* Read back to deassert IRQ immediately to avoid too many
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* spurious interrupts.
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*/
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REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
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/* Return here if interrupt is shared and is disabled. */
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if (unlikely(atomic_read(&bp->intr_sem) != 0))
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return IRQ_HANDLED;
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netif_rx_schedule(dev);
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if (netif_rx_schedule_prep(dev)) {
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bp->last_status_idx = sblk->status_idx;
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__netif_rx_schedule(dev);
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}
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return IRQ_HANDLED;
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}
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