staging: rtl8192e: Remove unused macros/structures in rtl_core.h
- Removed unused macros/enums/structures - Remove unused fields in r8192_priv Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mateusz Kulikowski
Greg Kroah-Hartman
parent
e6d948a57d
commit
b81b6d2843
@ -68,74 +68,19 @@
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#define DRV_AUTHOR "<wlanfae@realtek.com>"
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#define DRV_VERSION "0014.0401.2010"
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#define IS_HARDWARE_TYPE_819xP(_priv) \
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((((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8190P) || \
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(((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192E))
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#define IS_HARDWARE_TYPE_8192SE(_priv) \
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(((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192SE)
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#define IS_HARDWARE_TYPE_8192CE(_priv) \
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(((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192CE)
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#define IS_HARDWARE_TYPE_8192CU(_priv) \
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(((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192CU)
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#define IS_HARDWARE_TYPE_8192DE(_priv) \
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(((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192DE)
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#define IS_HARDWARE_TYPE_8192DU(_priv) \
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(((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192DU)
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#define RTL_PCI_DEVICE(vend, dev, cfg) \
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.vendor = (vend), .device = (dev), \
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.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
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.driver_data = (kernel_ulong_t)&(cfg)
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#define RTL_MAX_SCAN_SIZE 128
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#define RTL_RATE_MAX 30
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#define TOTAL_CAM_ENTRY 32
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#define CAM_CONTENT_COUNT 8
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#ifndef BIT
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#define BIT(_i) (1<<(_i))
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#endif
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#define IS_ADAPTER_SENDS_BEACON(dev) 0
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#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000
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#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000
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#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000
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#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
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#define HAL_HW_PCI_REVISION_ID_8192CE 0x1
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000
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#define HAL_HW_PCI_REVISION_ID_8192DE 0x0
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#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000
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#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
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#define HAL_HW_PCI_8185_DEVICE_ID 0x8185
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#define HAL_HW_PCI_8188_DEVICE_ID 0x8188
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#define HAL_HW_PCI_8198_DEVICE_ID 0x8198
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#define HAL_HW_PCI_8190_DEVICE_ID 0x8190
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#define HAL_HW_PCI_8192_DEVICE_ID 0x8192
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#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192
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#define HAL_HW_PCI_8174_DEVICE_ID 0x8174
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#define HAL_HW_PCI_8173_DEVICE_ID 0x8173
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#define HAL_HW_PCI_8172_DEVICE_ID 0x8172
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#define HAL_HW_PCI_8171_DEVICE_ID 0x8171
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#define HAL_HW_PCI_0045_DEVICE_ID 0x0045
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#define HAL_HW_PCI_0046_DEVICE_ID 0x0046
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#define HAL_HW_PCI_0044_DEVICE_ID 0x0044
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#define HAL_HW_PCI_0047_DEVICE_ID 0x0047
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#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
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#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
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#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
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#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191
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#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178
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#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177
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#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176
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#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191
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#define HAL_HW_PCI_8192DE_DEVICE_ID 0x092D
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#define HAL_HW_PCI_8192DU_DEVICE_ID 0x092D
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#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
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@ -150,16 +95,12 @@
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(1600 + (MAX_802_11_HEADER_LENGTH + ENCRYPTION_MAX_OVERHEAD) * \
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MAX_FRAGMENT_COUNT)
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#define scrclng 4
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#define DEFAULT_FRAG_THRESHOLD 2342U
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#define MIN_FRAG_THRESHOLD 256U
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#define DEFAULT_BEACONINTERVAL 0x64U
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#define DEFAULT_SSID ""
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#define DEFAULT_RETRY_RTS 7
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#define DEFAULT_RETRY_DATA 7
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#define PRISM_HDR_SIZE 64
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#define PHY_RSSI_SLID_WIN_MAX 100
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@ -183,29 +124,6 @@
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extern int hwwep;
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enum RTL819x_PHY_PARAM {
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RTL819X_PHY_MACPHY_REG = 0,
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RTL819X_PHY_MACPHY_REG_PG = 1,
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RTL8188C_PHY_MACREG = 2,
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RTL8192C_PHY_MACREG = 3,
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RTL819X_PHY_REG = 4,
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RTL819X_PHY_REG_1T2R = 5,
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RTL819X_PHY_REG_to1T1R = 6,
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RTL819X_PHY_REG_to1T2R = 7,
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RTL819X_PHY_REG_to2T2R = 8,
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RTL819X_PHY_REG_PG = 9,
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RTL819X_AGC_TAB = 10,
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RTL819X_PHY_RADIO_A = 11,
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RTL819X_PHY_RADIO_A_1T = 12,
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RTL819X_PHY_RADIO_A_2T = 13,
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RTL819X_PHY_RADIO_B = 14,
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RTL819X_PHY_RADIO_B_GM = 15,
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RTL819X_PHY_RADIO_C = 16,
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RTL819X_PHY_RADIO_D = 17,
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RTL819X_EEPROM_MAP = 18,
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RTL819X_EFUSE_MAP = 19,
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};
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enum nic_t {
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NIC_UNKNOWN = 0,
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NIC_8192E = 1,
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@ -220,7 +138,6 @@ enum nic_t {
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enum rt_eeprom_type {
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EEPROM_93C46,
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EEPROM_93C56,
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EEPROM_BOOT_EFUSE,
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};
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enum dcmg_txcmd_op {
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@ -242,19 +159,6 @@ enum rt_rf_type_819xu {
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RF_PSEUDO_11N = 5,
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};
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enum rf_step {
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RF_STEP_INIT = 0,
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RF_STEP_NORMAL,
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RF_STEP_MAX
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};
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enum rt_status {
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RT_STATUS_SUCCESS,
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RT_STATUS_FAILURE,
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RT_STATUS_PENDING,
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RT_STATUS_RESOURCE
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};
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enum rt_customer_id {
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RT_CID_DEFAULT = 0,
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RT_CID_8187_ALPHA0 = 1,
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@ -294,51 +198,6 @@ enum reset_type {
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RESET_TYPE_SILENT = 0x02
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};
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enum ic_inferiority_8192s {
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IC_INFERIORITY_A = 0,
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IC_INFERIORITY_B = 1,
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};
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enum pci_bridge_vendor {
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PCI_BRIDGE_VENDOR_INTEL = 0x0,
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PCI_BRIDGE_VENDOR_ATI,
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PCI_BRIDGE_VENDOR_AMD,
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PCI_BRIDGE_VENDOR_SIS,
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PCI_BRIDGE_VENDOR_UNKNOWN,
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PCI_BRIDGE_VENDOR_MAX,
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};
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struct buffer {
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struct buffer *next;
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u32 *buf;
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dma_addr_t dma;
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};
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struct rtl_reg_debug {
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unsigned int cmd;
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struct {
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unsigned char type;
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unsigned char addr;
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unsigned char page;
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unsigned char length;
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} head;
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unsigned char buf[0xff];
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};
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struct rt_tx_rahis {
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u32 cck[4];
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u32 ofdm[8];
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u32 ht_mcs[4][16];
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};
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struct rt_smooth_data_4rf {
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char elements[4][100];
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u32 index;
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u32 TotalNum;
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u32 TotalVal[4];
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};
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struct rt_stats {
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unsigned long txrdu;
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unsigned long rxrdu;
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@ -426,10 +285,8 @@ struct rt_stats {
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u8 rx_rssi_percentage[4];
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u8 rx_evm_percentage[2];
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long rxSNRdB[4];
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struct rt_tx_rahis txrate;
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u32 Slide_Beacon_pwdb[100];
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u32 Slide_Beacon_Total;
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struct rt_smooth_data_4rf cck_adc_pwdb;
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u32 CurrentShowTxate;
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};
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@ -442,15 +299,6 @@ struct channel_access_setting {
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u16 CWmaxIndex;
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};
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enum two_port_status {
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TWO_PORT_STATUS__DEFAULT_ONLY,
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TWO_PORT_STATUS__EXTENSION_ONLY,
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TWO_PORT_STATUS__EXTENSION_FOLLOW_DEFAULT,
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TWO_PORT_STATUS__DEFAULT_G_EXTENSION_N20,
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TWO_PORT_STATUS__ADHOC,
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TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE
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};
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struct init_gain {
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u8 xaagccore1;
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u8 xbagccore1;
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@ -553,7 +401,6 @@ struct r8192_priv {
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enum rt_rf_type_819xu rf_chip;
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enum ic_inferiority_8192s IC_Class;
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enum ht_channel_width CurrentChannelBW;
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struct bb_reg_definition PHYRegDef[4];
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struct rate_adaptive rate_adaptive;
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@ -792,7 +639,6 @@ struct r8192_priv {
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u8 bHwRfOffAction;
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bool aspm_clkreq_enable;
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u32 pci_bridge_vendor;
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u8 RegHostPciASPMSetting;
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u8 RegDevicePciASPMSetting;
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