diff --git a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
index 447cb131e909..17cce4490456 100644
--- a/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
+++ b/Documentation/devicetree/bindings/sound/omap-mcbsp.txt
@@ -8,38 +8,30 @@ Required properties:
 - reg: Register location and size, for OMAP4+ as an array:
        <MPU access base address, size>,
        <L3 interconnect address, size>;
+- reg-names: Array of strings associated with the address space
 - interrupts: Interrupt numbers for the McBSP port, as an array in case the
 	      McBSP IP have more interrupt lines:
 	<OCP compliant irq>,
 	<TX irq>,
 	<RX irq>;
+- interrupt-names: Array of strings associated with the interrupt numbers
 - interrupt-parent: The parent interrupt controller
 - ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
 - ti,hwmods: Name of the hwmod associated to the McBSP port
 
-Sidetone support for OMAP3 McBSP2 and 3 ports:
-- sidetone { }: Within this section the following parameters are required:
-- reg: Register location and size for the ST block
-- interrupts: The interrupt number for the ST block
-- interrupt-parent: The parent interrupt controller for the ST block
-
 Example:
 
 mcbsp2: mcbsp@49022000 {
 	compatible = "ti,omap3-mcbsp";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	reg = <0x49022000 0xff>;
-	interrupts = <0 17 0x4>, /* OCP compliant interrup */
-		     <0 62 0x4>, /* TX interrup */
-		     <0 63 0x4>; /* RX interrup */
+	reg = <0x49022000 0xff>,
+	      <0x49028000 0xff>;
+	reg-names = "mpu", "sidetone";
+	interrupts = <0 17 0x4>, /* OCP compliant interrupt */
+		     <0 62 0x4>, /* TX interrupt */
+		     <0 63 0x4>, /* RX interrupt */
+		     <0 4 0x4>;  /* Sidetone */
+	interrupt-names = "common", "tx", "rx", "sidetone";
 	interrupt-parent = <&intc>;
 	ti,buffer-size = <1280>;
 	ti,hwmods = "mcbsp2";
-
-	sidetone {
-		reg = <0x49028000 0xff>;
-		interrupts = <0 4 0x4>;
-		interrupt-parent = <&intc>;
-	};
 };