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drm/vc4: crtc: Add a delay after disabling the PixelValve output

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In order to avoid pixels getting stuck in the (unflushable) FIFO between
the HVS and the PV, we need to add some delay after disabling the PV output
and before disabling the HDMI controller. 20ms seems to be good enough so
let's use that.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/15cf215bd2ceebd203c4010c09c21a4019c650ed.1599120059.git-series.maxime@cerno.tech
This commit is contained in:
Maxime Ripard 2020-09-03 10:01:01 +02:00
parent 792c3132bc
commit b7cb67a6b4
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1 changed files with 18 additions and 0 deletions
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18
drivers/gpu/drm/vc4/vc4_crtc.c
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@ -403,6 +403,24 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
/*
* This delay is needed to avoid to get a pixel stuck in an
* unflushable FIFO between the pixelvalve and the HDMI
* controllers on the BCM2711.
*
* Timing is fairly sensitive here, so mdelay is the safest
* approach.
*
* If it was to be reworked, the stuck pixel happens on a
* BCM2711 when changing mode with a good probability, so a
* script that changes mode on a regular basis should trigger
* the bug after less than 10 attempts. It manifests itself with
* every pixels being shifted by one to the right, and thus the
* last pixel of a line actually being displayed as the first
* pixel on the next line.
*/
mdelay(20);
if (vc4_encoder->post_crtc_disable) if (vc4_encoder->post_crtc_disable)
vc4_encoder->post_crtc_disable(encoder); vc4_encoder->post_crtc_disable(encoder);