forked from Minki/linux
Merge branch 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Alex writes: "This request is mostly load detection fixes from Egbert and me." * 'drm-fixes-3.7' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: add load detection support for ext DAC on R200 (v2) DRM/radeon: For single CRTC GPUs move handling of CRTC_CRT_ON to crtc_dpms(). DRM/Radeon: Fix TV DAC Load Detection for single CRTC chips. DRM/Radeon: Clean up code in TV DAC load detection. drm/radeon: fix ATPX function documentation drivers/gpu/drm/radeon/evergreen_cs.c: Remove unnecessary semicolon DRM/Radeon: On DVI-I use Load Detection when EDID is bogus. DRM/Radeon: Fix primary DAC Load Detection for RV100 chips. DRM/Radeon: Fix Load Detection on legacy primary DAC.
This commit is contained in:
Dave Airlie
commit
b7a46dcf7a
@ -264,7 +264,7 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
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/* macro tile width & height */
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palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
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halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
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mtileb = (palign / 8) * (halign / 8) * tileb;;
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mtileb = (palign / 8) * (halign / 8) * tileb;
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mtile_pr = surf->nbx / palign;
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mtile_ps = (mtile_pr * surf->nby) / halign;
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surf->layer_size = mtile_ps * mtileb * slice_pt;
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@ -352,9 +352,9 @@ static int radeon_atpx_switchto(enum vga_switcheroo_client_id id)
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}
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/**
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* radeon_atpx_switchto - switch to the requested GPU
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* radeon_atpx_power_state - power down/up the requested GPU
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*
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* @id: GPU to switch to
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* @id: GPU to power down/up
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* @state: requested power state (0 = off, 1 = on)
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*
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* Execute the necessary ATPX function to power down/up the discrete GPU
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@ -941,7 +941,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
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struct drm_mode_object *obj;
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int i;
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enum drm_connector_status ret = connector_status_disconnected;
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bool dret = false;
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bool dret = false, broken_edid = false;
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if (!force && radeon_check_hpd_status_unchanged(connector))
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return connector->status;
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@ -965,6 +965,9 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
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ret = connector_status_disconnected;
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DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", drm_get_connector_name(connector));
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radeon_connector->ddc_bus = NULL;
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} else {
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ret = connector_status_connected;
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broken_edid = true; /* defer use_digital to later */
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}
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} else {
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radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
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@ -1047,13 +1050,24 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
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encoder_funcs = encoder->helper_private;
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if (encoder_funcs->detect) {
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if (ret != connector_status_connected) {
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ret = encoder_funcs->detect(encoder, connector);
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if (ret == connector_status_connected) {
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radeon_connector->use_digital = false;
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if (!broken_edid) {
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if (ret != connector_status_connected) {
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/* deal with analog monitors without DDC */
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ret = encoder_funcs->detect(encoder, connector);
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if (ret == connector_status_connected) {
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radeon_connector->use_digital = false;
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}
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if (ret != connector_status_disconnected)
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radeon_connector->detected_by_load = true;
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}
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if (ret != connector_status_disconnected)
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radeon_connector->detected_by_load = true;
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} else {
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enum drm_connector_status lret;
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/* assume digital unless load detected otherwise */
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radeon_connector->use_digital = true;
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lret = encoder_funcs->detect(encoder, connector);
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DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
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if (lret == connector_status_connected)
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radeon_connector->use_digital = false;
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}
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break;
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}
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@ -295,6 +295,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t crtc_ext_cntl = 0;
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uint32_t mask;
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if (radeon_crtc->crtc_id)
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@ -307,6 +308,16 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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RADEON_CRTC_VSYNC_DIS |
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RADEON_CRTC_HSYNC_DIS);
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/*
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* On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
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* Therefore it is set in the DAC DMPS function.
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* This is different for GPU's with a single CRTC but a primary and a
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* TV DAC: here it controls the single CRTC no matter where it is
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* routed. Therefore we set it here.
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*/
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if (rdev->flags & RADEON_SINGLE_CRTC)
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crtc_ext_cntl = RADEON_CRTC_CRT_ON;
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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radeon_crtc->enabled = true;
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@ -317,7 +328,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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else {
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WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
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RADEON_CRTC_DISP_REQ_EN_B));
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WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
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WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
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}
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drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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radeon_crtc_load_lut(crtc);
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@ -331,7 +342,7 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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else {
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WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
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RADEON_CRTC_DISP_REQ_EN_B));
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WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
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WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
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}
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radeon_crtc->enabled = false;
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/* adjust pm to dpms changes AFTER disabling crtcs */
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@ -537,7 +537,9 @@ static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode
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break;
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}
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WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
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/* handled in radeon_crtc_dpms() */
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if (!(rdev->flags & RADEON_SINGLE_CRTC))
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WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
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WREG32(RADEON_DAC_CNTL, dac_cntl);
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WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
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@ -662,6 +664,8 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc
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if (ASIC_IS_R300(rdev))
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tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
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else if (ASIC_IS_RV100(rdev))
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tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
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else
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tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
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@ -671,6 +675,7 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc
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tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
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WREG32(RADEON_DAC_CNTL, tmp);
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tmp = dac_macro_cntl;
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tmp &= ~(RADEON_DAC_PDWN_R |
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RADEON_DAC_PDWN_G |
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RADEON_DAC_PDWN_B);
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@ -1092,7 +1097,8 @@ static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
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} else {
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if (is_tv)
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WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
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else
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/* handled in radeon_crtc_dpms() */
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else if (!(rdev->flags & RADEON_SINGLE_CRTC))
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WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
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WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
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}
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@ -1416,13 +1422,104 @@ static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
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return found;
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}
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static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
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uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
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uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
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uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
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uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
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bool found = false;
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int i;
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/* save the regs we need */
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gpio_monid = RREG32(RADEON_GPIO_MONID);
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fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
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disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
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crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
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disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
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disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
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disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
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disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
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disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
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disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
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crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
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crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
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crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
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crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
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tmp = RREG32(RADEON_GPIO_MONID);
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tmp &= ~RADEON_GPIO_A_0;
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WREG32(RADEON_GPIO_MONID, tmp);
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WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
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RADEON_FP2_PANEL_FORMAT |
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R200_FP2_SOURCE_SEL_TRANS_UNIT |
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RADEON_FP2_DVO_EN |
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R200_FP2_DVO_RATE_SEL_SDR));
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WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
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RADEON_DISP_TRANS_MATRIX_GRAPHICS));
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WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
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RADEON_CRTC2_DISP_REQ_EN_B));
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
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WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
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WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
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WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
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WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
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for (i = 0; i < 200; i++) {
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tmp = RREG32(RADEON_GPIO_MONID);
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if (tmp & RADEON_GPIO_Y_0)
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found = true;
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if (found)
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break;
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if (!drm_can_sleep())
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mdelay(1);
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else
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msleep(1);
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}
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/* restore the regs we used */
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
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WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
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WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
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WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
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WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
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WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
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WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
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WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
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WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
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WREG32(RADEON_GPIO_MONID, gpio_monid);
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return found;
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}
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static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
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uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
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uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
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uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
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uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
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enum drm_connector_status found = connector_status_disconnected;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
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@ -1459,12 +1556,27 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
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return connector_status_disconnected;
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}
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/* R200 uses an external DAC for secondary DAC */
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if (rdev->family == CHIP_R200) {
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if (radeon_legacy_ext_dac_detect(encoder, connector))
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found = connector_status_connected;
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return found;
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}
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/* save the regs we need */
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pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
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gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
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disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
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disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
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crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
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if (rdev->flags & RADEON_SINGLE_CRTC) {
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crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
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} else {
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if (ASIC_IS_R300(rdev)) {
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gpiopad_a = RREG32(RADEON_GPIOPAD_A);
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disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
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} else {
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disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
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}
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crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
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}
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tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
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dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
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dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
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@ -1473,22 +1585,24 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
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| RADEON_PIX2CLK_DAC_ALWAYS_ONb);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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if (ASIC_IS_R300(rdev))
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WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
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tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
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tmp |= RADEON_CRTC2_CRT2_ON |
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(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
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WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
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if (ASIC_IS_R300(rdev)) {
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tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
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tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
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WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
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if (rdev->flags & RADEON_SINGLE_CRTC) {
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tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
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WREG32(RADEON_CRTC_EXT_CNTL, tmp);
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} else {
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tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
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WREG32(RADEON_DISP_HW_DEBUG, tmp);
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tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
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tmp |= RADEON_CRTC2_CRT2_ON |
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(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
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WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
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if (ASIC_IS_R300(rdev)) {
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WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
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tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
|
||||
tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
|
||||
WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
|
||||
} else {
|
||||
tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
|
||||
WREG32(RADEON_DISP_HW_DEBUG, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
tmp = RADEON_TV_DAC_NBLANK |
|
||||
@ -1530,14 +1644,19 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
|
||||
WREG32(RADEON_DAC_CNTL2, dac_cntl2);
|
||||
WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
|
||||
WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
|
||||
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
|
||||
|
||||
if (ASIC_IS_R300(rdev)) {
|
||||
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
|
||||
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
|
||||
if (rdev->flags & RADEON_SINGLE_CRTC) {
|
||||
WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
|
||||
} else {
|
||||
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
|
||||
WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
|
||||
if (ASIC_IS_R300(rdev)) {
|
||||
WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
|
||||
WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
|
||||
} else {
|
||||
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
|
||||
}
|
||||
}
|
||||
|
||||
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
|
||||
|
||||
return found;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user