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drm/vc4: hdmi: Replace CSC_CTL hardcoded value by defines

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On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an
opaque value. Let's replace it with properly defined values.

Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120151625.594595-9-maxime@cerno.tech
This commit is contained in:
Maxime Ripard 2022-01-20 16:16:17 +01:00
parent 0cbb53b283
commit b718d8478e
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GPG Key ID: E3EF0D6F671851C5
2 changed files with 5 additions and 3 deletions
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5
drivers/gpu/drm/vc4/vc4_hdmi.c
View File

@ -779,9 +779,8 @@ static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
const struct drm_display_mode *mode) const struct drm_display_mode *mode)
{ {
unsigned long flags; unsigned long flags;
u32 csc_ctl; u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
VC5_MT_CP_CSC_CTL_MODE);
csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);

3
drivers/gpu/drm/vc4/vc4_regs.h
View File

@ -774,6 +774,9 @@ enum {
# define VC4_HD_CSC_CTL_RGB2YCC BIT(1) # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
# define VC4_HD_CSC_CTL_ENABLE BIT(0) # define VC4_HD_CSC_CTL_ENABLE BIT(0)
# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
# define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1) # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
/* HVS display list information. */ /* HVS display list information. */