forked from Minki/linux
ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance
There are two instances of PCIe PHY in DRA7xx. So renamed optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk respectively. This is needed for adding the clocks for second PCIe PHY instance. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -1165,7 +1165,7 @@
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reg = <0x021c>, <0x0220>;
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};
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optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {
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optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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#clock-cells = <0>;
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@ -1183,7 +1183,7 @@
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ti,max-div = <2>;
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};
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optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
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optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
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compatible = "ti,gate-clock";
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clocks = <&apll_pcie_ck>;
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#clock-cells = <0>;
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@ -1191,7 +1191,7 @@
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ti,bit-shift = <9>;
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};
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optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
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optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
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compatible = "ti,gate-clock";
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clocks = <&optfclk_pciephy_div>;
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#clock-cells = <0>;
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