drm/amd/display: DP training to set properly SCRAMBLING_DISABLE
[Why] DP training sequence to set SCRAMBLING_DISABLE bit properly based on training pattern - per DP Spec. [How] Update dpcd_pattern.v1_4.SCRAMBLING_DISABLE with 1 for TPS1, TPS2, TPS3, but not for TPS4. Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -220,6 +220,30 @@ static enum dpcd_training_patterns
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return dpcd_tr_pattern;
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return dpcd_tr_pattern;
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}
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}
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static uint8_t dc_dp_initialize_scrambling_data_symbols(
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struct dc_link *link,
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enum dc_dp_training_pattern pattern)
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{
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uint8_t disable_scrabled_data_symbols = 0;
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switch (pattern) {
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case DP_TRAINING_PATTERN_SEQUENCE_1:
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case DP_TRAINING_PATTERN_SEQUENCE_2:
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case DP_TRAINING_PATTERN_SEQUENCE_3:
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disable_scrabled_data_symbols = 1;
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break;
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case DP_TRAINING_PATTERN_SEQUENCE_4:
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disable_scrabled_data_symbols = 0;
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break;
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default:
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ASSERT(0);
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DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
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__func__, pattern);
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break;
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}
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return disable_scrabled_data_symbols;
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}
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static inline bool is_repeater(struct dc_link *link, uint32_t offset)
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static inline bool is_repeater(struct dc_link *link, uint32_t offset)
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{
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{
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return (!link->is_lttpr_mode_transparent && offset != 0);
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return (!link->is_lttpr_mode_transparent && offset != 0);
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@ -252,6 +276,9 @@ static void dpcd_set_lt_pattern_and_lane_settings(
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
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dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
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dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
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dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
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dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
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dc_dp_initialize_scrambling_data_symbols(link, pattern);
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dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
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dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
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= dpcd_pattern.raw;
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= dpcd_pattern.raw;
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