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drm/i915/gt: Only wait for register chipset flush if active

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Only serialise with the chipset using an mmio if the chipset is
currently active. We expect that any writes into the chipset range will
simply be forgotten until it wakes up.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191118184943.2593048-8-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2019-11-18 18:49:33 +00:00
parent d147483884
commit b6422694c5
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/gt/intel_gt.c
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@ -304,7 +304,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
intel_gt_chipset_flush(gt);
with_intel_runtime_pm(uncore->rpm, wakeref) {
with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
unsigned long flags;
spin_lock_irqsave(&uncore->lock, flags);