forked from Minki/linux
Merge branch 'drm-gma500-alanc' into drm-core-next
* drm-gma500-alanc: gma500: Now connect up to the DRM build to finish the job gma500: fixup build versus latest header changes. gma500: Add support for Cedarview gma500: Add Oaktrail support gma500: Add Poulsbo support gma500: Add the core DRM files and headers gma500: Add the i2c bus support gma500: Add the glue to the various BIOS and firmware interfaces gma500: Add device framework gma500: introduce the framebuffer support code gma500: introduce the GTT and MMU handling logic gma500: GEM and GEM glue gma500: Move the basic driver out of staging
This commit is contained in:
commit
b63e0f9cb4
@ -162,3 +162,6 @@ config DRM_SAVAGE
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source "drivers/gpu/drm/exynos/Kconfig"
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source "drivers/gpu/drm/vmwgfx/Kconfig"
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source "drivers/gpu/drm/gma500/Kconfig"
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|
@ -36,4 +36,5 @@ obj-$(CONFIG_DRM_VMWGFX)+= vmwgfx/
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obj-$(CONFIG_DRM_VIA) +=via/
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obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/
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obj-$(CONFIG_DRM_EXYNOS) +=exynos/
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obj-$(CONFIG_DRM_GMA500) += gma500/
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obj-y += i2c/
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|
26
drivers/gpu/drm/gma500/Kconfig
Normal file
26
drivers/gpu/drm/gma500/Kconfig
Normal file
@ -0,0 +1,26 @@
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config DRM_GMA500
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tristate "Intel GMA5/600 KMS Framebuffer"
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depends on DRM && PCI && X86 && EXPERIMENTAL
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select FB_CFB_COPYAREA
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select FB_CFB_FILLRECT
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select FB_CFB_IMAGEBLIT
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select DRM_KMS_HELPER
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select DRM_TTM
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help
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Say yes for an experimental 2D KMS framebuffer driver for the
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Intel GMA500 ('Poulsbo') and other Intel IMG based graphics
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devices.
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config DRM_GMA600
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bool "Intel GMA600 support (Experimental)"
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depends on DRM_GMA500
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help
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Say yes to include support for GMA600 (Intel Moorestown/Oaktrail)
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platforms with LVDS ports. HDMI and MIPI are not currently
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supported.
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config DRM_CEDARVIEW
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bool "Intel Cedarview support (Experimental)"
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depends on DRM_GMA500
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help
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Say yes to include support for Intel Cedarview platforms
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39
drivers/gpu/drm/gma500/Makefile
Normal file
39
drivers/gpu/drm/gma500/Makefile
Normal file
@ -0,0 +1,39 @@
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#
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# KMS driver for the GMA500
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#
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ccflags-y += -Iinclude/drm
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gma500_gfx-y += gem_glue.o \
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accel_2d.o \
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backlight.o \
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framebuffer.o \
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gem.o \
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gtt.o \
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intel_bios.o \
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intel_i2c.o \
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intel_opregion.o \
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mmu.o \
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power.o \
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psb_drv.o \
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psb_intel_display.o \
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psb_intel_lvds.o \
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psb_intel_modes.o \
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psb_intel_sdvo.o \
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psb_lid.o \
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psb_irq.o \
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psb_device.o \
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mid_bios.o
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gma500_gfx-$(CONFIG_DRM_CEDARVIEW) += cdv_device.o \
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cdv_intel_crt.o \
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cdv_intel_display.o \
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cdv_intel_hdmi.o \
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cdv_intel_lvds.o
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gma500_gfx-$(CONFIG_DRM_GMA600) += oaktrail_device.o \
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oaktrail_crtc.o \
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oaktrail_lvds.o \
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oaktrail_hdmi.o \
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oaktrail_hdmi_i2c.o
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obj-$(CONFIG_DRM_GMA500) += gma500_gfx.o
|
362
drivers/gpu/drm/gma500/accel_2d.c
Normal file
362
drivers/gpu/drm/gma500/accel_2d.c
Normal file
@ -0,0 +1,362 @@
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/**************************************************************************
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||||
* Copyright (c) 2007-2011, Intel Corporation.
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* All Rights Reserved.
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
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||||
*
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||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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||||
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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* develop this driver.
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*
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**************************************************************************/
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||||
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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||||
#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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||||
#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include <drm/drm_crtc.h>
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#include "psb_drv.h"
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#include "psb_reg.h"
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#include "framebuffer.h"
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||||
/**
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* psb_spank - reset the 2D engine
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* @dev_priv: our PSB DRM device
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*
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* Soft reset the graphics engine and then reload the necessary registers.
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||||
* We use this at initialisation time but it will become relevant for
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||||
* accelerated X later
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*/
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void psb_spank(struct drm_psb_private *dev_priv)
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||||
{
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||||
PSB_WSGX32(_PSB_CS_RESET_BIF_RESET | _PSB_CS_RESET_DPM_RESET |
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_PSB_CS_RESET_TA_RESET | _PSB_CS_RESET_USE_RESET |
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||||
_PSB_CS_RESET_ISP_RESET | _PSB_CS_RESET_TSP_RESET |
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||||
_PSB_CS_RESET_TWOD_RESET, PSB_CR_SOFT_RESET);
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||||
PSB_RSGX32(PSB_CR_SOFT_RESET);
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||||
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msleep(1);
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||||
PSB_WSGX32(0, PSB_CR_SOFT_RESET);
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wmb();
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PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_CB_CTRL_CLEAR_FAULT,
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||||
PSB_CR_BIF_CTRL);
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||||
wmb();
|
||||
(void) PSB_RSGX32(PSB_CR_BIF_CTRL);
|
||||
|
||||
msleep(1);
|
||||
PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_CB_CTRL_CLEAR_FAULT,
|
||||
PSB_CR_BIF_CTRL);
|
||||
(void) PSB_RSGX32(PSB_CR_BIF_CTRL);
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||||
PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb2_2d_wait_available - wait for FIFO room
|
||||
* @dev_priv: our DRM device
|
||||
* @size: size (in dwords) of the command we want to issue
|
||||
*
|
||||
* Wait until there is room to load the FIFO with our data. If the
|
||||
* device is not responding then reset it
|
||||
*/
|
||||
static int psb_2d_wait_available(struct drm_psb_private *dev_priv,
|
||||
unsigned size)
|
||||
{
|
||||
uint32_t avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
|
||||
unsigned long t = jiffies + HZ;
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||||
|
||||
while (avail < size) {
|
||||
avail = PSB_RSGX32(PSB_CR_2D_SOCIF);
|
||||
if (time_after(jiffies, t)) {
|
||||
psb_spank(dev_priv);
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_2d_submit - submit a 2D command
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||||
* @dev_priv: our DRM device
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||||
* @cmdbuf: command to issue
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||||
* @size: length (in dwords)
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||||
*
|
||||
* Issue one or more 2D commands to the accelerator. This needs to be
|
||||
* serialized later when we add the GEM interfaces for acceleration
|
||||
*/
|
||||
static int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
|
||||
unsigned size)
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||||
{
|
||||
int ret = 0;
|
||||
int i;
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||||
unsigned submit_size;
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||||
|
||||
mutex_lock(&dev_priv->mutex_2d);
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||||
while (size > 0) {
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||||
submit_size = (size < 0x60) ? size : 0x60;
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||||
size -= submit_size;
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||||
ret = psb_2d_wait_available(dev_priv, submit_size);
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||||
if (ret)
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||||
break;
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||||
|
||||
submit_size <<= 2;
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||||
|
||||
for (i = 0; i < submit_size; i += 4)
|
||||
PSB_WSGX32(*cmdbuf++, PSB_SGX_2D_SLAVE_PORT + i);
|
||||
|
||||
(void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT + i - 4);
|
||||
}
|
||||
mutex_unlock(&dev_priv->mutex_2d);
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||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/**
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||||
* psb_accel_2d_copy_direction - compute blit order
|
||||
* @xdir: X direction of move
|
||||
* @ydir: Y direction of move
|
||||
*
|
||||
* Compute the correct order setings to ensure that an overlapping blit
|
||||
* correctly copies all the pixels.
|
||||
*/
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||||
static u32 psb_accel_2d_copy_direction(int xdir, int ydir)
|
||||
{
|
||||
if (xdir < 0)
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||||
return (ydir < 0) ? PSB_2D_COPYORDER_BR2TL :
|
||||
PSB_2D_COPYORDER_TR2BL;
|
||||
else
|
||||
return (ydir < 0) ? PSB_2D_COPYORDER_BL2TR :
|
||||
PSB_2D_COPYORDER_TL2BR;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_accel_2d_copy - accelerated 2D copy
|
||||
* @dev_priv: our DRM device
|
||||
* @src_offset in bytes
|
||||
* @src_stride in bytes
|
||||
* @src_format psb 2D format defines
|
||||
* @dst_offset in bytes
|
||||
* @dst_stride in bytes
|
||||
* @dst_format psb 2D format defines
|
||||
* @src_x offset in pixels
|
||||
* @src_y offset in pixels
|
||||
* @dst_x offset in pixels
|
||||
* @dst_y offset in pixels
|
||||
* @size_x of the copied area
|
||||
* @size_y of the copied area
|
||||
*
|
||||
* Format and issue a 2D accelerated copy command.
|
||||
*/
|
||||
static int psb_accel_2d_copy(struct drm_psb_private *dev_priv,
|
||||
uint32_t src_offset, uint32_t src_stride,
|
||||
uint32_t src_format, uint32_t dst_offset,
|
||||
uint32_t dst_stride, uint32_t dst_format,
|
||||
uint16_t src_x, uint16_t src_y,
|
||||
uint16_t dst_x, uint16_t dst_y,
|
||||
uint16_t size_x, uint16_t size_y)
|
||||
{
|
||||
uint32_t blit_cmd;
|
||||
uint32_t buffer[10];
|
||||
uint32_t *buf;
|
||||
uint32_t direction;
|
||||
|
||||
buf = buffer;
|
||||
|
||||
direction =
|
||||
psb_accel_2d_copy_direction(src_x - dst_x, src_y - dst_y);
|
||||
|
||||
if (direction == PSB_2D_COPYORDER_BR2TL ||
|
||||
direction == PSB_2D_COPYORDER_TR2BL) {
|
||||
src_x += size_x - 1;
|
||||
dst_x += size_x - 1;
|
||||
}
|
||||
if (direction == PSB_2D_COPYORDER_BR2TL ||
|
||||
direction == PSB_2D_COPYORDER_BL2TR) {
|
||||
src_y += size_y - 1;
|
||||
dst_y += size_y - 1;
|
||||
}
|
||||
|
||||
blit_cmd =
|
||||
PSB_2D_BLIT_BH |
|
||||
PSB_2D_ROT_NONE |
|
||||
PSB_2D_DSTCK_DISABLE |
|
||||
PSB_2D_SRCCK_DISABLE |
|
||||
PSB_2D_USE_PAT | PSB_2D_ROP3_SRCCOPY | direction;
|
||||
|
||||
*buf++ = PSB_2D_FENCE_BH;
|
||||
*buf++ =
|
||||
PSB_2D_DST_SURF_BH | dst_format | (dst_stride <<
|
||||
PSB_2D_DST_STRIDE_SHIFT);
|
||||
*buf++ = dst_offset;
|
||||
*buf++ =
|
||||
PSB_2D_SRC_SURF_BH | src_format | (src_stride <<
|
||||
PSB_2D_SRC_STRIDE_SHIFT);
|
||||
*buf++ = src_offset;
|
||||
*buf++ =
|
||||
PSB_2D_SRC_OFF_BH | (src_x << PSB_2D_SRCOFF_XSTART_SHIFT) |
|
||||
(src_y << PSB_2D_SRCOFF_YSTART_SHIFT);
|
||||
*buf++ = blit_cmd;
|
||||
*buf++ =
|
||||
(dst_x << PSB_2D_DST_XSTART_SHIFT) | (dst_y <<
|
||||
PSB_2D_DST_YSTART_SHIFT);
|
||||
*buf++ =
|
||||
(size_x << PSB_2D_DST_XSIZE_SHIFT) | (size_y <<
|
||||
PSB_2D_DST_YSIZE_SHIFT);
|
||||
*buf++ = PSB_2D_FLUSH_BH;
|
||||
|
||||
return psbfb_2d_submit(dev_priv, buffer, buf - buffer);
|
||||
}
|
||||
|
||||
/**
|
||||
* psbfb_copyarea_accel - copyarea acceleration for /dev/fb
|
||||
* @info: our framebuffer
|
||||
* @a: copyarea parameters from the framebuffer core
|
||||
*
|
||||
* Perform a 2D copy via the accelerator
|
||||
*/
|
||||
static void psbfb_copyarea_accel(struct fb_info *info,
|
||||
const struct fb_copyarea *a)
|
||||
{
|
||||
struct psb_fbdev *fbdev = info->par;
|
||||
struct psb_framebuffer *psbfb = &fbdev->pfb;
|
||||
struct drm_device *dev = psbfb->base.dev;
|
||||
struct drm_framebuffer *fb = fbdev->psb_fb_helper.fb;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
uint32_t offset;
|
||||
uint32_t stride;
|
||||
uint32_t src_format;
|
||||
uint32_t dst_format;
|
||||
|
||||
if (!fb)
|
||||
return;
|
||||
|
||||
offset = psbfb->gtt->offset;
|
||||
stride = fb->pitch;
|
||||
|
||||
switch (fb->depth) {
|
||||
case 8:
|
||||
src_format = PSB_2D_SRC_332RGB;
|
||||
dst_format = PSB_2D_DST_332RGB;
|
||||
break;
|
||||
case 15:
|
||||
src_format = PSB_2D_SRC_555RGB;
|
||||
dst_format = PSB_2D_DST_555RGB;
|
||||
break;
|
||||
case 16:
|
||||
src_format = PSB_2D_SRC_565RGB;
|
||||
dst_format = PSB_2D_DST_565RGB;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
/* this is wrong but since we don't do blending its okay */
|
||||
src_format = PSB_2D_SRC_8888ARGB;
|
||||
dst_format = PSB_2D_DST_8888ARGB;
|
||||
break;
|
||||
default:
|
||||
/* software fallback */
|
||||
cfb_copyarea(info, a);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!gma_power_begin(dev, false)) {
|
||||
cfb_copyarea(info, a);
|
||||
return;
|
||||
}
|
||||
psb_accel_2d_copy(dev_priv,
|
||||
offset, stride, src_format,
|
||||
offset, stride, dst_format,
|
||||
a->sx, a->sy, a->dx, a->dy, a->width, a->height);
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* psbfb_copyarea - 2D copy interface
|
||||
* @info: our framebuffer
|
||||
* @region: region to copy
|
||||
*
|
||||
* Copy an area of the framebuffer console either by the accelerator
|
||||
* or directly using the cfb helpers according to the request
|
||||
*/
|
||||
void psbfb_copyarea(struct fb_info *info,
|
||||
const struct fb_copyarea *region)
|
||||
{
|
||||
if (unlikely(info->state != FBINFO_STATE_RUNNING))
|
||||
return;
|
||||
|
||||
/* Avoid the 8 pixel erratum */
|
||||
if (region->width == 8 || region->height == 8 ||
|
||||
(info->flags & FBINFO_HWACCEL_DISABLED))
|
||||
return cfb_copyarea(info, region);
|
||||
|
||||
psbfb_copyarea_accel(info, region);
|
||||
}
|
||||
|
||||
/**
|
||||
* psbfb_sync - synchronize 2D
|
||||
* @info: our framebuffer
|
||||
*
|
||||
* Wait for the 2D engine to quiesce so that we can do CPU
|
||||
* access to the framebuffer again
|
||||
*/
|
||||
int psbfb_sync(struct fb_info *info)
|
||||
{
|
||||
struct psb_fbdev *fbdev = info->par;
|
||||
struct psb_framebuffer *psbfb = &fbdev->pfb;
|
||||
struct drm_device *dev = psbfb->base.dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long _end = jiffies + DRM_HZ;
|
||||
int busy = 0;
|
||||
|
||||
mutex_lock(&dev_priv->mutex_2d);
|
||||
/*
|
||||
* First idle the 2D engine.
|
||||
*/
|
||||
|
||||
if ((PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) &&
|
||||
((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & _PSB_C2B_STATUS_BUSY) == 0))
|
||||
goto out;
|
||||
|
||||
do {
|
||||
busy = (PSB_RSGX32(PSB_CR_2D_SOCIF) != _PSB_C2_SOCIF_EMPTY);
|
||||
cpu_relax();
|
||||
} while (busy && !time_after_eq(jiffies, _end));
|
||||
|
||||
if (busy)
|
||||
busy = (PSB_RSGX32(PSB_CR_2D_SOCIF) != _PSB_C2_SOCIF_EMPTY);
|
||||
if (busy)
|
||||
goto out;
|
||||
|
||||
do {
|
||||
busy = ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) &
|
||||
_PSB_C2B_STATUS_BUSY) != 0);
|
||||
cpu_relax();
|
||||
} while (busy && !time_after_eq(jiffies, _end));
|
||||
if (busy)
|
||||
busy = ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) &
|
||||
_PSB_C2B_STATUS_BUSY) != 0);
|
||||
|
||||
out:
|
||||
mutex_unlock(&dev_priv->mutex_2d);
|
||||
return (busy) ? -EBUSY : 0;
|
||||
}
|
49
drivers/gpu/drm/gma500/backlight.c
Normal file
49
drivers/gpu/drm/gma500/backlight.c
Normal file
@ -0,0 +1,49 @@
|
||||
/*
|
||||
* GMA500 Backlight Interface
|
||||
*
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors: Eric Knopp
|
||||
*
|
||||
*/
|
||||
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "intel_bios.h"
|
||||
#include "power.h"
|
||||
|
||||
int gma_backlight_init(struct drm_device *dev)
|
||||
{
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
return dev_priv->ops->backlight_init(dev);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
void gma_backlight_exit(struct drm_device *dev)
|
||||
{
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
if (dev_priv->backlight_device) {
|
||||
dev_priv->backlight_device->props.brightness = 0;
|
||||
backlight_update_status(dev_priv->backlight_device);
|
||||
backlight_device_unregister(dev_priv->backlight_device);
|
||||
}
|
||||
#endif
|
||||
}
|
351
drivers/gpu/drm/gma500/cdv_device.c
Normal file
351
drivers/gpu/drm/gma500/cdv_device.c
Normal file
@ -0,0 +1,351 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#include <linux/backlight.h>
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_drm.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "intel_bios.h"
|
||||
#include "cdv_device.h"
|
||||
|
||||
#define VGA_SR_INDEX 0x3c4
|
||||
#define VGA_SR_DATA 0x3c5
|
||||
|
||||
/* FIXME: should check if we are the active VGA device ?? */
|
||||
static void cdv_disable_vga(struct drm_device *dev)
|
||||
{
|
||||
u8 sr1;
|
||||
u32 vga_reg;
|
||||
|
||||
vga_reg = VGACNTRL;
|
||||
|
||||
outb(1, VGA_SR_INDEX);
|
||||
sr1 = inb(VGA_SR_DATA);
|
||||
outb(sr1 | 1<<5, VGA_SR_DATA);
|
||||
udelay(300);
|
||||
|
||||
REG_WRITE(vga_reg, VGA_DISP_DISABLE);
|
||||
REG_READ(vga_reg);
|
||||
}
|
||||
|
||||
static int cdv_output_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
cdv_disable_vga(dev);
|
||||
|
||||
cdv_intel_crt_init(dev, &dev_priv->mode_dev);
|
||||
cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
|
||||
|
||||
/* These bits indicate HDMI not SDVO on CDV, but we don't yet support
|
||||
the HDMI interface */
|
||||
if (REG_READ(SDVOB) & SDVO_DETECTED)
|
||||
cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
|
||||
if (REG_READ(SDVOC) & SDVO_DETECTED)
|
||||
cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
|
||||
/*
|
||||
* Poulsbo Backlight Interfaces
|
||||
*/
|
||||
|
||||
#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
|
||||
#define BLC_PWM_FREQ_CALC_CONSTANT 32
|
||||
#define MHz 1000000
|
||||
|
||||
#define PSB_BLC_PWM_PRECISION_FACTOR 10
|
||||
#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
|
||||
#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
|
||||
|
||||
#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
|
||||
#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
|
||||
|
||||
static int cdv_brightness;
|
||||
static struct backlight_device *cdv_backlight_device;
|
||||
|
||||
static int cdv_get_brightness(struct backlight_device *bd)
|
||||
{
|
||||
/* return locally cached var instead of HW read (due to DPST etc.) */
|
||||
/* FIXME: ideally return actual value in case firmware fiddled with
|
||||
it */
|
||||
return cdv_brightness;
|
||||
}
|
||||
|
||||
|
||||
static int cdv_backlight_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long core_clock;
|
||||
/* u32 bl_max_freq; */
|
||||
/* unsigned long value; */
|
||||
u16 bl_max_freq;
|
||||
uint32_t value;
|
||||
uint32_t blc_pwm_precision_factor;
|
||||
|
||||
/* get bl_max_freq and pol from dev_priv*/
|
||||
if (!dev_priv->lvds_bl) {
|
||||
dev_err(dev->dev, "Has no valid LVDS backlight info\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
bl_max_freq = dev_priv->lvds_bl->freq;
|
||||
blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
|
||||
|
||||
core_clock = dev_priv->core_freq;
|
||||
|
||||
value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
|
||||
value *= blc_pwm_precision_factor;
|
||||
value /= bl_max_freq;
|
||||
value /= blc_pwm_precision_factor;
|
||||
|
||||
if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
|
||||
value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
|
||||
return -ERANGE;
|
||||
else {
|
||||
/* FIXME */
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdv_set_brightness(struct backlight_device *bd)
|
||||
{
|
||||
int level = bd->props.brightness;
|
||||
|
||||
/* Percentage 1-100% being valid */
|
||||
if (level < 1)
|
||||
level = 1;
|
||||
|
||||
/*cdv_intel_lvds_set_brightness(dev, level); FIXME */
|
||||
cdv_brightness = level;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct backlight_ops cdv_ops = {
|
||||
.get_brightness = cdv_get_brightness,
|
||||
.update_status = cdv_set_brightness,
|
||||
};
|
||||
|
||||
static int cdv_backlight_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
struct backlight_properties props;
|
||||
|
||||
memset(&props, 0, sizeof(struct backlight_properties));
|
||||
props.max_brightness = 100;
|
||||
props.type = BACKLIGHT_PLATFORM;
|
||||
|
||||
cdv_backlight_device = backlight_device_register("psb-bl",
|
||||
NULL, (void *)dev, &cdv_ops, &props);
|
||||
if (IS_ERR(cdv_backlight_device))
|
||||
return PTR_ERR(cdv_backlight_device);
|
||||
|
||||
ret = cdv_backlight_setup(dev);
|
||||
if (ret < 0) {
|
||||
backlight_device_unregister(cdv_backlight_device);
|
||||
cdv_backlight_device = NULL;
|
||||
return ret;
|
||||
}
|
||||
cdv_backlight_device->props.brightness = 100;
|
||||
cdv_backlight_device->props.max_brightness = 100;
|
||||
backlight_update_status(cdv_backlight_device);
|
||||
dev_priv->backlight_device = cdv_backlight_device;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Provide the Cedarview specific chip logic and low level methods
|
||||
* for power management
|
||||
*
|
||||
* FIXME: we need to implement the apm/ospm base management bits
|
||||
* for this and the MID devices.
|
||||
*/
|
||||
|
||||
static inline u32 CDV_MSG_READ32(uint port, uint offset)
|
||||
{
|
||||
int mcr = (0x10<<24) | (port << 16) | (offset << 8);
|
||||
uint32_t ret_val = 0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
||||
pci_dev_put(pci_root);
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
|
||||
{
|
||||
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD4, value);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
|
||||
#define PSB_APM_CMD 0x0
|
||||
#define PSB_APM_STS 0x04
|
||||
#define PSB_PM_SSC 0x20
|
||||
#define PSB_PM_SSS 0x30
|
||||
#define PSB_PWRGT_GFX_MASK 0x3
|
||||
#define CDV_PWRGT_DISPLAY_CNTR 0x000fc00c
|
||||
#define CDV_PWRGT_DISPLAY_STS 0x000fc00c
|
||||
|
||||
static void cdv_init_pm(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 pwr_cnt;
|
||||
int i;
|
||||
|
||||
dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
|
||||
PSB_APMBA) & 0xFFFF;
|
||||
dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
|
||||
PSB_OSPMBA) & 0xFFFF;
|
||||
|
||||
/* Force power on for now */
|
||||
pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
|
||||
pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
|
||||
|
||||
outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
|
||||
for (i = 0; i < 5; i++) {
|
||||
u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
|
||||
if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
|
||||
break;
|
||||
udelay(10);
|
||||
}
|
||||
pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
|
||||
pwr_cnt &= ~CDV_PWRGT_DISPLAY_CNTR;
|
||||
outl(pwr_cnt, dev_priv->ospm_base + PSB_PM_SSC);
|
||||
for (i = 0; i < 5; i++) {
|
||||
u32 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
|
||||
if ((pwr_sts & CDV_PWRGT_DISPLAY_STS) == 0)
|
||||
break;
|
||||
udelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* cdv_save_display_registers - save registers lost on suspend
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Save the state we need in order to be able to restore the interface
|
||||
* upon resume from suspend
|
||||
*
|
||||
* FIXME: review
|
||||
*/
|
||||
static int cdv_save_display_registers(struct drm_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdv_restore_display_registers - restore lost register state
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Restore register state that was lost during suspend and resume.
|
||||
*
|
||||
* FIXME: review
|
||||
*/
|
||||
static int cdv_restore_display_registers(struct drm_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdv_power_down(struct drm_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdv_power_up(struct drm_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* FIXME ? - shared with Poulsbo */
|
||||
static void cdv_get_core_freq(struct drm_device *dev)
|
||||
{
|
||||
uint32_t clock;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
|
||||
pci_read_config_dword(pci_root, 0xD4, &clock);
|
||||
pci_dev_put(pci_root);
|
||||
|
||||
switch (clock & 0x07) {
|
||||
case 0:
|
||||
dev_priv->core_freq = 100;
|
||||
break;
|
||||
case 1:
|
||||
dev_priv->core_freq = 133;
|
||||
break;
|
||||
case 2:
|
||||
dev_priv->core_freq = 150;
|
||||
break;
|
||||
case 3:
|
||||
dev_priv->core_freq = 178;
|
||||
break;
|
||||
case 4:
|
||||
dev_priv->core_freq = 200;
|
||||
break;
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
dev_priv->core_freq = 266;
|
||||
default:
|
||||
dev_priv->core_freq = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int cdv_chip_setup(struct drm_device *dev)
|
||||
{
|
||||
cdv_get_core_freq(dev);
|
||||
gma_intel_opregion_init(dev);
|
||||
psb_intel_init_bios(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* CDV is much like Poulsbo but has MID like SGX offsets and PM */
|
||||
|
||||
const struct psb_ops cdv_chip_ops = {
|
||||
.name = "Cedartrail",
|
||||
.accel_2d = 0,
|
||||
.pipes = 2,
|
||||
.sgx_offset = MRST_SGX_OFFSET,
|
||||
.chip_setup = cdv_chip_setup,
|
||||
|
||||
.crtc_helper = &cdv_intel_helper_funcs,
|
||||
.crtc_funcs = &cdv_intel_crtc_funcs,
|
||||
|
||||
.output_init = cdv_output_init,
|
||||
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
.backlight_init = cdv_backlight_init,
|
||||
#endif
|
||||
|
||||
.init_pm = cdv_init_pm,
|
||||
.save_regs = cdv_save_display_registers,
|
||||
.restore_regs = cdv_restore_display_registers,
|
||||
.power_down = cdv_power_down,
|
||||
.power_up = cdv_power_up,
|
||||
};
|
36
drivers/gpu/drm/gma500/cdv_device.h
Normal file
36
drivers/gpu/drm/gma500/cdv_device.h
Normal file
@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright © 2011 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
extern const struct drm_crtc_helper_funcs cdv_intel_helper_funcs;
|
||||
extern const struct drm_crtc_funcs cdv_intel_crtc_funcs;
|
||||
extern void cdv_intel_crt_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
extern void cdv_intel_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
extern void cdv_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev,
|
||||
int reg);
|
||||
extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
|
||||
struct drm_crtc *crtc);
|
||||
|
||||
extern inline void cdv_intel_wait_for_vblank(struct drm_device *dev)
|
||||
{
|
||||
/* Wait for 20ms, i.e. one cycle at 50hz. */
|
||||
/* FIXME: msleep ?? */
|
||||
mdelay(20);
|
||||
}
|
||||
|
||||
|
326
drivers/gpu/drm/gma500/cdv_intel_crt.c
Normal file
326
drivers/gpu/drm/gma500/cdv_intel_crt.c
Normal file
@ -0,0 +1,326 @@
|
||||
/*
|
||||
* Copyright © 2006-2007 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <drm/drmP.h>
|
||||
|
||||
#include "intel_bios.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "power.h"
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
|
||||
static void cdv_intel_crt_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
u32 temp, reg;
|
||||
reg = ADPA;
|
||||
|
||||
temp = REG_READ(reg);
|
||||
temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
|
||||
temp &= ~ADPA_DAC_ENABLE;
|
||||
|
||||
switch (mode) {
|
||||
case DRM_MODE_DPMS_ON:
|
||||
temp |= ADPA_DAC_ENABLE;
|
||||
break;
|
||||
case DRM_MODE_DPMS_STANDBY:
|
||||
temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
|
||||
break;
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
|
||||
break;
|
||||
case DRM_MODE_DPMS_OFF:
|
||||
temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
|
||||
break;
|
||||
}
|
||||
|
||||
REG_WRITE(reg, temp);
|
||||
}
|
||||
|
||||
static int cdv_intel_crt_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
int max_clock = 0;
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
/* The lowest clock for CDV is 20000KHz */
|
||||
if (mode->clock < 20000)
|
||||
return MODE_CLOCK_LOW;
|
||||
|
||||
/* The max clock for CDV is 355 instead of 400 */
|
||||
max_clock = 355000;
|
||||
if (mode->clock > max_clock)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
if (mode->hdisplay > 1680 || mode->vdisplay > 1050)
|
||||
return MODE_PANEL;
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
static bool cdv_intel_crt_mode_fixup(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static void cdv_intel_crt_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_crtc *crtc = encoder->crtc;
|
||||
struct psb_intel_crtc *psb_intel_crtc =
|
||||
to_psb_intel_crtc(crtc);
|
||||
int dpll_md_reg;
|
||||
u32 adpa, dpll_md;
|
||||
u32 adpa_reg;
|
||||
|
||||
if (psb_intel_crtc->pipe == 0)
|
||||
dpll_md_reg = DPLL_A_MD;
|
||||
else
|
||||
dpll_md_reg = DPLL_B_MD;
|
||||
|
||||
adpa_reg = ADPA;
|
||||
|
||||
/*
|
||||
* Disable separate mode multiplier used when cloning SDVO to CRT
|
||||
* XXX this needs to be adjusted when we really are cloning
|
||||
*/
|
||||
{
|
||||
dpll_md = REG_READ(dpll_md_reg);
|
||||
REG_WRITE(dpll_md_reg,
|
||||
dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
|
||||
}
|
||||
|
||||
adpa = 0;
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
||||
adpa |= ADPA_HSYNC_ACTIVE_HIGH;
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
||||
adpa |= ADPA_VSYNC_ACTIVE_HIGH;
|
||||
|
||||
if (psb_intel_crtc->pipe == 0)
|
||||
adpa |= ADPA_PIPE_A_SELECT;
|
||||
else
|
||||
adpa |= ADPA_PIPE_B_SELECT;
|
||||
|
||||
REG_WRITE(adpa_reg, adpa);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
|
||||
*
|
||||
* \return true if CRT is connected.
|
||||
* \return false if CRT is disconnected.
|
||||
*/
|
||||
static bool cdv_intel_crt_detect_hotplug(struct drm_connector *connector,
|
||||
bool force)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
u32 hotplug_en;
|
||||
int i, tries = 0, ret = false;
|
||||
u32 adpa_orig;
|
||||
|
||||
/* disable the DAC when doing the hotplug detection */
|
||||
|
||||
adpa_orig = REG_READ(ADPA);
|
||||
|
||||
REG_WRITE(ADPA, adpa_orig & ~(ADPA_DAC_ENABLE));
|
||||
|
||||
/*
|
||||
* On a CDV thep, CRT detect sequence need to be done twice
|
||||
* to get a reliable result.
|
||||
*/
|
||||
tries = 2;
|
||||
|
||||
hotplug_en = REG_READ(PORT_HOTPLUG_EN);
|
||||
hotplug_en &= ~(CRT_HOTPLUG_DETECT_MASK);
|
||||
hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
|
||||
|
||||
hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
|
||||
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
|
||||
|
||||
for (i = 0; i < tries ; i++) {
|
||||
unsigned long timeout;
|
||||
/* turn on the FORCE_DETECT */
|
||||
REG_WRITE(PORT_HOTPLUG_EN, hotplug_en);
|
||||
timeout = jiffies + msecs_to_jiffies(1000);
|
||||
/* wait for FORCE_DETECT to go off */
|
||||
do {
|
||||
if (!(REG_READ(PORT_HOTPLUG_EN) &
|
||||
CRT_HOTPLUG_FORCE_DETECT))
|
||||
break;
|
||||
msleep(1);
|
||||
} while (time_after(timeout, jiffies));
|
||||
}
|
||||
|
||||
if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
|
||||
CRT_HOTPLUG_MONITOR_NONE)
|
||||
ret = true;
|
||||
|
||||
/* Restore the saved ADPA */
|
||||
REG_WRITE(ADPA, adpa_orig);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static enum drm_connector_status cdv_intel_crt_detect(
|
||||
struct drm_connector *connector, bool force)
|
||||
{
|
||||
if (cdv_intel_crt_detect_hotplug(connector, force))
|
||||
return connector_status_connected;
|
||||
else
|
||||
return connector_status_disconnected;
|
||||
}
|
||||
|
||||
static void cdv_intel_crt_destroy(struct drm_connector *connector)
|
||||
{
|
||||
struct psb_intel_output *intel_output = to_psb_intel_output(connector);
|
||||
|
||||
psb_intel_i2c_destroy(intel_output->ddc_bus);
|
||||
drm_sysfs_connector_remove(connector);
|
||||
drm_connector_cleanup(connector);
|
||||
kfree(connector);
|
||||
}
|
||||
|
||||
static int cdv_intel_crt_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct psb_intel_output *intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
return psb_intel_ddc_get_modes(intel_output);
|
||||
}
|
||||
|
||||
static int cdv_intel_crt_set_property(struct drm_connector *connector,
|
||||
struct drm_property *property,
|
||||
uint64_t value)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines for controlling stuff on the analog port
|
||||
*/
|
||||
|
||||
static const struct drm_encoder_helper_funcs cdv_intel_crt_helper_funcs = {
|
||||
.dpms = cdv_intel_crt_dpms,
|
||||
.mode_fixup = cdv_intel_crt_mode_fixup,
|
||||
.prepare = psb_intel_encoder_prepare,
|
||||
.commit = psb_intel_encoder_commit,
|
||||
.mode_set = cdv_intel_crt_mode_set,
|
||||
};
|
||||
|
||||
static const struct drm_connector_funcs cdv_intel_crt_connector_funcs = {
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.detect = cdv_intel_crt_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.destroy = cdv_intel_crt_destroy,
|
||||
.set_property = cdv_intel_crt_set_property,
|
||||
};
|
||||
|
||||
static const struct drm_connector_helper_funcs
|
||||
cdv_intel_crt_connector_helper_funcs = {
|
||||
.mode_valid = cdv_intel_crt_mode_valid,
|
||||
.get_modes = cdv_intel_crt_get_modes,
|
||||
.best_encoder = psb_intel_best_encoder,
|
||||
};
|
||||
|
||||
static void cdv_intel_crt_enc_destroy(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_encoder_cleanup(encoder);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_funcs cdv_intel_crt_enc_funcs = {
|
||||
.destroy = cdv_intel_crt_enc_destroy,
|
||||
};
|
||||
|
||||
void cdv_intel_crt_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev)
|
||||
{
|
||||
|
||||
struct psb_intel_output *psb_intel_output;
|
||||
struct drm_connector *connector;
|
||||
struct drm_encoder *encoder;
|
||||
|
||||
u32 i2c_reg;
|
||||
|
||||
psb_intel_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
|
||||
if (!psb_intel_output)
|
||||
return;
|
||||
|
||||
psb_intel_output->mode_dev = mode_dev;
|
||||
connector = &psb_intel_output->base;
|
||||
drm_connector_init(dev, connector,
|
||||
&cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
|
||||
|
||||
encoder = &psb_intel_output->enc;
|
||||
drm_encoder_init(dev, encoder,
|
||||
&cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC);
|
||||
|
||||
drm_mode_connector_attach_encoder(&psb_intel_output->base,
|
||||
&psb_intel_output->enc);
|
||||
|
||||
/* Set up the DDC bus. */
|
||||
i2c_reg = GPIOA;
|
||||
/* Remove the following code for CDV */
|
||||
/*
|
||||
if (dev_priv->crt_ddc_bus != 0)
|
||||
i2c_reg = dev_priv->crt_ddc_bus;
|
||||
}*/
|
||||
psb_intel_output->ddc_bus = psb_intel_i2c_create(dev,
|
||||
i2c_reg, "CRTDDC_A");
|
||||
if (!psb_intel_output->ddc_bus) {
|
||||
dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
|
||||
"failed.\n");
|
||||
goto failed_ddc;
|
||||
}
|
||||
|
||||
psb_intel_output->type = INTEL_OUTPUT_ANALOG;
|
||||
/*
|
||||
psb_intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT);
|
||||
psb_intel_output->crtc_mask = (1 << 0) | (1 << 1);
|
||||
*/
|
||||
connector->interlace_allowed = 0;
|
||||
connector->doublescan_allowed = 0;
|
||||
|
||||
drm_encoder_helper_add(encoder, &cdv_intel_crt_helper_funcs);
|
||||
drm_connector_helper_add(connector,
|
||||
&cdv_intel_crt_connector_helper_funcs);
|
||||
|
||||
drm_sysfs_connector_add(connector);
|
||||
|
||||
return;
|
||||
failed_ddc:
|
||||
drm_encoder_cleanup(&psb_intel_output->enc);
|
||||
drm_connector_cleanup(&psb_intel_output->base);
|
||||
kfree(psb_intel_output);
|
||||
return;
|
||||
}
|
1508
drivers/gpu/drm/gma500/cdv_intel_display.c
Normal file
1508
drivers/gpu/drm/gma500/cdv_intel_display.c
Normal file
File diff suppressed because it is too large
Load Diff
376
drivers/gpu/drm/gma500/cdv_intel_hdmi.c
Normal file
376
drivers/gpu/drm/gma500/cdv_intel_hdmi.c
Normal file
@ -0,0 +1,376 @@
|
||||
/*
|
||||
* Copyright © 2006-2011 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* jim liu <jim.liu@intel.com>
|
||||
*
|
||||
* FIXME:
|
||||
* We should probably make this generic and share it with Medfield
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include <drm/drm_crtc.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
/* hdmi control bits */
|
||||
#define HDMI_NULL_PACKETS_DURING_VSYNC (1 << 9)
|
||||
#define HDMI_BORDER_ENABLE (1 << 7)
|
||||
#define HDMI_AUDIO_ENABLE (1 << 6)
|
||||
#define HDMI_VSYNC_ACTIVE_HIGH (1 << 4)
|
||||
#define HDMI_HSYNC_ACTIVE_HIGH (1 << 3)
|
||||
/* hdmi-b control bits */
|
||||
#define HDMIB_PIPE_B_SELECT (1 << 30)
|
||||
|
||||
|
||||
struct mid_intel_hdmi_priv {
|
||||
u32 hdmi_reg;
|
||||
u32 save_HDMIB;
|
||||
bool has_hdmi_sink;
|
||||
bool has_hdmi_audio;
|
||||
/* Should set this when detect hotplug */
|
||||
bool hdmi_device_connected;
|
||||
struct mdfld_hdmi_i2c *i2c_bus;
|
||||
struct i2c_adapter *hdmi_i2c_adapter; /* for control functions */
|
||||
struct drm_device *dev;
|
||||
};
|
||||
|
||||
static void cdv_hdmi_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct mid_intel_hdmi_priv *hdmi_priv = output->dev_priv;
|
||||
u32 hdmib;
|
||||
struct drm_crtc *crtc = encoder->crtc;
|
||||
struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
|
||||
|
||||
hdmib = (2 << 10);
|
||||
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
||||
hdmib |= HDMI_VSYNC_ACTIVE_HIGH;
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
||||
hdmib |= HDMI_HSYNC_ACTIVE_HIGH;
|
||||
|
||||
if (intel_crtc->pipe == 1)
|
||||
hdmib |= HDMIB_PIPE_B_SELECT;
|
||||
|
||||
if (hdmi_priv->has_hdmi_audio) {
|
||||
hdmib |= HDMI_AUDIO_ENABLE;
|
||||
hdmib |= HDMI_NULL_PACKETS_DURING_VSYNC;
|
||||
}
|
||||
|
||||
REG_WRITE(hdmi_priv->hdmi_reg, hdmib);
|
||||
REG_READ(hdmi_priv->hdmi_reg);
|
||||
}
|
||||
|
||||
static bool cdv_hdmi_mode_fixup(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static void cdv_hdmi_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct mid_intel_hdmi_priv *hdmi_priv = output->dev_priv;
|
||||
u32 hdmib;
|
||||
|
||||
hdmib = REG_READ(hdmi_priv->hdmi_reg);
|
||||
|
||||
if (mode != DRM_MODE_DPMS_ON)
|
||||
REG_WRITE(hdmi_priv->hdmi_reg, hdmib & ~HDMIB_PORT_EN);
|
||||
else
|
||||
REG_WRITE(hdmi_priv->hdmi_reg, hdmib | HDMIB_PORT_EN);
|
||||
REG_READ(hdmi_priv->hdmi_reg);
|
||||
}
|
||||
|
||||
static void cdv_hdmi_save(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct psb_intel_output *output = to_psb_intel_output(connector);
|
||||
struct mid_intel_hdmi_priv *hdmi_priv = output->dev_priv;
|
||||
|
||||
hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg);
|
||||
}
|
||||
|
||||
static void cdv_hdmi_restore(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct psb_intel_output *output = to_psb_intel_output(connector);
|
||||
struct mid_intel_hdmi_priv *hdmi_priv = output->dev_priv;
|
||||
|
||||
REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB);
|
||||
REG_READ(hdmi_priv->hdmi_reg);
|
||||
}
|
||||
|
||||
static enum drm_connector_status cdv_hdmi_detect(
|
||||
struct drm_connector *connector, bool force)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_output->dev_priv;
|
||||
struct edid *edid = NULL;
|
||||
enum drm_connector_status status = connector_status_disconnected;
|
||||
|
||||
edid = drm_get_edid(&psb_intel_output->base,
|
||||
psb_intel_output->hdmi_i2c_adapter);
|
||||
|
||||
hdmi_priv->has_hdmi_sink = false;
|
||||
hdmi_priv->has_hdmi_audio = false;
|
||||
if (edid) {
|
||||
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
|
||||
status = connector_status_connected;
|
||||
hdmi_priv->has_hdmi_sink =
|
||||
drm_detect_hdmi_monitor(edid);
|
||||
hdmi_priv->has_hdmi_audio =
|
||||
drm_detect_monitor_audio(edid);
|
||||
}
|
||||
|
||||
psb_intel_output->base.display_info.raw_edid = NULL;
|
||||
kfree(edid);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
static int cdv_hdmi_set_property(struct drm_connector *connector,
|
||||
struct drm_property *property,
|
||||
uint64_t value)
|
||||
{
|
||||
struct drm_encoder *encoder = connector->encoder;
|
||||
|
||||
if (!strcmp(property->name, "scaling mode") && encoder) {
|
||||
struct psb_intel_crtc *crtc = to_psb_intel_crtc(encoder->crtc);
|
||||
bool centre;
|
||||
uint64_t curValue;
|
||||
|
||||
if (!crtc)
|
||||
return -1;
|
||||
|
||||
switch (value) {
|
||||
case DRM_MODE_SCALE_FULLSCREEN:
|
||||
break;
|
||||
case DRM_MODE_SCALE_NO_SCALE:
|
||||
break;
|
||||
case DRM_MODE_SCALE_ASPECT:
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (drm_connector_property_get_value(connector,
|
||||
property, &curValue))
|
||||
return -1;
|
||||
|
||||
if (curValue == value)
|
||||
return 0;
|
||||
|
||||
if (drm_connector_property_set_value(connector,
|
||||
property, value))
|
||||
return -1;
|
||||
|
||||
centre = (curValue == DRM_MODE_SCALE_NO_SCALE) ||
|
||||
(value == DRM_MODE_SCALE_NO_SCALE);
|
||||
|
||||
if (crtc->saved_mode.hdisplay != 0 &&
|
||||
crtc->saved_mode.vdisplay != 0) {
|
||||
if (centre) {
|
||||
if (!drm_crtc_helper_set_mode(encoder->crtc, &crtc->saved_mode,
|
||||
encoder->crtc->x, encoder->crtc->y, encoder->crtc->fb))
|
||||
return -1;
|
||||
} else {
|
||||
struct drm_encoder_helper_funcs *helpers
|
||||
= encoder->helper_private;
|
||||
helpers->mode_set(encoder, &crtc->saved_mode,
|
||||
&crtc->saved_adjusted_mode);
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the list of HDMI DDC modes if available.
|
||||
*/
|
||||
static int cdv_hdmi_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct edid *edid = NULL;
|
||||
int ret = 0;
|
||||
|
||||
edid = drm_get_edid(&psb_intel_output->base,
|
||||
psb_intel_output->hdmi_i2c_adapter);
|
||||
if (edid) {
|
||||
drm_mode_connector_update_edid_property(&psb_intel_output->
|
||||
base, edid);
|
||||
ret = drm_add_edid_modes(&psb_intel_output->base, edid);
|
||||
kfree(edid);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cdv_hdmi_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
|
||||
if (mode->clock > 165000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
if (mode->clock < 20000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
/* just in case */
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
/* just in case */
|
||||
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
||||
return MODE_NO_INTERLACE;
|
||||
|
||||
/*
|
||||
* FIXME: for now we limit the size to 1680x1050 on CDV, otherwise it
|
||||
* will go beyond the stolen memory size allocated to the framebuffer
|
||||
*/
|
||||
if (mode->hdisplay > 1680)
|
||||
return MODE_PANEL;
|
||||
if (mode->vdisplay > 1050)
|
||||
return MODE_PANEL;
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
static void cdv_hdmi_destroy(struct drm_connector *connector)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
|
||||
if (psb_intel_output->ddc_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->ddc_bus);
|
||||
drm_sysfs_connector_remove(connector);
|
||||
drm_connector_cleanup(connector);
|
||||
kfree(connector);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs cdv_hdmi_helper_funcs = {
|
||||
.dpms = cdv_hdmi_dpms,
|
||||
.mode_fixup = cdv_hdmi_mode_fixup,
|
||||
.prepare = psb_intel_encoder_prepare,
|
||||
.mode_set = cdv_hdmi_mode_set,
|
||||
.commit = psb_intel_encoder_commit,
|
||||
};
|
||||
|
||||
static const struct drm_connector_helper_funcs
|
||||
cdv_hdmi_connector_helper_funcs = {
|
||||
.get_modes = cdv_hdmi_get_modes,
|
||||
.mode_valid = cdv_hdmi_mode_valid,
|
||||
.best_encoder = psb_intel_best_encoder,
|
||||
};
|
||||
|
||||
static const struct drm_connector_funcs cdv_hdmi_connector_funcs = {
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.save = cdv_hdmi_save,
|
||||
.restore = cdv_hdmi_restore,
|
||||
.detect = cdv_hdmi_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.set_property = cdv_hdmi_set_property,
|
||||
.destroy = cdv_hdmi_destroy,
|
||||
};
|
||||
|
||||
void cdv_hdmi_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev, int reg)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output;
|
||||
struct drm_connector *connector;
|
||||
struct drm_encoder *encoder;
|
||||
struct mid_intel_hdmi_priv *hdmi_priv;
|
||||
int ddc_bus;
|
||||
|
||||
psb_intel_output = kzalloc(sizeof(struct psb_intel_output) +
|
||||
sizeof(struct mid_intel_hdmi_priv), GFP_KERNEL);
|
||||
if (!psb_intel_output)
|
||||
return;
|
||||
|
||||
hdmi_priv = (struct mid_intel_hdmi_priv *)(psb_intel_output + 1);
|
||||
psb_intel_output->mode_dev = mode_dev;
|
||||
connector = &psb_intel_output->base;
|
||||
encoder = &psb_intel_output->enc;
|
||||
drm_connector_init(dev, &psb_intel_output->base,
|
||||
&cdv_hdmi_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_DVID);
|
||||
|
||||
drm_encoder_init(dev, &psb_intel_output->enc, &psb_intel_lvds_enc_funcs,
|
||||
DRM_MODE_ENCODER_TMDS);
|
||||
|
||||
drm_mode_connector_attach_encoder(&psb_intel_output->base,
|
||||
&psb_intel_output->enc);
|
||||
psb_intel_output->type = INTEL_OUTPUT_HDMI;
|
||||
hdmi_priv->hdmi_reg = reg;
|
||||
hdmi_priv->has_hdmi_sink = false;
|
||||
psb_intel_output->dev_priv = hdmi_priv;
|
||||
|
||||
drm_encoder_helper_add(encoder, &cdv_hdmi_helper_funcs);
|
||||
drm_connector_helper_add(connector,
|
||||
&cdv_hdmi_connector_helper_funcs);
|
||||
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = false;
|
||||
connector->doublescan_allowed = false;
|
||||
|
||||
drm_connector_attach_property(connector,
|
||||
dev->mode_config.scaling_mode_property, DRM_MODE_SCALE_FULLSCREEN);
|
||||
|
||||
switch (reg) {
|
||||
case SDVOB:
|
||||
ddc_bus = GPIOE;
|
||||
break;
|
||||
case SDVOC:
|
||||
ddc_bus = GPIOD;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("unknown reg 0x%x for HDMI\n", reg);
|
||||
goto failed_ddc;
|
||||
break;
|
||||
}
|
||||
|
||||
psb_intel_output->ddc_bus = psb_intel_i2c_create(dev,
|
||||
ddc_bus, (reg == SDVOB) ? "HDMIB" : "HDMIC");
|
||||
|
||||
if (!psb_intel_output->ddc_bus) {
|
||||
dev_err(dev->dev, "No ddc adapter available!\n");
|
||||
goto failed_ddc;
|
||||
}
|
||||
psb_intel_output->hdmi_i2c_adapter =
|
||||
&(psb_intel_output->ddc_bus->adapter);
|
||||
hdmi_priv->dev = dev;
|
||||
drm_sysfs_connector_add(connector);
|
||||
return;
|
||||
|
||||
failed_ddc:
|
||||
drm_encoder_cleanup(&psb_intel_output->enc);
|
||||
drm_connector_cleanup(&psb_intel_output->base);
|
||||
kfree(psb_intel_output);
|
||||
}
|
721
drivers/gpu/drm/gma500/cdv_intel_lvds.c
Normal file
721
drivers/gpu/drm/gma500/cdv_intel_lvds.c
Normal file
@ -0,0 +1,721 @@
|
||||
/*
|
||||
* Copyright © 2006-2011 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
* Dave Airlie <airlied@linux.ie>
|
||||
* Jesse Barnes <jesse.barnes@intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <drm/drmP.h>
|
||||
|
||||
#include "intel_bios.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "power.h"
|
||||
#include <linux/pm_runtime.h>
|
||||
#include "cdv_device.h"
|
||||
|
||||
/**
|
||||
* LVDS I2C backlight control macros
|
||||
*/
|
||||
#define BRIGHTNESS_MAX_LEVEL 100
|
||||
#define BRIGHTNESS_MASK 0xFF
|
||||
#define BLC_I2C_TYPE 0x01
|
||||
#define BLC_PWM_TYPT 0x02
|
||||
|
||||
#define BLC_POLARITY_NORMAL 0
|
||||
#define BLC_POLARITY_INVERSE 1
|
||||
|
||||
#define PSB_BLC_MAX_PWM_REG_FREQ (0xFFFE)
|
||||
#define PSB_BLC_MIN_PWM_REG_FREQ (0x2)
|
||||
#define PSB_BLC_PWM_PRECISION_FACTOR (10)
|
||||
#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
|
||||
#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
|
||||
|
||||
struct cdv_intel_lvds_priv {
|
||||
/**
|
||||
* Saved LVDO output states
|
||||
*/
|
||||
uint32_t savePP_ON;
|
||||
uint32_t savePP_OFF;
|
||||
uint32_t saveLVDS;
|
||||
uint32_t savePP_CONTROL;
|
||||
uint32_t savePP_CYCLE;
|
||||
uint32_t savePFIT_CONTROL;
|
||||
uint32_t savePFIT_PGM_RATIOS;
|
||||
uint32_t saveBLC_PWM_CTL;
|
||||
};
|
||||
|
||||
/*
|
||||
* Returns the maximum level of the backlight duty cycle field.
|
||||
*/
|
||||
static u32 cdv_intel_lvds_get_max_backlight(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 retval;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
retval = ((REG_READ(BLC_PWM_CTL) &
|
||||
BACKLIGHT_MODULATION_FREQ_MASK) >>
|
||||
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
|
||||
|
||||
gma_power_end(dev);
|
||||
} else
|
||||
retval = ((dev_priv->saveBLC_PWM_CTL &
|
||||
BACKLIGHT_MODULATION_FREQ_MASK) >>
|
||||
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set LVDS backlight level by I2C command
|
||||
*/
|
||||
static int cdv_lvds_i2c_set_brightness(struct drm_device *dev,
|
||||
unsigned int level)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_i2c_chan *lvds_i2c_bus = dev_priv->lvds_i2c_bus;
|
||||
u8 out_buf[2];
|
||||
unsigned int blc_i2c_brightness;
|
||||
|
||||
struct i2c_msg msgs[] = {
|
||||
{
|
||||
.addr = lvds_i2c_bus->slave_addr,
|
||||
.flags = 0,
|
||||
.len = 2,
|
||||
.buf = out_buf,
|
||||
}
|
||||
};
|
||||
|
||||
blc_i2c_brightness = BRIGHTNESS_MASK & ((unsigned int)level *
|
||||
BRIGHTNESS_MASK /
|
||||
BRIGHTNESS_MAX_LEVEL);
|
||||
|
||||
if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)
|
||||
blc_i2c_brightness = BRIGHTNESS_MASK - blc_i2c_brightness;
|
||||
|
||||
out_buf[0] = dev_priv->lvds_bl->brightnesscmd;
|
||||
out_buf[1] = (u8)blc_i2c_brightness;
|
||||
|
||||
if (i2c_transfer(&lvds_i2c_bus->adapter, msgs, 1) == 1)
|
||||
return 0;
|
||||
|
||||
DRM_ERROR("I2C transfer error\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static int cdv_lvds_pwm_set_brightness(struct drm_device *dev, int level)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
u32 max_pwm_blc;
|
||||
u32 blc_pwm_duty_cycle;
|
||||
|
||||
max_pwm_blc = cdv_intel_lvds_get_max_backlight(dev);
|
||||
|
||||
/*BLC_PWM_CTL Should be initiated while backlight device init*/
|
||||
BUG_ON((max_pwm_blc & PSB_BLC_MAX_PWM_REG_FREQ) == 0);
|
||||
|
||||
blc_pwm_duty_cycle = level * max_pwm_blc / BRIGHTNESS_MAX_LEVEL;
|
||||
|
||||
if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)
|
||||
blc_pwm_duty_cycle = max_pwm_blc - blc_pwm_duty_cycle;
|
||||
|
||||
blc_pwm_duty_cycle &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
|
||||
REG_WRITE(BLC_PWM_CTL,
|
||||
(max_pwm_blc << PSB_BACKLIGHT_PWM_CTL_SHIFT) |
|
||||
(blc_pwm_duty_cycle));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set LVDS backlight level either by I2C or PWM
|
||||
*/
|
||||
void cdv_intel_lvds_set_brightness(struct drm_device *dev, int level)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (!dev_priv->lvds_bl) {
|
||||
DRM_ERROR("NO LVDS Backlight Info\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (dev_priv->lvds_bl->type == BLC_I2C_TYPE)
|
||||
cdv_lvds_i2c_set_brightness(dev, level);
|
||||
else
|
||||
cdv_lvds_pwm_set_brightness(dev, level);
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the backlight level.
|
||||
*
|
||||
* level backlight level, from 0 to cdv_intel_lvds_get_max_backlight().
|
||||
*/
|
||||
static void cdv_intel_lvds_set_backlight(struct drm_device *dev, int level)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 blc_pwm_ctl;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
blc_pwm_ctl =
|
||||
REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
|
||||
REG_WRITE(BLC_PWM_CTL,
|
||||
(blc_pwm_ctl |
|
||||
(level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
|
||||
gma_power_end(dev);
|
||||
} else {
|
||||
blc_pwm_ctl = dev_priv->saveBLC_PWM_CTL &
|
||||
~BACKLIGHT_DUTY_CYCLE_MASK;
|
||||
dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl |
|
||||
(level << BACKLIGHT_DUTY_CYCLE_SHIFT));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the power state for the panel.
|
||||
*/
|
||||
static void cdv_intel_lvds_set_power(struct drm_device *dev,
|
||||
struct psb_intel_output *output, bool on)
|
||||
{
|
||||
u32 pp_status;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
if (on) {
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
|
||||
POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while ((pp_status & PP_ON) == 0);
|
||||
|
||||
cdv_intel_lvds_set_backlight(dev,
|
||||
output->
|
||||
mode_dev->backlight_duty_cycle);
|
||||
} else {
|
||||
cdv_intel_lvds_set_backlight(dev, 0);
|
||||
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
|
||||
~POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while (pp_status & PP_ON);
|
||||
}
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
static void cdv_intel_lvds_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
if (mode == DRM_MODE_DPMS_ON)
|
||||
cdv_intel_lvds_set_power(dev, output, true);
|
||||
else
|
||||
cdv_intel_lvds_set_power(dev, output, false);
|
||||
/* XXX: We never power down the LVDS pairs. */
|
||||
}
|
||||
|
||||
static void cdv_intel_lvds_save(struct drm_connector *connector)
|
||||
{
|
||||
}
|
||||
|
||||
static void cdv_intel_lvds_restore(struct drm_connector *connector)
|
||||
{
|
||||
}
|
||||
|
||||
int cdv_intel_lvds_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct drm_display_mode *fixed_mode =
|
||||
psb_intel_output->mode_dev->panel_fixed_mode;
|
||||
|
||||
/* just in case */
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
/* just in case */
|
||||
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
||||
return MODE_NO_INTERLACE;
|
||||
|
||||
if (fixed_mode) {
|
||||
if (mode->hdisplay > fixed_mode->hdisplay)
|
||||
return MODE_PANEL;
|
||||
if (mode->vdisplay > fixed_mode->vdisplay)
|
||||
return MODE_PANEL;
|
||||
}
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
bool cdv_intel_lvds_mode_fixup(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct psb_intel_mode_device *mode_dev =
|
||||
enc_to_psb_intel_output(encoder)->mode_dev;
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_encoder *tmp_encoder;
|
||||
struct drm_display_mode *panel_fixed_mode = mode_dev->panel_fixed_mode;
|
||||
|
||||
/* Should never happen!! */
|
||||
list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list,
|
||||
head) {
|
||||
if (tmp_encoder != encoder
|
||||
&& tmp_encoder->crtc == encoder->crtc) {
|
||||
printk(KERN_ERR "Can't enable LVDS and another "
|
||||
"encoder on the same pipe\n");
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If we have timings from the BIOS for the panel, put them in
|
||||
* to the adjusted mode. The CRTC will be set up for this mode,
|
||||
* with the panel scaling set up to source from the H/VDisplay
|
||||
* of the original mode.
|
||||
*/
|
||||
if (panel_fixed_mode != NULL) {
|
||||
adjusted_mode->hdisplay = panel_fixed_mode->hdisplay;
|
||||
adjusted_mode->hsync_start = panel_fixed_mode->hsync_start;
|
||||
adjusted_mode->hsync_end = panel_fixed_mode->hsync_end;
|
||||
adjusted_mode->htotal = panel_fixed_mode->htotal;
|
||||
adjusted_mode->vdisplay = panel_fixed_mode->vdisplay;
|
||||
adjusted_mode->vsync_start = panel_fixed_mode->vsync_start;
|
||||
adjusted_mode->vsync_end = panel_fixed_mode->vsync_end;
|
||||
adjusted_mode->vtotal = panel_fixed_mode->vtotal;
|
||||
adjusted_mode->clock = panel_fixed_mode->clock;
|
||||
drm_mode_set_crtcinfo(adjusted_mode,
|
||||
CRTC_INTERLACE_HALVE_V);
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX: It would be nice to support lower refresh rates on the
|
||||
* panels to reduce power consumption, and perhaps match the
|
||||
* user's requested refresh rate.
|
||||
*/
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void cdv_intel_lvds_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct psb_intel_mode_device *mode_dev = output->mode_dev;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
|
||||
mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
|
||||
BACKLIGHT_DUTY_CYCLE_MASK);
|
||||
|
||||
cdv_intel_lvds_set_power(dev, output, false);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
static void cdv_intel_lvds_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct psb_intel_mode_device *mode_dev = output->mode_dev;
|
||||
|
||||
if (mode_dev->backlight_duty_cycle == 0)
|
||||
mode_dev->backlight_duty_cycle =
|
||||
cdv_intel_lvds_get_max_backlight(dev);
|
||||
|
||||
cdv_intel_lvds_set_power(dev, output, true);
|
||||
}
|
||||
|
||||
static void cdv_intel_lvds_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 pfit_control;
|
||||
|
||||
/*
|
||||
* The LVDS pin pair will already have been turned on in the
|
||||
* cdv_intel_crtc_mode_set since it has a large impact on the DPLL
|
||||
* settings.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Enable automatic panel scaling so that non-native modes fill the
|
||||
* screen. Should be enabled before the pipe is enabled, according to
|
||||
* register description and PRM.
|
||||
*/
|
||||
if (mode->hdisplay != adjusted_mode->hdisplay ||
|
||||
mode->vdisplay != adjusted_mode->vdisplay)
|
||||
pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
|
||||
HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR |
|
||||
HORIZ_INTERP_BILINEAR);
|
||||
else
|
||||
pfit_control = 0;
|
||||
|
||||
if (dev_priv->lvds_dither)
|
||||
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
|
||||
|
||||
REG_WRITE(PFIT_CONTROL, pfit_control);
|
||||
}
|
||||
|
||||
/**
|
||||
* Detect the LVDS connection.
|
||||
*
|
||||
* This always returns CONNECTOR_STATUS_CONNECTED.
|
||||
* This connector should only have
|
||||
* been set up if the LVDS was actually connected anyway.
|
||||
*/
|
||||
static enum drm_connector_status cdv_intel_lvds_detect(
|
||||
struct drm_connector *connector, bool force)
|
||||
{
|
||||
return connector_status_connected;
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
|
||||
*/
|
||||
static int cdv_intel_lvds_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct psb_intel_mode_device *mode_dev =
|
||||
psb_intel_output->mode_dev;
|
||||
int ret;
|
||||
|
||||
ret = psb_intel_ddc_get_modes(psb_intel_output);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Didn't get an EDID, so
|
||||
* Set wide sync ranges so we get all modes
|
||||
* handed to valid_mode for checking
|
||||
*/
|
||||
connector->display_info.min_vfreq = 0;
|
||||
connector->display_info.max_vfreq = 200;
|
||||
connector->display_info.min_hfreq = 0;
|
||||
connector->display_info.max_hfreq = 200;
|
||||
if (mode_dev->panel_fixed_mode != NULL) {
|
||||
struct drm_display_mode *mode =
|
||||
drm_mode_duplicate(dev, mode_dev->panel_fixed_mode);
|
||||
drm_mode_probed_add(connector, mode);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cdv_intel_lvds_destroy - unregister and free LVDS structures
|
||||
* @connector: connector to free
|
||||
*
|
||||
* Unregister the DDC bus for this connector then free the driver private
|
||||
* structure.
|
||||
*/
|
||||
void cdv_intel_lvds_destroy(struct drm_connector *connector)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
|
||||
if (psb_intel_output->ddc_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->ddc_bus);
|
||||
drm_sysfs_connector_remove(connector);
|
||||
drm_connector_cleanup(connector);
|
||||
kfree(connector);
|
||||
}
|
||||
|
||||
int cdv_intel_lvds_set_property(struct drm_connector *connector,
|
||||
struct drm_property *property,
|
||||
uint64_t value)
|
||||
{
|
||||
struct drm_encoder *encoder = connector->encoder;
|
||||
|
||||
if (!strcmp(property->name, "scaling mode") && encoder) {
|
||||
struct psb_intel_crtc *crtc =
|
||||
to_psb_intel_crtc(encoder->crtc);
|
||||
uint64_t curValue;
|
||||
|
||||
if (!crtc)
|
||||
return -1;
|
||||
|
||||
switch (value) {
|
||||
case DRM_MODE_SCALE_FULLSCREEN:
|
||||
break;
|
||||
case DRM_MODE_SCALE_NO_SCALE:
|
||||
break;
|
||||
case DRM_MODE_SCALE_ASPECT:
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (drm_connector_property_get_value(connector,
|
||||
property,
|
||||
&curValue))
|
||||
return -1;
|
||||
|
||||
if (curValue == value)
|
||||
return 0;
|
||||
|
||||
if (drm_connector_property_set_value(connector,
|
||||
property,
|
||||
value))
|
||||
return -1;
|
||||
|
||||
if (crtc->saved_mode.hdisplay != 0 &&
|
||||
crtc->saved_mode.vdisplay != 0) {
|
||||
if (!drm_crtc_helper_set_mode(encoder->crtc,
|
||||
&crtc->saved_mode,
|
||||
encoder->crtc->x,
|
||||
encoder->crtc->y,
|
||||
encoder->crtc->fb))
|
||||
return -1;
|
||||
}
|
||||
} else if (!strcmp(property->name, "backlight") && encoder) {
|
||||
if (drm_connector_property_set_value(connector,
|
||||
property,
|
||||
value))
|
||||
return -1;
|
||||
else {
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
struct drm_psb_private *dev_priv =
|
||||
encoder->dev->dev_private;
|
||||
struct backlight_device *bd =
|
||||
dev_priv->backlight_device;
|
||||
bd->props.brightness = value;
|
||||
backlight_update_status(bd);
|
||||
#endif
|
||||
}
|
||||
} else if (!strcmp(property->name, "DPMS") && encoder) {
|
||||
struct drm_encoder_helper_funcs *helpers =
|
||||
encoder->helper_private;
|
||||
helpers->dpms(encoder, value);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs
|
||||
cdv_intel_lvds_helper_funcs = {
|
||||
.dpms = cdv_intel_lvds_encoder_dpms,
|
||||
.mode_fixup = cdv_intel_lvds_mode_fixup,
|
||||
.prepare = cdv_intel_lvds_prepare,
|
||||
.mode_set = cdv_intel_lvds_mode_set,
|
||||
.commit = cdv_intel_lvds_commit,
|
||||
};
|
||||
|
||||
static const struct drm_connector_helper_funcs
|
||||
cdv_intel_lvds_connector_helper_funcs = {
|
||||
.get_modes = cdv_intel_lvds_get_modes,
|
||||
.mode_valid = cdv_intel_lvds_mode_valid,
|
||||
.best_encoder = psb_intel_best_encoder,
|
||||
};
|
||||
|
||||
static const struct drm_connector_funcs cdv_intel_lvds_connector_funcs = {
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.save = cdv_intel_lvds_save,
|
||||
.restore = cdv_intel_lvds_restore,
|
||||
.detect = cdv_intel_lvds_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.set_property = cdv_intel_lvds_set_property,
|
||||
.destroy = cdv_intel_lvds_destroy,
|
||||
};
|
||||
|
||||
|
||||
static void cdv_intel_lvds_enc_destroy(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_encoder_cleanup(encoder);
|
||||
}
|
||||
|
||||
const struct drm_encoder_funcs cdv_intel_lvds_enc_funcs = {
|
||||
.destroy = cdv_intel_lvds_enc_destroy,
|
||||
};
|
||||
|
||||
/**
|
||||
* cdv_intel_lvds_init - setup LVDS connectors on this device
|
||||
* @dev: drm device
|
||||
*
|
||||
* Create the connector, register the LVDS DDC bus, and try to figure out what
|
||||
* modes we can display on the LVDS panel (if present).
|
||||
*/
|
||||
void cdv_intel_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output;
|
||||
struct cdv_intel_lvds_priv *lvds_priv;
|
||||
struct drm_connector *connector;
|
||||
struct drm_encoder *encoder;
|
||||
struct drm_display_mode *scan;
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 lvds;
|
||||
int pipe;
|
||||
|
||||
psb_intel_output = kzalloc(sizeof(struct psb_intel_output) +
|
||||
sizeof(struct cdv_intel_lvds_priv), GFP_KERNEL);
|
||||
if (!psb_intel_output)
|
||||
return;
|
||||
|
||||
lvds_priv = (struct cdv_intel_lvds_priv *)(psb_intel_output + 1);
|
||||
|
||||
psb_intel_output->dev_priv = lvds_priv;
|
||||
|
||||
psb_intel_output->mode_dev = mode_dev;
|
||||
connector = &psb_intel_output->base;
|
||||
encoder = &psb_intel_output->enc;
|
||||
|
||||
|
||||
drm_connector_init(dev, &psb_intel_output->base,
|
||||
&cdv_intel_lvds_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_LVDS);
|
||||
|
||||
drm_encoder_init(dev, &psb_intel_output->enc,
|
||||
&cdv_intel_lvds_enc_funcs,
|
||||
DRM_MODE_ENCODER_LVDS);
|
||||
|
||||
|
||||
drm_mode_connector_attach_encoder(&psb_intel_output->base,
|
||||
&psb_intel_output->enc);
|
||||
psb_intel_output->type = INTEL_OUTPUT_LVDS;
|
||||
|
||||
drm_encoder_helper_add(encoder, &cdv_intel_lvds_helper_funcs);
|
||||
drm_connector_helper_add(connector,
|
||||
&cdv_intel_lvds_connector_helper_funcs);
|
||||
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = false;
|
||||
connector->doublescan_allowed = false;
|
||||
|
||||
/*Attach connector properties*/
|
||||
drm_connector_attach_property(connector,
|
||||
dev->mode_config.scaling_mode_property,
|
||||
DRM_MODE_SCALE_FULLSCREEN);
|
||||
drm_connector_attach_property(connector,
|
||||
dev_priv->backlight_property,
|
||||
BRIGHTNESS_MAX_LEVEL);
|
||||
|
||||
/**
|
||||
* Set up I2C bus
|
||||
* FIXME: distroy i2c_bus when exit
|
||||
*/
|
||||
psb_intel_output->i2c_bus = psb_intel_i2c_create(dev,
|
||||
GPIOB,
|
||||
"LVDSBLC_B");
|
||||
if (!psb_intel_output->i2c_bus) {
|
||||
dev_printk(KERN_ERR,
|
||||
&dev->pdev->dev, "I2C bus registration failed.\n");
|
||||
goto failed_blc_i2c;
|
||||
}
|
||||
psb_intel_output->i2c_bus->slave_addr = 0x2C;
|
||||
dev_priv->lvds_i2c_bus = psb_intel_output->i2c_bus;
|
||||
|
||||
/*
|
||||
* LVDS discovery:
|
||||
* 1) check for EDID on DDC
|
||||
* 2) check for VBT data
|
||||
* 3) check to see if LVDS is already on
|
||||
* if none of the above, no panel
|
||||
* 4) make sure lid is open
|
||||
* if closed, act like it's not there for now
|
||||
*/
|
||||
|
||||
/* Set up the DDC bus. */
|
||||
psb_intel_output->ddc_bus = psb_intel_i2c_create(dev,
|
||||
GPIOC,
|
||||
"LVDSDDC_C");
|
||||
if (!psb_intel_output->ddc_bus) {
|
||||
dev_printk(KERN_ERR, &dev->pdev->dev,
|
||||
"DDC bus registration " "failed.\n");
|
||||
goto failed_ddc;
|
||||
}
|
||||
|
||||
/*
|
||||
* Attempt to get the fixed panel mode from DDC. Assume that the
|
||||
* preferred mode is the right one.
|
||||
*/
|
||||
psb_intel_ddc_get_modes(psb_intel_output);
|
||||
list_for_each_entry(scan, &connector->probed_modes, head) {
|
||||
if (scan->type & DRM_MODE_TYPE_PREFERRED) {
|
||||
mode_dev->panel_fixed_mode =
|
||||
drm_mode_duplicate(dev, scan);
|
||||
goto out; /* FIXME: check for quirks */
|
||||
}
|
||||
}
|
||||
|
||||
/* Failed to get EDID, what about VBT? do we need this?*/
|
||||
if (dev_priv->lfp_lvds_vbt_mode) {
|
||||
mode_dev->panel_fixed_mode =
|
||||
drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
|
||||
if (mode_dev->panel_fixed_mode) {
|
||||
mode_dev->panel_fixed_mode->type |=
|
||||
DRM_MODE_TYPE_PREFERRED;
|
||||
goto out; /* FIXME: check for quirks */
|
||||
}
|
||||
}
|
||||
/*
|
||||
* If we didn't get EDID, try checking if the panel is already turned
|
||||
* on. If so, assume that whatever is currently programmed is the
|
||||
* correct mode.
|
||||
*/
|
||||
lvds = REG_READ(LVDS);
|
||||
pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
|
||||
crtc = psb_intel_get_crtc_from_pipe(dev, pipe);
|
||||
|
||||
if (crtc && (lvds & LVDS_PORT_EN)) {
|
||||
mode_dev->panel_fixed_mode =
|
||||
cdv_intel_crtc_mode_get(dev, crtc);
|
||||
if (mode_dev->panel_fixed_mode) {
|
||||
mode_dev->panel_fixed_mode->type |=
|
||||
DRM_MODE_TYPE_PREFERRED;
|
||||
goto out; /* FIXME: check for quirks */
|
||||
}
|
||||
}
|
||||
|
||||
/* If we still don't have a mode after all that, give up. */
|
||||
if (!mode_dev->panel_fixed_mode) {
|
||||
DRM_DEBUG
|
||||
("Found no modes on the lvds, ignoring the LVDS\n");
|
||||
goto failed_find;
|
||||
}
|
||||
|
||||
out:
|
||||
drm_sysfs_connector_add(connector);
|
||||
return;
|
||||
|
||||
failed_find:
|
||||
printk(KERN_ERR "Failed find\n");
|
||||
if (psb_intel_output->ddc_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->ddc_bus);
|
||||
failed_ddc:
|
||||
printk(KERN_ERR "Failed DDC\n");
|
||||
if (psb_intel_output->i2c_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->i2c_bus);
|
||||
failed_blc_i2c:
|
||||
printk(KERN_ERR "Failed BLC\n");
|
||||
drm_encoder_cleanup(encoder);
|
||||
drm_connector_cleanup(connector);
|
||||
kfree(connector);
|
||||
}
|
784
drivers/gpu/drm/gma500/framebuffer.c
Normal file
784
drivers/gpu/drm/gma500/framebuffer.c
Normal file
@ -0,0 +1,784 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/console.h>
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include <drm/drm_crtc.h>
|
||||
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "framebuffer.h"
|
||||
|
||||
static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb);
|
||||
static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb,
|
||||
struct drm_file *file_priv,
|
||||
unsigned int *handle);
|
||||
|
||||
static const struct drm_framebuffer_funcs psb_fb_funcs = {
|
||||
.destroy = psb_user_framebuffer_destroy,
|
||||
.create_handle = psb_user_framebuffer_create_handle,
|
||||
};
|
||||
|
||||
#define CMAP_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16)
|
||||
|
||||
static int psbfb_setcolreg(unsigned regno, unsigned red, unsigned green,
|
||||
unsigned blue, unsigned transp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
struct psb_fbdev *fbdev = info->par;
|
||||
struct drm_framebuffer *fb = fbdev->psb_fb_helper.fb;
|
||||
uint32_t v;
|
||||
|
||||
if (!fb)
|
||||
return -ENOMEM;
|
||||
|
||||
if (regno > 255)
|
||||
return 1;
|
||||
|
||||
red = CMAP_TOHW(red, info->var.red.length);
|
||||
blue = CMAP_TOHW(blue, info->var.blue.length);
|
||||
green = CMAP_TOHW(green, info->var.green.length);
|
||||
transp = CMAP_TOHW(transp, info->var.transp.length);
|
||||
|
||||
v = (red << info->var.red.offset) |
|
||||
(green << info->var.green.offset) |
|
||||
(blue << info->var.blue.offset) |
|
||||
(transp << info->var.transp.offset);
|
||||
|
||||
if (regno < 16) {
|
||||
switch (fb->bits_per_pixel) {
|
||||
case 16:
|
||||
((uint32_t *) info->pseudo_palette)[regno] = v;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
((uint32_t *) info->pseudo_palette)[regno] = v;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void psbfb_suspend(struct drm_device *dev)
|
||||
{
|
||||
struct drm_framebuffer *fb = 0;
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(fb);
|
||||
|
||||
console_lock();
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
|
||||
struct fb_info *info = psbfb->fbdev;
|
||||
fb_set_suspend(info, 1);
|
||||
drm_fb_helper_blank(FB_BLANK_POWERDOWN, info);
|
||||
}
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
console_unlock();
|
||||
}
|
||||
|
||||
void psbfb_resume(struct drm_device *dev)
|
||||
{
|
||||
struct drm_framebuffer *fb = 0;
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(fb);
|
||||
|
||||
console_lock();
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
|
||||
struct fb_info *info = psbfb->fbdev;
|
||||
fb_set_suspend(info, 0);
|
||||
drm_fb_helper_blank(FB_BLANK_UNBLANK, info);
|
||||
}
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
console_unlock();
|
||||
drm_helper_disable_unused_functions(dev);
|
||||
}
|
||||
|
||||
static int psbfb_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
||||
{
|
||||
struct psb_framebuffer *psbfb = vma->vm_private_data;
|
||||
struct drm_device *dev = psbfb->base.dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int page_num;
|
||||
int i;
|
||||
unsigned long address;
|
||||
int ret;
|
||||
unsigned long pfn;
|
||||
/* FIXME: assumes fb at stolen base which may not be true */
|
||||
unsigned long phys_addr = (unsigned long)dev_priv->stolen_base;
|
||||
|
||||
page_num = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
|
||||
address = (unsigned long)vmf->virtual_address;
|
||||
|
||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||
|
||||
for (i = 0; i < page_num; i++) {
|
||||
pfn = (phys_addr >> PAGE_SHIFT);
|
||||
|
||||
ret = vm_insert_mixed(vma, address, pfn);
|
||||
if (unlikely((ret == -EBUSY) || (ret != 0 && i > 0)))
|
||||
break;
|
||||
else if (unlikely(ret != 0)) {
|
||||
ret = (ret == -ENOMEM) ? VM_FAULT_OOM : VM_FAULT_SIGBUS;
|
||||
return ret;
|
||||
}
|
||||
address += PAGE_SIZE;
|
||||
phys_addr += PAGE_SIZE;
|
||||
}
|
||||
return VM_FAULT_NOPAGE;
|
||||
}
|
||||
|
||||
static void psbfb_vm_open(struct vm_area_struct *vma)
|
||||
{
|
||||
}
|
||||
|
||||
static void psbfb_vm_close(struct vm_area_struct *vma)
|
||||
{
|
||||
}
|
||||
|
||||
static struct vm_operations_struct psbfb_vm_ops = {
|
||||
.fault = psbfb_vm_fault,
|
||||
.open = psbfb_vm_open,
|
||||
.close = psbfb_vm_close
|
||||
};
|
||||
|
||||
static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
|
||||
{
|
||||
struct psb_fbdev *fbdev = info->par;
|
||||
struct psb_framebuffer *psbfb = &fbdev->pfb;
|
||||
|
||||
if (vma->vm_pgoff != 0)
|
||||
return -EINVAL;
|
||||
if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
|
||||
return -EINVAL;
|
||||
|
||||
if (!psbfb->addr_space)
|
||||
psbfb->addr_space = vma->vm_file->f_mapping;
|
||||
/*
|
||||
* If this is a GEM object then info->screen_base is the virtual
|
||||
* kernel remapping of the object. FIXME: Review if this is
|
||||
* suitable for our mmap work
|
||||
*/
|
||||
vma->vm_ops = &psbfb_vm_ops;
|
||||
vma->vm_private_data = (void *)psbfb;
|
||||
vma->vm_flags |= VM_RESERVED | VM_IO |
|
||||
VM_MIXEDMAP | VM_DONTEXPAND;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int psbfb_ioctl(struct fb_info *info, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
static struct fb_ops psbfb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_check_var = drm_fb_helper_check_var,
|
||||
.fb_set_par = drm_fb_helper_set_par,
|
||||
.fb_blank = drm_fb_helper_blank,
|
||||
.fb_setcolreg = psbfb_setcolreg,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = psbfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_mmap = psbfb_mmap,
|
||||
.fb_sync = psbfb_sync,
|
||||
.fb_ioctl = psbfb_ioctl,
|
||||
};
|
||||
|
||||
static struct fb_ops psbfb_unaccel_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_check_var = drm_fb_helper_check_var,
|
||||
.fb_set_par = drm_fb_helper_set_par,
|
||||
.fb_blank = drm_fb_helper_blank,
|
||||
.fb_setcolreg = psbfb_setcolreg,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_mmap = psbfb_mmap,
|
||||
.fb_ioctl = psbfb_ioctl,
|
||||
};
|
||||
|
||||
/**
|
||||
* psb_framebuffer_init - initialize a framebuffer
|
||||
* @dev: our DRM device
|
||||
* @fb: framebuffer to set up
|
||||
* @mode_cmd: mode description
|
||||
* @gt: backing object
|
||||
*
|
||||
* Configure and fill in the boilerplate for our frame buffer. Return
|
||||
* 0 on success or an error code if we fail.
|
||||
*/
|
||||
static int psb_framebuffer_init(struct drm_device *dev,
|
||||
struct psb_framebuffer *fb,
|
||||
struct drm_mode_fb_cmd *mode_cmd,
|
||||
struct gtt_range *gt)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (mode_cmd->pitch & 63)
|
||||
return -EINVAL;
|
||||
switch (mode_cmd->bpp) {
|
||||
case 8:
|
||||
case 16:
|
||||
case 24:
|
||||
case 32:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = drm_framebuffer_init(dev, &fb->base, &psb_fb_funcs);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "framebuffer init failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
drm_helper_mode_fill_fb_struct(&fb->base, mode_cmd);
|
||||
fb->gtt = gt;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_framebuffer_create - create a framebuffer backed by gt
|
||||
* @dev: our DRM device
|
||||
* @mode_cmd: the description of the requested mode
|
||||
* @gt: the backing object
|
||||
*
|
||||
* Create a framebuffer object backed by the gt, and fill in the
|
||||
* boilerplate required
|
||||
*
|
||||
* TODO: review object references
|
||||
*/
|
||||
|
||||
static struct drm_framebuffer *psb_framebuffer_create
|
||||
(struct drm_device *dev,
|
||||
struct drm_mode_fb_cmd *mode_cmd,
|
||||
struct gtt_range *gt)
|
||||
{
|
||||
struct psb_framebuffer *fb;
|
||||
int ret;
|
||||
|
||||
fb = kzalloc(sizeof(*fb), GFP_KERNEL);
|
||||
if (!fb)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
ret = psb_framebuffer_init(dev, fb, mode_cmd, gt);
|
||||
if (ret) {
|
||||
kfree(fb);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
return &fb->base;
|
||||
}
|
||||
|
||||
/**
|
||||
* psbfb_alloc - allocate frame buffer memory
|
||||
* @dev: the DRM device
|
||||
* @aligned_size: space needed
|
||||
*
|
||||
* Allocate the frame buffer. In the usual case we get a GTT range that
|
||||
* is stolen memory backed and life is simple. If there isn't sufficient
|
||||
* stolen memory or the system has no stolen memory we allocate a range
|
||||
* and back it with a GEM object.
|
||||
*
|
||||
* In this case the GEM object has no handle.
|
||||
*
|
||||
* FIXME: console speed up - allocate twice the space if room and use
|
||||
* hardware scrolling for acceleration.
|
||||
*/
|
||||
static struct gtt_range *psbfb_alloc(struct drm_device *dev, int aligned_size)
|
||||
{
|
||||
struct gtt_range *backing;
|
||||
/* Begin by trying to use stolen memory backing */
|
||||
backing = psb_gtt_alloc_range(dev, aligned_size, "fb", 1);
|
||||
if (backing) {
|
||||
if (drm_gem_private_object_init(dev,
|
||||
&backing->gem, aligned_size) == 0)
|
||||
return backing;
|
||||
psb_gtt_free_range(dev, backing);
|
||||
}
|
||||
/* Next try using GEM host memory */
|
||||
backing = psb_gtt_alloc_range(dev, aligned_size, "fb(gem)", 0);
|
||||
if (backing == NULL)
|
||||
return NULL;
|
||||
|
||||
/* Now back it with an object */
|
||||
if (drm_gem_object_init(dev, &backing->gem, aligned_size) != 0) {
|
||||
psb_gtt_free_range(dev, backing);
|
||||
return NULL;
|
||||
}
|
||||
return backing;
|
||||
}
|
||||
|
||||
/**
|
||||
* psbfb_create - create a framebuffer
|
||||
* @fbdev: the framebuffer device
|
||||
* @sizes: specification of the layout
|
||||
*
|
||||
* Create a framebuffer to the specifications provided
|
||||
*/
|
||||
static int psbfb_create(struct psb_fbdev *fbdev,
|
||||
struct drm_fb_helper_surface_size *sizes)
|
||||
{
|
||||
struct drm_device *dev = fbdev->psb_fb_helper.dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct fb_info *info;
|
||||
struct drm_framebuffer *fb;
|
||||
struct psb_framebuffer *psbfb = &fbdev->pfb;
|
||||
struct drm_mode_fb_cmd mode_cmd;
|
||||
struct device *device = &dev->pdev->dev;
|
||||
int size;
|
||||
int ret;
|
||||
struct gtt_range *backing;
|
||||
|
||||
mode_cmd.width = sizes->surface_width;
|
||||
mode_cmd.height = sizes->surface_height;
|
||||
mode_cmd.bpp = sizes->surface_bpp;
|
||||
|
||||
/* No 24bit packed */
|
||||
if (mode_cmd.bpp == 24)
|
||||
mode_cmd.bpp = 32;
|
||||
|
||||
/* HW requires pitch to be 64 byte aligned */
|
||||
mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 7) / 8), 64);
|
||||
mode_cmd.depth = sizes->surface_depth;
|
||||
|
||||
size = mode_cmd.pitch * mode_cmd.height;
|
||||
size = ALIGN(size, PAGE_SIZE);
|
||||
|
||||
/* Allocate the framebuffer in the GTT with stolen page backing */
|
||||
backing = psbfb_alloc(dev, size);
|
||||
if (backing == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
info = framebuffer_alloc(0, device);
|
||||
if (!info) {
|
||||
ret = -ENOMEM;
|
||||
goto out_err1;
|
||||
}
|
||||
info->par = fbdev;
|
||||
|
||||
ret = psb_framebuffer_init(dev, psbfb, &mode_cmd, backing);
|
||||
if (ret)
|
||||
goto out_unref;
|
||||
|
||||
fb = &psbfb->base;
|
||||
psbfb->fbdev = info;
|
||||
|
||||
fbdev->psb_fb_helper.fb = fb;
|
||||
fbdev->psb_fb_helper.fbdev = info;
|
||||
|
||||
strcpy(info->fix.id, "psbfb");
|
||||
|
||||
info->flags = FBINFO_DEFAULT;
|
||||
/* No 2D engine */
|
||||
if (!dev_priv->ops->accel_2d)
|
||||
info->fbops = &psbfb_unaccel_ops;
|
||||
else
|
||||
info->fbops = &psbfb_ops;
|
||||
|
||||
ret = fb_alloc_cmap(&info->cmap, 256, 0);
|
||||
if (ret) {
|
||||
ret = -ENOMEM;
|
||||
goto out_unref;
|
||||
}
|
||||
|
||||
info->fix.smem_start = dev->mode_config.fb_base;
|
||||
info->fix.smem_len = size;
|
||||
|
||||
if (backing->stolen) {
|
||||
/* Accessed stolen memory directly */
|
||||
info->screen_base = (char *)dev_priv->vram_addr +
|
||||
backing->offset;
|
||||
} else {
|
||||
/* Pin the pages into the GTT and create a mapping to them */
|
||||
psb_gtt_pin(backing);
|
||||
info->screen_base = vm_map_ram(backing->pages, backing->npage,
|
||||
-1, PAGE_KERNEL);
|
||||
if (info->screen_base == NULL) {
|
||||
psb_gtt_unpin(backing);
|
||||
ret = -ENOMEM;
|
||||
goto out_unref;
|
||||
}
|
||||
psbfb->vm_map = 1;
|
||||
}
|
||||
info->screen_size = size;
|
||||
|
||||
if (dev_priv->gtt.stolen_size) {
|
||||
info->apertures = alloc_apertures(1);
|
||||
if (!info->apertures) {
|
||||
ret = -ENOMEM;
|
||||
goto out_unref;
|
||||
}
|
||||
info->apertures->ranges[0].base = dev->mode_config.fb_base;
|
||||
info->apertures->ranges[0].size = dev_priv->gtt.stolen_size;
|
||||
}
|
||||
|
||||
drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
|
||||
drm_fb_helper_fill_var(info, &fbdev->psb_fb_helper,
|
||||
sizes->fb_width, sizes->fb_height);
|
||||
|
||||
info->fix.mmio_start = pci_resource_start(dev->pdev, 0);
|
||||
info->fix.mmio_len = pci_resource_len(dev->pdev, 0);
|
||||
|
||||
info->pixmap.size = 64 * 1024;
|
||||
info->pixmap.buf_align = 8;
|
||||
info->pixmap.access_align = 32;
|
||||
info->pixmap.flags = FB_PIXMAP_SYSTEM;
|
||||
info->pixmap.scan_align = 1;
|
||||
|
||||
dev_info(dev->dev, "allocated %dx%d fb\n",
|
||||
psbfb->base.width, psbfb->base.height);
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
return 0;
|
||||
out_unref:
|
||||
if (backing->stolen)
|
||||
psb_gtt_free_range(dev, backing);
|
||||
else {
|
||||
if (psbfb->vm_map)
|
||||
vm_unmap_ram(info->screen_base, backing->npage);
|
||||
drm_gem_object_unreference(&backing->gem);
|
||||
}
|
||||
out_err1:
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
psb_gtt_free_range(dev, backing);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_user_framebuffer_create - create framebuffer
|
||||
* @dev: our DRM device
|
||||
* @filp: client file
|
||||
* @cmd: mode request
|
||||
*
|
||||
* Create a new framebuffer backed by a userspace GEM object
|
||||
*/
|
||||
static struct drm_framebuffer *psb_user_framebuffer_create
|
||||
(struct drm_device *dev, struct drm_file *filp,
|
||||
struct drm_mode_fb_cmd *cmd)
|
||||
{
|
||||
struct gtt_range *r;
|
||||
struct drm_gem_object *obj;
|
||||
|
||||
/*
|
||||
* Find the GEM object and thus the gtt range object that is
|
||||
* to back this space
|
||||
*/
|
||||
obj = drm_gem_object_lookup(dev, filp, cmd->handle);
|
||||
if (obj == NULL)
|
||||
return ERR_PTR(-ENOENT);
|
||||
|
||||
/* Let the core code do all the work */
|
||||
r = container_of(obj, struct gtt_range, gem);
|
||||
return psb_framebuffer_create(dev, cmd, r);
|
||||
}
|
||||
|
||||
static void psbfb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
|
||||
u16 blue, int regno)
|
||||
{
|
||||
}
|
||||
|
||||
static void psbfb_gamma_get(struct drm_crtc *crtc, u16 *red,
|
||||
u16 *green, u16 *blue, int regno)
|
||||
{
|
||||
}
|
||||
|
||||
static int psbfb_probe(struct drm_fb_helper *helper,
|
||||
struct drm_fb_helper_surface_size *sizes)
|
||||
{
|
||||
struct psb_fbdev *psb_fbdev = (struct psb_fbdev *)helper;
|
||||
int new_fb = 0;
|
||||
int ret;
|
||||
|
||||
if (!helper->fb) {
|
||||
ret = psbfb_create(psb_fbdev, sizes);
|
||||
if (ret)
|
||||
return ret;
|
||||
new_fb = 1;
|
||||
}
|
||||
return new_fb;
|
||||
}
|
||||
|
||||
struct drm_fb_helper_funcs psb_fb_helper_funcs = {
|
||||
.gamma_set = psbfb_gamma_set,
|
||||
.gamma_get = psbfb_gamma_get,
|
||||
.fb_probe = psbfb_probe,
|
||||
};
|
||||
|
||||
int psb_fbdev_destroy(struct drm_device *dev, struct psb_fbdev *fbdev)
|
||||
{
|
||||
struct fb_info *info;
|
||||
struct psb_framebuffer *psbfb = &fbdev->pfb;
|
||||
|
||||
if (fbdev->psb_fb_helper.fbdev) {
|
||||
info = fbdev->psb_fb_helper.fbdev;
|
||||
|
||||
/* If this is our base framebuffer then kill any virtual map
|
||||
for the framebuffer layer and unpin it */
|
||||
if (psbfb->vm_map) {
|
||||
vm_unmap_ram(info->screen_base, psbfb->gtt->npage);
|
||||
psb_gtt_unpin(psbfb->gtt);
|
||||
}
|
||||
unregister_framebuffer(info);
|
||||
if (info->cmap.len)
|
||||
fb_dealloc_cmap(&info->cmap);
|
||||
framebuffer_release(info);
|
||||
}
|
||||
drm_fb_helper_fini(&fbdev->psb_fb_helper);
|
||||
drm_framebuffer_cleanup(&psbfb->base);
|
||||
|
||||
if (psbfb->gtt)
|
||||
drm_gem_object_unreference(&psbfb->gtt->gem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int psb_fbdev_init(struct drm_device *dev)
|
||||
{
|
||||
struct psb_fbdev *fbdev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
fbdev = kzalloc(sizeof(struct psb_fbdev), GFP_KERNEL);
|
||||
if (!fbdev) {
|
||||
dev_err(dev->dev, "no memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dev_priv->fbdev = fbdev;
|
||||
fbdev->psb_fb_helper.funcs = &psb_fb_helper_funcs;
|
||||
|
||||
drm_fb_helper_init(dev, &fbdev->psb_fb_helper, dev_priv->ops->crtcs,
|
||||
INTELFB_CONN_LIMIT);
|
||||
|
||||
drm_fb_helper_single_add_all_connectors(&fbdev->psb_fb_helper);
|
||||
drm_fb_helper_initial_config(&fbdev->psb_fb_helper, 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psb_fbdev_fini(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (!dev_priv->fbdev)
|
||||
return;
|
||||
|
||||
psb_fbdev_destroy(dev, dev_priv->fbdev);
|
||||
kfree(dev_priv->fbdev);
|
||||
dev_priv->fbdev = NULL;
|
||||
}
|
||||
|
||||
static void psbfb_output_poll_changed(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_fbdev *fbdev = (struct psb_fbdev *)dev_priv->fbdev;
|
||||
drm_fb_helper_hotplug_event(&fbdev->psb_fb_helper);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_user_framebuffer_create_handle - add hamdle to a framebuffer
|
||||
* @fb: framebuffer
|
||||
* @file_priv: our DRM file
|
||||
* @handle: returned handle
|
||||
*
|
||||
* Our framebuffer object is a GTT range which also contains a GEM
|
||||
* object. We need to turn it into a handle for userspace. GEM will do
|
||||
* the work for us
|
||||
*/
|
||||
static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb,
|
||||
struct drm_file *file_priv,
|
||||
unsigned int *handle)
|
||||
{
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(fb);
|
||||
struct gtt_range *r = psbfb->gtt;
|
||||
return drm_gem_handle_create(file_priv, &r->gem, handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_user_framebuffer_destroy - destruct user created fb
|
||||
* @fb: framebuffer
|
||||
*
|
||||
* User framebuffers are backed by GEM objects so all we have to do is
|
||||
* clean up a bit and drop the reference, GEM will handle the fallout
|
||||
*/
|
||||
static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
||||
{
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(fb);
|
||||
struct gtt_range *r = psbfb->gtt;
|
||||
struct drm_device *dev = fb->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_fbdev *fbdev = dev_priv->fbdev;
|
||||
struct drm_crtc *crtc;
|
||||
int reset = 0;
|
||||
|
||||
/* Should never get stolen memory for a user fb */
|
||||
WARN_ON(r->stolen);
|
||||
|
||||
/* Check if we are erroneously live */
|
||||
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
|
||||
if (crtc->fb == fb)
|
||||
reset = 1;
|
||||
|
||||
if (reset)
|
||||
/*
|
||||
* Now force a sane response before we permit the DRM CRTC
|
||||
* layer to do stupid things like blank the display. Instead
|
||||
* we reset this framebuffer as if the user had forced a reset.
|
||||
* We must do this before the cleanup so that the DRM layer
|
||||
* doesn't get a chance to stick its oar in where it isn't
|
||||
* wanted.
|
||||
*/
|
||||
drm_fb_helper_restore_fbdev_mode(&fbdev->psb_fb_helper);
|
||||
|
||||
/* Let DRM do its clean up */
|
||||
drm_framebuffer_cleanup(fb);
|
||||
/* We are no longer using the resource in GEM */
|
||||
drm_gem_object_unreference_unlocked(&r->gem);
|
||||
kfree(fb);
|
||||
}
|
||||
|
||||
static const struct drm_mode_config_funcs psb_mode_funcs = {
|
||||
.fb_create = psb_user_framebuffer_create,
|
||||
.output_poll_changed = psbfb_output_poll_changed,
|
||||
};
|
||||
|
||||
static int psb_create_backlight_property(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct drm_property *backlight;
|
||||
|
||||
if (dev_priv->backlight_property)
|
||||
return 0;
|
||||
|
||||
backlight = drm_property_create(dev, DRM_MODE_PROP_RANGE,
|
||||
"backlight", 2);
|
||||
backlight->values[0] = 0;
|
||||
backlight->values[1] = 100;
|
||||
|
||||
dev_priv->backlight_property = backlight;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void psb_setup_outputs(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct drm_connector *connector;
|
||||
|
||||
drm_mode_create_scaling_mode_property(dev);
|
||||
psb_create_backlight_property(dev);
|
||||
|
||||
dev_priv->ops->output_init(dev);
|
||||
|
||||
list_for_each_entry(connector, &dev->mode_config.connector_list,
|
||||
head) {
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct drm_encoder *encoder = &psb_intel_output->enc;
|
||||
int crtc_mask = 0, clone_mask = 0;
|
||||
|
||||
/* valid crtcs */
|
||||
switch (psb_intel_output->type) {
|
||||
case INTEL_OUTPUT_ANALOG:
|
||||
crtc_mask = (1 << 0);
|
||||
clone_mask = (1 << INTEL_OUTPUT_ANALOG);
|
||||
break;
|
||||
case INTEL_OUTPUT_SDVO:
|
||||
crtc_mask = ((1 << 0) | (1 << 1));
|
||||
clone_mask = (1 << INTEL_OUTPUT_SDVO);
|
||||
break;
|
||||
case INTEL_OUTPUT_LVDS:
|
||||
if (IS_MRST(dev))
|
||||
crtc_mask = (1 << 0);
|
||||
else
|
||||
crtc_mask = (1 << 1);
|
||||
clone_mask = (1 << INTEL_OUTPUT_LVDS);
|
||||
break;
|
||||
case INTEL_OUTPUT_MIPI:
|
||||
crtc_mask = (1 << 0);
|
||||
clone_mask = (1 << INTEL_OUTPUT_MIPI);
|
||||
break;
|
||||
case INTEL_OUTPUT_MIPI2:
|
||||
crtc_mask = (1 << 2);
|
||||
clone_mask = (1 << INTEL_OUTPUT_MIPI2);
|
||||
break;
|
||||
case INTEL_OUTPUT_HDMI:
|
||||
if (IS_MFLD(dev))
|
||||
crtc_mask = (1 << 1);
|
||||
else
|
||||
crtc_mask = (1 << 0);
|
||||
clone_mask = (1 << INTEL_OUTPUT_HDMI);
|
||||
break;
|
||||
}
|
||||
encoder->possible_crtcs = crtc_mask;
|
||||
encoder->possible_clones =
|
||||
psb_intel_connector_clones(dev, clone_mask);
|
||||
}
|
||||
}
|
||||
|
||||
void psb_modeset_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
|
||||
int i;
|
||||
|
||||
drm_mode_config_init(dev);
|
||||
|
||||
dev->mode_config.min_width = 0;
|
||||
dev->mode_config.min_height = 0;
|
||||
|
||||
dev->mode_config.funcs = (void *) &psb_mode_funcs;
|
||||
|
||||
/* set memory base */
|
||||
/* MRST and PSB should use BAR 2*/
|
||||
pci_read_config_dword(dev->pdev, PSB_BSM, (u32 *)
|
||||
&(dev->mode_config.fb_base));
|
||||
|
||||
/* num pipes is 2 for PSB but 1 for Mrst */
|
||||
for (i = 0; i < dev_priv->num_pipe; i++)
|
||||
psb_intel_crtc_init(dev, i, mode_dev);
|
||||
|
||||
dev->mode_config.max_width = 2048;
|
||||
dev->mode_config.max_height = 2048;
|
||||
|
||||
psb_setup_outputs(dev);
|
||||
}
|
||||
|
||||
void psb_modeset_cleanup(struct drm_device *dev)
|
||||
{
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
drm_kms_helper_poll_fini(dev);
|
||||
psb_fbdev_fini(dev);
|
||||
drm_mode_config_cleanup(dev);
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
}
|
48
drivers/gpu/drm/gma500/framebuffer.h
Normal file
48
drivers/gpu/drm/gma500/framebuffer.h
Normal file
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2011, Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _FRAMEBUFFER_H_
|
||||
#define _FRAMEBUFFER_H_
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
|
||||
#include "psb_drv.h"
|
||||
|
||||
struct psb_framebuffer {
|
||||
struct drm_framebuffer base;
|
||||
struct address_space *addr_space;
|
||||
struct fb_info *fbdev;
|
||||
struct gtt_range *gtt;
|
||||
bool vm_map; /* True if we must undo a vm_map_ram */
|
||||
};
|
||||
|
||||
struct psb_fbdev {
|
||||
struct drm_fb_helper psb_fb_helper;
|
||||
struct psb_framebuffer pfb;
|
||||
};
|
||||
|
||||
#define to_psb_fb(x) container_of(x, struct psb_framebuffer, base)
|
||||
|
||||
extern int psb_intel_connector_clones(struct drm_device *dev, int type_mask);
|
||||
|
||||
#endif
|
||||
|
295
drivers/gpu/drm/gma500/gem.c
Normal file
295
drivers/gpu/drm/gma500/gem.c
Normal file
@ -0,0 +1,295 @@
|
||||
/*
|
||||
* psb GEM interface
|
||||
*
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors: Alan Cox
|
||||
*
|
||||
* TODO:
|
||||
* - we need to work out if the MMU is relevant (eg for
|
||||
* accelerated operations on a GEM object)
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_drm.h"
|
||||
#include "psb_drv.h"
|
||||
|
||||
int psb_gem_init_object(struct drm_gem_object *obj)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void psb_gem_free_object(struct drm_gem_object *obj)
|
||||
{
|
||||
struct gtt_range *gtt = container_of(obj, struct gtt_range, gem);
|
||||
drm_gem_object_release_wrap(obj);
|
||||
/* This must occur last as it frees up the memory of the GEM object */
|
||||
psb_gtt_free_range(obj->dev, gtt);
|
||||
}
|
||||
|
||||
int psb_gem_get_aperture(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gem_dumb_map_gtt - buffer mapping for dumb interface
|
||||
* @file: our drm client file
|
||||
* @dev: drm device
|
||||
* @handle: GEM handle to the object (from dumb_create)
|
||||
*
|
||||
* Do the necessary setup to allow the mapping of the frame buffer
|
||||
* into user memory. We don't have to do much here at the moment.
|
||||
*/
|
||||
int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
|
||||
uint32_t handle, uint64_t *offset)
|
||||
{
|
||||
int ret = 0;
|
||||
struct drm_gem_object *obj;
|
||||
|
||||
if (!(dev->driver->driver_features & DRIVER_GEM))
|
||||
return -ENODEV;
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
/* GEM does all our handle to object mapping */
|
||||
obj = drm_gem_object_lookup(dev, file, handle);
|
||||
if (obj == NULL) {
|
||||
ret = -ENOENT;
|
||||
goto unlock;
|
||||
}
|
||||
/* What validation is needed here ? */
|
||||
|
||||
/* Make it mmapable */
|
||||
if (!obj->map_list.map) {
|
||||
ret = gem_create_mmap_offset(obj);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
/* GEM should really work out the hash offsets for us */
|
||||
*offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
|
||||
out:
|
||||
drm_gem_object_unreference(obj);
|
||||
unlock:
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gem_create - create a mappable object
|
||||
* @file: the DRM file of the client
|
||||
* @dev: our device
|
||||
* @size: the size requested
|
||||
* @handlep: returned handle (opaque number)
|
||||
*
|
||||
* Create a GEM object, fill in the boilerplate and attach a handle to
|
||||
* it so that userspace can speak about it. This does the core work
|
||||
* for the various methods that do/will create GEM objects for things
|
||||
*/
|
||||
static int psb_gem_create(struct drm_file *file,
|
||||
struct drm_device *dev, uint64_t size, uint32_t *handlep)
|
||||
{
|
||||
struct gtt_range *r;
|
||||
int ret;
|
||||
u32 handle;
|
||||
|
||||
size = roundup(size, PAGE_SIZE);
|
||||
|
||||
/* Allocate our object - for now a direct gtt range which is not
|
||||
stolen memory backed */
|
||||
r = psb_gtt_alloc_range(dev, size, "gem", 0);
|
||||
if (r == NULL) {
|
||||
dev_err(dev->dev, "no memory for %lld byte GEM object\n", size);
|
||||
return -ENOSPC;
|
||||
}
|
||||
/* Initialize the extra goodies GEM needs to do all the hard work */
|
||||
if (drm_gem_object_init(dev, &r->gem, size) != 0) {
|
||||
psb_gtt_free_range(dev, r);
|
||||
/* GEM doesn't give an error code and we don't have an
|
||||
EGEMSUCKS so make something up for now - FIXME */
|
||||
dev_err(dev->dev, "GEM init failed for %lld\n", size);
|
||||
return -ENOMEM;
|
||||
}
|
||||
/* Give the object a handle so we can carry it more easily */
|
||||
ret = drm_gem_handle_create(file, &r->gem, &handle);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "GEM handle failed for %p, %lld\n",
|
||||
&r->gem, size);
|
||||
drm_gem_object_release(&r->gem);
|
||||
psb_gtt_free_range(dev, r);
|
||||
return ret;
|
||||
}
|
||||
/* We have the initial and handle reference but need only one now */
|
||||
drm_gem_object_unreference(&r->gem);
|
||||
*handlep = handle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gem_dumb_create - create a dumb buffer
|
||||
* @drm_file: our client file
|
||||
* @dev: our device
|
||||
* @args: the requested arguments copied from userspace
|
||||
*
|
||||
* Allocate a buffer suitable for use for a frame buffer of the
|
||||
* form described by user space. Give userspace a handle by which
|
||||
* to reference it.
|
||||
*/
|
||||
int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
|
||||
struct drm_mode_create_dumb *args)
|
||||
{
|
||||
args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
|
||||
args->size = args->pitch * args->height;
|
||||
return psb_gem_create(file, dev, args->size, &args->handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gem_dumb_destroy - destroy a dumb buffer
|
||||
* @file: client file
|
||||
* @dev: our DRM device
|
||||
* @handle: the object handle
|
||||
*
|
||||
* Destroy a handle that was created via psb_gem_dumb_create, at least
|
||||
* we hope it was created that way. i915 seems to assume the caller
|
||||
* does the checking but that might be worth review ! FIXME
|
||||
*/
|
||||
int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
|
||||
uint32_t handle)
|
||||
{
|
||||
/* No special work needed, drop the reference and see what falls out */
|
||||
return drm_gem_handle_delete(file, handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gem_fault - pagefault handler for GEM objects
|
||||
* @vma: the VMA of the GEM object
|
||||
* @vmf: fault detail
|
||||
*
|
||||
* Invoked when a fault occurs on an mmap of a GEM managed area. GEM
|
||||
* does most of the work for us including the actual map/unmap calls
|
||||
* but we need to do the actual page work.
|
||||
*
|
||||
* This code eventually needs to handle faulting objects in and out
|
||||
* of the GTT and repacking it when we run out of space. We can put
|
||||
* that off for now and for our simple uses
|
||||
*
|
||||
* The VMA was set up by GEM. In doing so it also ensured that the
|
||||
* vma->vm_private_data points to the GEM object that is backing this
|
||||
* mapping.
|
||||
*
|
||||
* FIXME
|
||||
*/
|
||||
int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
||||
{
|
||||
struct drm_gem_object *obj;
|
||||
struct gtt_range *r;
|
||||
int ret;
|
||||
unsigned long pfn;
|
||||
pgoff_t page_offset;
|
||||
struct drm_device *dev;
|
||||
struct drm_psb_private *dev_priv;
|
||||
|
||||
obj = vma->vm_private_data; /* GEM object */
|
||||
dev = obj->dev;
|
||||
dev_priv = dev->dev_private;
|
||||
|
||||
r = container_of(obj, struct gtt_range, gem); /* Get the gtt range */
|
||||
|
||||
/* Make sure we don't parallel update on a fault, nor move or remove
|
||||
something from beneath our feet */
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
/* For now the mmap pins the object and it stays pinned. As things
|
||||
stand that will do us no harm */
|
||||
if (r->mmapping == 0) {
|
||||
ret = psb_gtt_pin(r);
|
||||
if (ret < 0) {
|
||||
dev_err(dev->dev, "gma500: pin failed: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
r->mmapping = 1;
|
||||
}
|
||||
|
||||
/* Page relative to the VMA start - we must calculate this ourselves
|
||||
because vmf->pgoff is the fake GEM offset */
|
||||
page_offset = ((unsigned long) vmf->virtual_address - vma->vm_start)
|
||||
>> PAGE_SHIFT;
|
||||
|
||||
/* CPU view of the page, don't go via the GART for CPU writes */
|
||||
if (r->stolen)
|
||||
pfn = (dev_priv->stolen_base + r->offset) >> PAGE_SHIFT;
|
||||
else
|
||||
pfn = page_to_pfn(r->pages[page_offset]);
|
||||
ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
|
||||
|
||||
fail:
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
switch (ret) {
|
||||
case 0:
|
||||
case -ERESTARTSYS:
|
||||
case -EINTR:
|
||||
return VM_FAULT_NOPAGE;
|
||||
case -ENOMEM:
|
||||
return VM_FAULT_OOM;
|
||||
default:
|
||||
return VM_FAULT_SIGBUS;
|
||||
}
|
||||
}
|
||||
|
||||
static int psb_gem_create_stolen(struct drm_file *file, struct drm_device *dev,
|
||||
int size, u32 *handle)
|
||||
{
|
||||
struct gtt_range *gtt = psb_gtt_alloc_range(dev, size, "gem", 1);
|
||||
if (gtt == NULL)
|
||||
return -ENOMEM;
|
||||
if (drm_gem_private_object_init(dev, >t->gem, size) != 0)
|
||||
goto free_gtt;
|
||||
if (drm_gem_handle_create(file, >t->gem, handle) == 0)
|
||||
return 0;
|
||||
free_gtt:
|
||||
psb_gtt_free_range(dev, gtt);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/*
|
||||
* GEM interfaces for our specific client
|
||||
*/
|
||||
int psb_gem_create_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
{
|
||||
struct drm_psb_gem_create *args = data;
|
||||
int ret;
|
||||
if (args->flags & PSB_GEM_CREATE_STOLEN) {
|
||||
ret = psb_gem_create_stolen(file, dev, args->size,
|
||||
&args->handle);
|
||||
if (ret == 0)
|
||||
return 0;
|
||||
/* Fall throguh */
|
||||
args->flags &= ~PSB_GEM_CREATE_STOLEN;
|
||||
}
|
||||
return psb_gem_create(file, dev, args->size, &args->handle);
|
||||
}
|
||||
|
||||
int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
{
|
||||
struct drm_psb_gem_mmap *args = data;
|
||||
return dev->driver->dumb_map_offset(file, dev,
|
||||
args->handle, &args->offset);
|
||||
}
|
||||
|
89
drivers/gpu/drm/gma500/gem_glue.c
Normal file
89
drivers/gpu/drm/gma500/gem_glue.c
Normal file
@ -0,0 +1,89 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
|
||||
void drm_gem_object_release_wrap(struct drm_gem_object *obj)
|
||||
{
|
||||
/* Remove the list map if one is present */
|
||||
if (obj->map_list.map) {
|
||||
struct drm_gem_mm *mm = obj->dev->mm_private;
|
||||
struct drm_map_list *list = &obj->map_list;
|
||||
drm_ht_remove_item(&mm->offset_hash, &list->hash);
|
||||
drm_mm_put_block(list->file_offset_node);
|
||||
kfree(list->map);
|
||||
list->map = NULL;
|
||||
}
|
||||
drm_gem_object_release(obj);
|
||||
}
|
||||
|
||||
/**
|
||||
* gem_create_mmap_offset - invent an mmap offset
|
||||
* @obj: our object
|
||||
*
|
||||
* Standard implementation of offset generation for mmap as is
|
||||
* duplicated in several drivers. This belongs in GEM.
|
||||
*/
|
||||
int gem_create_mmap_offset(struct drm_gem_object *obj)
|
||||
{
|
||||
struct drm_device *dev = obj->dev;
|
||||
struct drm_gem_mm *mm = dev->mm_private;
|
||||
struct drm_map_list *list;
|
||||
struct drm_local_map *map;
|
||||
int ret;
|
||||
|
||||
list = &obj->map_list;
|
||||
list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
|
||||
if (list->map == NULL)
|
||||
return -ENOMEM;
|
||||
map = list->map;
|
||||
map->type = _DRM_GEM;
|
||||
map->size = obj->size;
|
||||
map->handle = obj;
|
||||
|
||||
list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
|
||||
obj->size / PAGE_SIZE, 0, 0);
|
||||
if (!list->file_offset_node) {
|
||||
dev_err(dev->dev, "failed to allocate offset for bo %d\n",
|
||||
obj->name);
|
||||
ret = -ENOSPC;
|
||||
goto free_it;
|
||||
}
|
||||
list->file_offset_node = drm_mm_get_block(list->file_offset_node,
|
||||
obj->size / PAGE_SIZE, 0);
|
||||
if (!list->file_offset_node) {
|
||||
ret = -ENOMEM;
|
||||
goto free_it;
|
||||
}
|
||||
list->hash.key = list->file_offset_node->start;
|
||||
ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "failed to add to map hash\n");
|
||||
goto free_mm;
|
||||
}
|
||||
return 0;
|
||||
|
||||
free_mm:
|
||||
drm_mm_put_block(list->file_offset_node);
|
||||
free_it:
|
||||
kfree(list->map);
|
||||
list->map = NULL;
|
||||
return ret;
|
||||
}
|
2
drivers/gpu/drm/gma500/gem_glue.h
Normal file
2
drivers/gpu/drm/gma500/gem_glue.h
Normal file
@ -0,0 +1,2 @@
|
||||
extern void drm_gem_object_release_wrap(struct drm_gem_object *obj);
|
||||
extern int gem_create_mmap_offset(struct drm_gem_object *obj);
|
500
drivers/gpu/drm/gma500/gtt.c
Normal file
500
drivers/gpu/drm/gma500/gtt.c
Normal file
@ -0,0 +1,500 @@
|
||||
/*
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
|
||||
* Alan Cox <alan@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include "psb_drv.h"
|
||||
|
||||
|
||||
/*
|
||||
* GTT resource allocator - manage page mappings in GTT space
|
||||
*/
|
||||
|
||||
/**
|
||||
* psb_gtt_mask_pte - generate GTT pte entry
|
||||
* @pfn: page number to encode
|
||||
* @type: type of memory in the GTT
|
||||
*
|
||||
* Set the GTT entry for the appropriate memory type.
|
||||
*/
|
||||
static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type)
|
||||
{
|
||||
uint32_t mask = PSB_PTE_VALID;
|
||||
|
||||
if (type & PSB_MMU_CACHED_MEMORY)
|
||||
mask |= PSB_PTE_CACHED;
|
||||
if (type & PSB_MMU_RO_MEMORY)
|
||||
mask |= PSB_PTE_RO;
|
||||
if (type & PSB_MMU_WO_MEMORY)
|
||||
mask |= PSB_PTE_WO;
|
||||
|
||||
return (pfn << PAGE_SHIFT) | mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_entry - find the GTT entries for a gtt_range
|
||||
* @dev: our DRM device
|
||||
* @r: our GTT range
|
||||
*
|
||||
* Given a gtt_range object return the GTT offset of the page table
|
||||
* entries for this gtt_range
|
||||
*/
|
||||
u32 *psb_gtt_entry(struct drm_device *dev, struct gtt_range *r)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long offset;
|
||||
|
||||
offset = r->resource.start - dev_priv->gtt_mem->start;
|
||||
|
||||
return dev_priv->gtt_map + (offset >> PAGE_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_insert - put an object into the GTT
|
||||
* @dev: our DRM device
|
||||
* @r: our GTT range
|
||||
*
|
||||
* Take our preallocated GTT range and insert the GEM object into
|
||||
* the GTT.
|
||||
*
|
||||
* FIXME: gtt lock ?
|
||||
*/
|
||||
static int psb_gtt_insert(struct drm_device *dev, struct gtt_range *r)
|
||||
{
|
||||
u32 *gtt_slot, pte;
|
||||
struct page **pages;
|
||||
int i;
|
||||
|
||||
if (r->pages == NULL) {
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
WARN_ON(r->stolen); /* refcount these maybe ? */
|
||||
|
||||
gtt_slot = psb_gtt_entry(dev, r);
|
||||
pages = r->pages;
|
||||
|
||||
/* Make sure changes are visible to the GPU */
|
||||
set_pages_array_uc(pages, r->npage);
|
||||
|
||||
/* Write our page entries into the GTT itself */
|
||||
for (i = 0; i < r->npage; i++) {
|
||||
pte = psb_gtt_mask_pte(page_to_pfn(*pages++), 0/*type*/);
|
||||
iowrite32(pte, gtt_slot++);
|
||||
}
|
||||
/* Make sure all the entries are set before we return */
|
||||
ioread32(gtt_slot - 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_remove - remove an object from the GTT
|
||||
* @dev: our DRM device
|
||||
* @r: our GTT range
|
||||
*
|
||||
* Remove a preallocated GTT range from the GTT. Overwrite all the
|
||||
* page table entries with the dummy page
|
||||
*/
|
||||
|
||||
static void psb_gtt_remove(struct drm_device *dev, struct gtt_range *r)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 *gtt_slot, pte;
|
||||
int i;
|
||||
|
||||
WARN_ON(r->stolen);
|
||||
|
||||
gtt_slot = psb_gtt_entry(dev, r);
|
||||
pte = psb_gtt_mask_pte(page_to_pfn(dev_priv->scratch_page), 0);
|
||||
|
||||
for (i = 0; i < r->npage; i++)
|
||||
iowrite32(pte, gtt_slot++);
|
||||
ioread32(gtt_slot - 1);
|
||||
set_pages_array_wb(r->pages, r->npage);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_attach_pages - attach and pin GEM pages
|
||||
* @gt: the gtt range
|
||||
*
|
||||
* Pin and build an in kernel list of the pages that back our GEM object.
|
||||
* While we hold this the pages cannot be swapped out
|
||||
*/
|
||||
static int psb_gtt_attach_pages(struct gtt_range *gt)
|
||||
{
|
||||
struct inode *inode;
|
||||
struct address_space *mapping;
|
||||
int i;
|
||||
struct page *p;
|
||||
int pages = gt->gem.size / PAGE_SIZE;
|
||||
|
||||
WARN_ON(gt->pages);
|
||||
|
||||
/* This is the shared memory object that backs the GEM resource */
|
||||
inode = gt->gem.filp->f_path.dentry->d_inode;
|
||||
mapping = inode->i_mapping;
|
||||
|
||||
gt->pages = kmalloc(pages * sizeof(struct page *), GFP_KERNEL);
|
||||
if (gt->pages == NULL)
|
||||
return -ENOMEM;
|
||||
gt->npage = pages;
|
||||
|
||||
for (i = 0; i < pages; i++) {
|
||||
/* FIXME: review flags later */
|
||||
p = read_cache_page_gfp(mapping, i,
|
||||
__GFP_COLD | GFP_KERNEL);
|
||||
if (IS_ERR(p))
|
||||
goto err;
|
||||
gt->pages[i] = p;
|
||||
}
|
||||
return 0;
|
||||
|
||||
err:
|
||||
while (i--)
|
||||
page_cache_release(gt->pages[i]);
|
||||
kfree(gt->pages);
|
||||
gt->pages = NULL;
|
||||
return PTR_ERR(p);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_detach_pages - attach and pin GEM pages
|
||||
* @gt: the gtt range
|
||||
*
|
||||
* Undo the effect of psb_gtt_attach_pages. At this point the pages
|
||||
* must have been removed from the GTT as they could now be paged out
|
||||
* and move bus address.
|
||||
*/
|
||||
static void psb_gtt_detach_pages(struct gtt_range *gt)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < gt->npage; i++) {
|
||||
/* FIXME: do we need to force dirty */
|
||||
set_page_dirty(gt->pages[i]);
|
||||
page_cache_release(gt->pages[i]);
|
||||
}
|
||||
kfree(gt->pages);
|
||||
gt->pages = NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_pin - pin pages into the GTT
|
||||
* @gt: range to pin
|
||||
*
|
||||
* Pin a set of pages into the GTT. The pins are refcounted so that
|
||||
* multiple pins need multiple unpins to undo.
|
||||
*
|
||||
* Non GEM backed objects treat this as a no-op as they are always GTT
|
||||
* backed objects.
|
||||
*/
|
||||
int psb_gtt_pin(struct gtt_range *gt)
|
||||
{
|
||||
int ret = 0;
|
||||
struct drm_device *dev = gt->gem.dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
mutex_lock(&dev_priv->gtt_mutex);
|
||||
|
||||
if (gt->in_gart == 0 && gt->stolen == 0) {
|
||||
ret = psb_gtt_attach_pages(gt);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
ret = psb_gtt_insert(dev, gt);
|
||||
if (ret < 0) {
|
||||
psb_gtt_detach_pages(gt);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
gt->in_gart++;
|
||||
out:
|
||||
mutex_unlock(&dev_priv->gtt_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_unpin - Drop a GTT pin requirement
|
||||
* @gt: range to pin
|
||||
*
|
||||
* Undoes the effect of psb_gtt_pin. On the last drop the GEM object
|
||||
* will be removed from the GTT which will also drop the page references
|
||||
* and allow the VM to clean up or page stuff.
|
||||
*
|
||||
* Non GEM backed objects treat this as a no-op as they are always GTT
|
||||
* backed objects.
|
||||
*/
|
||||
void psb_gtt_unpin(struct gtt_range *gt)
|
||||
{
|
||||
struct drm_device *dev = gt->gem.dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
mutex_lock(&dev_priv->gtt_mutex);
|
||||
|
||||
WARN_ON(!gt->in_gart);
|
||||
|
||||
gt->in_gart--;
|
||||
if (gt->in_gart == 0 && gt->stolen == 0) {
|
||||
psb_gtt_remove(dev, gt);
|
||||
psb_gtt_detach_pages(gt);
|
||||
}
|
||||
mutex_unlock(&dev_priv->gtt_mutex);
|
||||
}
|
||||
|
||||
/*
|
||||
* GTT resource allocator - allocate and manage GTT address space
|
||||
*/
|
||||
|
||||
/**
|
||||
* psb_gtt_alloc_range - allocate GTT address space
|
||||
* @dev: Our DRM device
|
||||
* @len: length (bytes) of address space required
|
||||
* @name: resource name
|
||||
* @backed: resource should be backed by stolen pages
|
||||
*
|
||||
* Ask the kernel core to find us a suitable range of addresses
|
||||
* to use for a GTT mapping.
|
||||
*
|
||||
* Returns a gtt_range structure describing the object, or NULL on
|
||||
* error. On successful return the resource is both allocated and marked
|
||||
* as in use.
|
||||
*/
|
||||
struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
|
||||
const char *name, int backed)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct gtt_range *gt;
|
||||
struct resource *r = dev_priv->gtt_mem;
|
||||
int ret;
|
||||
unsigned long start, end;
|
||||
|
||||
if (backed) {
|
||||
/* The start of the GTT is the stolen pages */
|
||||
start = r->start;
|
||||
end = r->start + dev_priv->gtt.stolen_size - 1;
|
||||
} else {
|
||||
/* The rest we will use for GEM backed objects */
|
||||
start = r->start + dev_priv->gtt.stolen_size;
|
||||
end = r->end;
|
||||
}
|
||||
|
||||
gt = kzalloc(sizeof(struct gtt_range), GFP_KERNEL);
|
||||
if (gt == NULL)
|
||||
return NULL;
|
||||
gt->resource.name = name;
|
||||
gt->stolen = backed;
|
||||
gt->in_gart = backed;
|
||||
/* Ensure this is set for non GEM objects */
|
||||
gt->gem.dev = dev;
|
||||
ret = allocate_resource(dev_priv->gtt_mem, >->resource,
|
||||
len, start, end, PAGE_SIZE, NULL, NULL);
|
||||
if (ret == 0) {
|
||||
gt->offset = gt->resource.start - r->start;
|
||||
return gt;
|
||||
}
|
||||
kfree(gt);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_gtt_free_range - release GTT address space
|
||||
* @dev: our DRM device
|
||||
* @gt: a mapping created with psb_gtt_alloc_range
|
||||
*
|
||||
* Release a resource that was allocated with psb_gtt_alloc_range. If the
|
||||
* object has been pinned by mmap users we clean this up here currently.
|
||||
*/
|
||||
void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt)
|
||||
{
|
||||
/* Undo the mmap pin if we are destroying the object */
|
||||
if (gt->mmapping) {
|
||||
psb_gtt_unpin(gt);
|
||||
gt->mmapping = 0;
|
||||
}
|
||||
WARN_ON(gt->in_gart && !gt->stolen);
|
||||
release_resource(>->resource);
|
||||
kfree(gt);
|
||||
}
|
||||
|
||||
void psb_gtt_alloc(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
init_rwsem(&dev_priv->gtt.sem);
|
||||
}
|
||||
|
||||
void psb_gtt_takedown(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (dev_priv->gtt_map) {
|
||||
iounmap(dev_priv->gtt_map);
|
||||
dev_priv->gtt_map = NULL;
|
||||
}
|
||||
if (dev_priv->gtt_initialized) {
|
||||
pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
|
||||
dev_priv->gmch_ctrl);
|
||||
PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);
|
||||
(void) PSB_RVDC32(PSB_PGETBL_CTL);
|
||||
}
|
||||
if (dev_priv->vram_addr)
|
||||
iounmap(dev_priv->gtt_map);
|
||||
}
|
||||
|
||||
int psb_gtt_init(struct drm_device *dev, int resume)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned gtt_pages;
|
||||
unsigned long stolen_size, vram_stolen_size;
|
||||
unsigned i, num_pages;
|
||||
unsigned pfn_base;
|
||||
uint32_t vram_pages;
|
||||
uint32_t dvmt_mode = 0;
|
||||
struct psb_gtt *pg;
|
||||
|
||||
int ret = 0;
|
||||
uint32_t pte;
|
||||
|
||||
mutex_init(&dev_priv->gtt_mutex);
|
||||
|
||||
psb_gtt_alloc(dev);
|
||||
pg = &dev_priv->gtt;
|
||||
|
||||
/* Enable the GTT */
|
||||
pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
|
||||
pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
|
||||
dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
|
||||
|
||||
dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
|
||||
PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
|
||||
(void) PSB_RVDC32(PSB_PGETBL_CTL);
|
||||
|
||||
/* The root resource we allocate address space from */
|
||||
dev_priv->gtt_initialized = 1;
|
||||
|
||||
pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;
|
||||
|
||||
/*
|
||||
* FIXME: video mmu has hw bug to access 0x0D0000000,
|
||||
* then make gatt start at 0x0e000,0000
|
||||
*/
|
||||
pg->mmu_gatt_start = 0xE0000000;
|
||||
|
||||
pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
|
||||
gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE)
|
||||
>> PAGE_SHIFT;
|
||||
/* CDV workaround */
|
||||
if (pg->gtt_start == 0 || gtt_pages == 0) {
|
||||
dev_err(dev->dev, "GTT PCI BAR not initialized.\n");
|
||||
gtt_pages = 64;
|
||||
pg->gtt_start = dev_priv->pge_ctl;
|
||||
}
|
||||
|
||||
pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
|
||||
pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
|
||||
>> PAGE_SHIFT;
|
||||
dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE];
|
||||
|
||||
if (pg->gatt_pages == 0 || pg->gatt_start == 0) {
|
||||
static struct resource fudge; /* Preferably peppermint */
|
||||
|
||||
/* This can occur on CDV SDV systems. Fudge it in this case.
|
||||
We really don't care what imaginary space is being allocated
|
||||
at this point */
|
||||
dev_err(dev->dev, "GATT PCI BAR not initialized.\n");
|
||||
pg->gatt_start = 0x40000000;
|
||||
pg->gatt_pages = (128 * 1024 * 1024) >> PAGE_SHIFT;
|
||||
fudge.start = 0x40000000;
|
||||
fudge.end = 0x40000000 + 128 * 1024 * 1024 - 1;
|
||||
fudge.name = "fudge";
|
||||
fudge.flags = IORESOURCE_MEM;
|
||||
dev_priv->gtt_mem = &fudge;
|
||||
}
|
||||
|
||||
pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
|
||||
vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base
|
||||
- PAGE_SIZE;
|
||||
|
||||
stolen_size = vram_stolen_size;
|
||||
|
||||
printk(KERN_INFO "Stolen memory information\n");
|
||||
printk(KERN_INFO " base in RAM: 0x%x\n", dev_priv->stolen_base);
|
||||
printk(KERN_INFO " size: %luK, calculated by (GTT RAM base) - (Stolen base), seems wrong\n",
|
||||
vram_stolen_size/1024);
|
||||
dvmt_mode = (dev_priv->gmch_ctrl >> 4) & 0x7;
|
||||
printk(KERN_INFO " the correct size should be: %dM(dvmt mode=%d)\n",
|
||||
(dvmt_mode == 1) ? 1 : (2 << (dvmt_mode - 1)), dvmt_mode);
|
||||
|
||||
if (resume && (gtt_pages != pg->gtt_pages) &&
|
||||
(stolen_size != pg->stolen_size)) {
|
||||
dev_err(dev->dev, "GTT resume error.\n");
|
||||
ret = -EINVAL;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
pg->gtt_pages = gtt_pages;
|
||||
pg->stolen_size = stolen_size;
|
||||
dev_priv->vram_stolen_size = vram_stolen_size;
|
||||
|
||||
/*
|
||||
* Map the GTT and the stolen memory area
|
||||
*/
|
||||
dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start,
|
||||
gtt_pages << PAGE_SHIFT);
|
||||
if (!dev_priv->gtt_map) {
|
||||
dev_err(dev->dev, "Failure to map gtt.\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base, stolen_size);
|
||||
if (!dev_priv->vram_addr) {
|
||||
dev_err(dev->dev, "Failure to map stolen base.\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Insert vram stolen pages into the GTT
|
||||
*/
|
||||
|
||||
pfn_base = dev_priv->stolen_base >> PAGE_SHIFT;
|
||||
vram_pages = num_pages = vram_stolen_size >> PAGE_SHIFT;
|
||||
printk(KERN_INFO"Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n",
|
||||
num_pages, pfn_base << PAGE_SHIFT, 0);
|
||||
for (i = 0; i < num_pages; ++i) {
|
||||
pte = psb_gtt_mask_pte(pfn_base + i, 0);
|
||||
iowrite32(pte, dev_priv->gtt_map + i);
|
||||
}
|
||||
|
||||
/*
|
||||
* Init rest of GTT to the scratch page to avoid accidents or scribbles
|
||||
*/
|
||||
|
||||
pfn_base = page_to_pfn(dev_priv->scratch_page);
|
||||
pte = psb_gtt_mask_pte(pfn_base, 0);
|
||||
for (; i < gtt_pages; ++i)
|
||||
iowrite32(pte, dev_priv->gtt_map + i);
|
||||
|
||||
(void) ioread32(dev_priv->gtt_map + i - 1);
|
||||
return 0;
|
||||
|
||||
out_err:
|
||||
psb_gtt_takedown(dev);
|
||||
return ret;
|
||||
}
|
61
drivers/gpu/drm/gma500/gtt.h
Normal file
61
drivers/gpu/drm/gma500/gtt.h
Normal file
@ -0,0 +1,61 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007-2008, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef _PSB_GTT_H_
|
||||
#define _PSB_GTT_H_
|
||||
|
||||
#include <drm/drmP.h>
|
||||
|
||||
/* This wants cleaning up with respect to the psb_dev and un-needed stuff */
|
||||
struct psb_gtt {
|
||||
uint32_t gatt_start;
|
||||
uint32_t mmu_gatt_start;
|
||||
uint32_t gtt_start;
|
||||
uint32_t gtt_phys_start;
|
||||
unsigned gtt_pages;
|
||||
unsigned gatt_pages;
|
||||
unsigned long stolen_size;
|
||||
unsigned long vram_stolen_size;
|
||||
struct rw_semaphore sem;
|
||||
};
|
||||
|
||||
/* Exported functions */
|
||||
extern int psb_gtt_init(struct drm_device *dev, int resume);
|
||||
extern void psb_gtt_takedown(struct drm_device *dev);
|
||||
|
||||
/* Each gtt_range describes an allocation in the GTT area */
|
||||
struct gtt_range {
|
||||
struct resource resource; /* Resource for our allocation */
|
||||
u32 offset; /* GTT offset of our object */
|
||||
struct drm_gem_object gem; /* GEM high level stuff */
|
||||
int in_gart; /* Currently in the GART (ref ct) */
|
||||
bool stolen; /* Backed from stolen RAM */
|
||||
bool mmapping; /* Is mmappable */
|
||||
struct page **pages; /* Backing pages if present */
|
||||
int npage; /* Number of backing pages */
|
||||
};
|
||||
|
||||
extern struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
|
||||
const char *name, int backed);
|
||||
extern void psb_gtt_kref_put(struct gtt_range *gt);
|
||||
extern void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt);
|
||||
extern int psb_gtt_pin(struct gtt_range *gt);
|
||||
extern void psb_gtt_unpin(struct gtt_range *gt);
|
||||
|
||||
#endif
|
303
drivers/gpu/drm/gma500/intel_bios.c
Normal file
303
drivers/gpu/drm/gma500/intel_bios.c
Normal file
@ -0,0 +1,303 @@
|
||||
/*
|
||||
* Copyright (c) 2006 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*
|
||||
*/
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_drm.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "intel_bios.h"
|
||||
|
||||
|
||||
static void *find_section(struct bdb_header *bdb, int section_id)
|
||||
{
|
||||
u8 *base = (u8 *)bdb;
|
||||
int index = 0;
|
||||
u16 total, current_size;
|
||||
u8 current_id;
|
||||
|
||||
/* skip to first section */
|
||||
index += bdb->header_size;
|
||||
total = bdb->bdb_size;
|
||||
|
||||
/* walk the sections looking for section_id */
|
||||
while (index < total) {
|
||||
current_id = *(base + index);
|
||||
index++;
|
||||
current_size = *((u16 *)(base + index));
|
||||
index += 2;
|
||||
if (current_id == section_id)
|
||||
return base + index;
|
||||
index += current_size;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
|
||||
struct lvds_dvo_timing *dvo_timing)
|
||||
{
|
||||
panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
|
||||
dvo_timing->hactive_lo;
|
||||
panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
|
||||
((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
|
||||
panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
|
||||
dvo_timing->hsync_pulse_width;
|
||||
panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
|
||||
((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
|
||||
|
||||
panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
|
||||
dvo_timing->vactive_lo;
|
||||
panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
|
||||
dvo_timing->vsync_off;
|
||||
panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
|
||||
dvo_timing->vsync_pulse_width;
|
||||
panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
|
||||
((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
|
||||
panel_fixed_mode->clock = dvo_timing->clock * 10;
|
||||
panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
|
||||
|
||||
/* Some VBTs have bogus h/vtotal values */
|
||||
if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
|
||||
panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
|
||||
if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
|
||||
panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
|
||||
|
||||
drm_mode_set_name(panel_fixed_mode);
|
||||
}
|
||||
|
||||
static void parse_backlight_data(struct drm_psb_private *dev_priv,
|
||||
struct bdb_header *bdb)
|
||||
{
|
||||
struct bdb_lvds_backlight *vbt_lvds_bl = NULL;
|
||||
struct bdb_lvds_backlight *lvds_bl;
|
||||
u8 p_type = 0;
|
||||
void *bl_start = NULL;
|
||||
struct bdb_lvds_options *lvds_opts
|
||||
= find_section(bdb, BDB_LVDS_OPTIONS);
|
||||
|
||||
dev_priv->lvds_bl = NULL;
|
||||
|
||||
if (lvds_opts)
|
||||
p_type = lvds_opts->panel_type;
|
||||
else
|
||||
return;
|
||||
|
||||
bl_start = find_section(bdb, BDB_LVDS_BACKLIGHT);
|
||||
vbt_lvds_bl = (struct bdb_lvds_backlight *)(bl_start + 1) + p_type;
|
||||
|
||||
lvds_bl = kzalloc(sizeof(*vbt_lvds_bl), GFP_KERNEL);
|
||||
if (!lvds_bl) {
|
||||
dev_err(dev_priv->dev->dev, "out of memory for backlight data\n");
|
||||
return;
|
||||
}
|
||||
memcpy(lvds_bl, vbt_lvds_bl, sizeof(*vbt_lvds_bl));
|
||||
dev_priv->lvds_bl = lvds_bl;
|
||||
}
|
||||
|
||||
/* Try to find integrated panel data */
|
||||
static void parse_lfp_panel_data(struct drm_psb_private *dev_priv,
|
||||
struct bdb_header *bdb)
|
||||
{
|
||||
struct bdb_lvds_options *lvds_options;
|
||||
struct bdb_lvds_lfp_data *lvds_lfp_data;
|
||||
struct bdb_lvds_lfp_data_entry *entry;
|
||||
struct lvds_dvo_timing *dvo_timing;
|
||||
struct drm_display_mode *panel_fixed_mode;
|
||||
|
||||
/* Defaults if we can't find VBT info */
|
||||
dev_priv->lvds_dither = 0;
|
||||
dev_priv->lvds_vbt = 0;
|
||||
|
||||
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
|
||||
if (!lvds_options)
|
||||
return;
|
||||
|
||||
dev_priv->lvds_dither = lvds_options->pixel_dither;
|
||||
if (lvds_options->panel_type == 0xff)
|
||||
return;
|
||||
|
||||
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
|
||||
if (!lvds_lfp_data)
|
||||
return;
|
||||
|
||||
|
||||
entry = &lvds_lfp_data->data[lvds_options->panel_type];
|
||||
dvo_timing = &entry->dvo_timing;
|
||||
|
||||
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode),
|
||||
GFP_KERNEL);
|
||||
if (panel_fixed_mode == NULL) {
|
||||
dev_err(dev_priv->dev->dev, "out of memory for fixed panel mode\n");
|
||||
return;
|
||||
}
|
||||
|
||||
dev_priv->lvds_vbt = 1;
|
||||
fill_detail_timing_data(panel_fixed_mode, dvo_timing);
|
||||
|
||||
if (panel_fixed_mode->htotal > 0 && panel_fixed_mode->vtotal > 0) {
|
||||
dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
|
||||
drm_mode_debug_printmodeline(panel_fixed_mode);
|
||||
} else {
|
||||
dev_dbg(dev_priv->dev->dev, "ignoring invalid LVDS VBT\n");
|
||||
dev_priv->lvds_vbt = 0;
|
||||
kfree(panel_fixed_mode);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* Try to find sdvo panel data */
|
||||
static void parse_sdvo_panel_data(struct drm_psb_private *dev_priv,
|
||||
struct bdb_header *bdb)
|
||||
{
|
||||
struct bdb_sdvo_lvds_options *sdvo_lvds_options;
|
||||
struct lvds_dvo_timing *dvo_timing;
|
||||
struct drm_display_mode *panel_fixed_mode;
|
||||
|
||||
dev_priv->sdvo_lvds_vbt_mode = NULL;
|
||||
|
||||
sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
|
||||
if (!sdvo_lvds_options)
|
||||
return;
|
||||
|
||||
dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
|
||||
if (!dvo_timing)
|
||||
return;
|
||||
|
||||
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
|
||||
|
||||
if (!panel_fixed_mode)
|
||||
return;
|
||||
|
||||
fill_detail_timing_data(panel_fixed_mode,
|
||||
dvo_timing + sdvo_lvds_options->panel_type);
|
||||
|
||||
dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void parse_general_features(struct drm_psb_private *dev_priv,
|
||||
struct bdb_header *bdb)
|
||||
{
|
||||
struct bdb_general_features *general;
|
||||
|
||||
/* Set sensible defaults in case we can't find the general block */
|
||||
dev_priv->int_tv_support = 1;
|
||||
dev_priv->int_crt_support = 1;
|
||||
|
||||
general = find_section(bdb, BDB_GENERAL_FEATURES);
|
||||
if (general) {
|
||||
dev_priv->int_tv_support = general->int_tv_support;
|
||||
dev_priv->int_crt_support = general->int_crt_support;
|
||||
dev_priv->lvds_use_ssc = general->enable_ssc;
|
||||
|
||||
if (dev_priv->lvds_use_ssc) {
|
||||
dev_priv->lvds_ssc_freq
|
||||
= general->ssc_freq ? 100 : 96;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_intel_init_bios - initialize VBIOS settings & find VBT
|
||||
* @dev: DRM device
|
||||
*
|
||||
* Loads the Video BIOS and checks that the VBT exists. Sets scratch registers
|
||||
* to appropriate values.
|
||||
*
|
||||
* VBT existence is a sanity check that is relied on by other i830_bios.c code.
|
||||
* Note that it would be better to use a BIOS call to get the VBT, as BIOSes may
|
||||
* feed an updated VBT back through that, compared to what we'll fetch using
|
||||
* this method of groping around in the BIOS data.
|
||||
*
|
||||
* Returns 0 on success, nonzero on failure.
|
||||
*/
|
||||
bool psb_intel_init_bios(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct pci_dev *pdev = dev->pdev;
|
||||
struct vbt_header *vbt = NULL;
|
||||
struct bdb_header *bdb;
|
||||
u8 __iomem *bios;
|
||||
size_t size;
|
||||
int i;
|
||||
|
||||
bios = pci_map_rom(pdev, &size);
|
||||
if (!bios)
|
||||
return -1;
|
||||
|
||||
/* Scour memory looking for the VBT signature */
|
||||
for (i = 0; i + 4 < size; i++) {
|
||||
if (!memcmp(bios + i, "$VBT", 4)) {
|
||||
vbt = (struct vbt_header *)(bios + i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!vbt) {
|
||||
dev_err(dev->dev, "VBT signature missing\n");
|
||||
pci_unmap_rom(pdev, bios);
|
||||
return -1;
|
||||
}
|
||||
|
||||
bdb = (struct bdb_header *)(bios + i + vbt->bdb_offset);
|
||||
|
||||
/* Grab useful general definitions */
|
||||
parse_general_features(dev_priv, bdb);
|
||||
parse_lfp_panel_data(dev_priv, bdb);
|
||||
parse_sdvo_panel_data(dev_priv, bdb);
|
||||
parse_backlight_data(dev_priv, bdb);
|
||||
|
||||
pci_unmap_rom(pdev, bios);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Destroy and free VBT data
|
||||
*/
|
||||
void psb_intel_destroy_bios(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct drm_display_mode *sdvo_lvds_vbt_mode =
|
||||
dev_priv->sdvo_lvds_vbt_mode;
|
||||
struct drm_display_mode *lfp_lvds_vbt_mode =
|
||||
dev_priv->lfp_lvds_vbt_mode;
|
||||
struct bdb_lvds_backlight *lvds_bl =
|
||||
dev_priv->lvds_bl;
|
||||
|
||||
/*free sdvo panel mode*/
|
||||
if (sdvo_lvds_vbt_mode) {
|
||||
dev_priv->sdvo_lvds_vbt_mode = NULL;
|
||||
kfree(sdvo_lvds_vbt_mode);
|
||||
}
|
||||
|
||||
if (lfp_lvds_vbt_mode) {
|
||||
dev_priv->lfp_lvds_vbt_mode = NULL;
|
||||
kfree(lfp_lvds_vbt_mode);
|
||||
}
|
||||
|
||||
if (lvds_bl) {
|
||||
dev_priv->lvds_bl = NULL;
|
||||
kfree(lvds_bl);
|
||||
}
|
||||
}
|
430
drivers/gpu/drm/gma500/intel_bios.h
Normal file
430
drivers/gpu/drm/gma500/intel_bios.h
Normal file
@ -0,0 +1,430 @@
|
||||
/*
|
||||
* Copyright (c) 2006 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _I830_BIOS_H_
|
||||
#define _I830_BIOS_H_
|
||||
|
||||
#include <drm/drmP.h>
|
||||
|
||||
struct vbt_header {
|
||||
u8 signature[20]; /**< Always starts with 'VBT$' */
|
||||
u16 version; /**< decimal */
|
||||
u16 header_size; /**< in bytes */
|
||||
u16 vbt_size; /**< in bytes */
|
||||
u8 vbt_checksum;
|
||||
u8 reserved0;
|
||||
u32 bdb_offset; /**< from beginning of VBT */
|
||||
u32 aim_offset[4]; /**< from beginning of VBT */
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
struct bdb_header {
|
||||
u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
|
||||
u16 version; /**< decimal */
|
||||
u16 header_size; /**< in bytes */
|
||||
u16 bdb_size; /**< in bytes */
|
||||
};
|
||||
|
||||
/* strictly speaking, this is a "skip" block, but it has interesting info */
|
||||
struct vbios_data {
|
||||
u8 type; /* 0 == desktop, 1 == mobile */
|
||||
u8 relstage;
|
||||
u8 chipset;
|
||||
u8 lvds_present:1;
|
||||
u8 tv_present:1;
|
||||
u8 rsvd2:6; /* finish byte */
|
||||
u8 rsvd3[4];
|
||||
u8 signon[155];
|
||||
u8 copyright[61];
|
||||
u16 code_segment;
|
||||
u8 dos_boot_mode;
|
||||
u8 bandwidth_percent;
|
||||
u8 rsvd4; /* popup memory size */
|
||||
u8 resize_pci_bios;
|
||||
u8 rsvd5; /* is crt already on ddc2 */
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* There are several types of BIOS data blocks (BDBs), each block has
|
||||
* an ID and size in the first 3 bytes (ID in first, size in next 2).
|
||||
* Known types are listed below.
|
||||
*/
|
||||
#define BDB_GENERAL_FEATURES 1
|
||||
#define BDB_GENERAL_DEFINITIONS 2
|
||||
#define BDB_OLD_TOGGLE_LIST 3
|
||||
#define BDB_MODE_SUPPORT_LIST 4
|
||||
#define BDB_GENERIC_MODE_TABLE 5
|
||||
#define BDB_EXT_MMIO_REGS 6
|
||||
#define BDB_SWF_IO 7
|
||||
#define BDB_SWF_MMIO 8
|
||||
#define BDB_DOT_CLOCK_TABLE 9
|
||||
#define BDB_MODE_REMOVAL_TABLE 10
|
||||
#define BDB_CHILD_DEVICE_TABLE 11
|
||||
#define BDB_DRIVER_FEATURES 12
|
||||
#define BDB_DRIVER_PERSISTENCE 13
|
||||
#define BDB_EXT_TABLE_PTRS 14
|
||||
#define BDB_DOT_CLOCK_OVERRIDE 15
|
||||
#define BDB_DISPLAY_SELECT 16
|
||||
/* 17 rsvd */
|
||||
#define BDB_DRIVER_ROTATION 18
|
||||
#define BDB_DISPLAY_REMOVE 19
|
||||
#define BDB_OEM_CUSTOM 20
|
||||
#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
|
||||
#define BDB_SDVO_LVDS_OPTIONS 22
|
||||
#define BDB_SDVO_PANEL_DTDS 23
|
||||
#define BDB_SDVO_LVDS_PNP_IDS 24
|
||||
#define BDB_SDVO_LVDS_POWER_SEQ 25
|
||||
#define BDB_TV_OPTIONS 26
|
||||
#define BDB_LVDS_OPTIONS 40
|
||||
#define BDB_LVDS_LFP_DATA_PTRS 41
|
||||
#define BDB_LVDS_LFP_DATA 42
|
||||
#define BDB_LVDS_BACKLIGHT 43
|
||||
#define BDB_LVDS_POWER 44
|
||||
#define BDB_SKIP 254 /* VBIOS private block, ignore */
|
||||
|
||||
struct bdb_general_features {
|
||||
/* bits 1 */
|
||||
u8 panel_fitting:2;
|
||||
u8 flexaim:1;
|
||||
u8 msg_enable:1;
|
||||
u8 clear_screen:3;
|
||||
u8 color_flip:1;
|
||||
|
||||
/* bits 2 */
|
||||
u8 download_ext_vbt:1;
|
||||
u8 enable_ssc:1;
|
||||
u8 ssc_freq:1;
|
||||
u8 enable_lfp_on_override:1;
|
||||
u8 disable_ssc_ddt:1;
|
||||
u8 rsvd8:3; /* finish byte */
|
||||
|
||||
/* bits 3 */
|
||||
u8 disable_smooth_vision:1;
|
||||
u8 single_dvi:1;
|
||||
u8 rsvd9:6; /* finish byte */
|
||||
|
||||
/* bits 4 */
|
||||
u8 legacy_monitor_detect;
|
||||
|
||||
/* bits 5 */
|
||||
u8 int_crt_support:1;
|
||||
u8 int_tv_support:1;
|
||||
u8 rsvd11:6; /* finish byte */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_general_definitions {
|
||||
/* DDC GPIO */
|
||||
u8 crt_ddc_gmbus_pin;
|
||||
|
||||
/* DPMS bits */
|
||||
u8 dpms_acpi:1;
|
||||
u8 skip_boot_crt_detect:1;
|
||||
u8 dpms_aim:1;
|
||||
u8 rsvd1:5; /* finish byte */
|
||||
|
||||
/* boot device bits */
|
||||
u8 boot_display[2];
|
||||
u8 child_dev_size;
|
||||
|
||||
/* device info */
|
||||
u8 tv_or_lvds_info[33];
|
||||
u8 dev1[33];
|
||||
u8 dev2[33];
|
||||
u8 dev3[33];
|
||||
u8 dev4[33];
|
||||
/* may be another device block here on some platforms */
|
||||
};
|
||||
|
||||
struct bdb_lvds_options {
|
||||
u8 panel_type;
|
||||
u8 rsvd1;
|
||||
/* LVDS capabilities, stored in a dword */
|
||||
u8 pfit_mode:2;
|
||||
u8 pfit_text_mode_enhanced:1;
|
||||
u8 pfit_gfx_mode_enhanced:1;
|
||||
u8 pfit_ratio_auto:1;
|
||||
u8 pixel_dither:1;
|
||||
u8 lvds_edid:1;
|
||||
u8 rsvd2:1;
|
||||
u8 rsvd4;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_backlight {
|
||||
u8 type:2;
|
||||
u8 pol:1;
|
||||
u8 gpio:3;
|
||||
u8 gmbus:2;
|
||||
u16 freq;
|
||||
u8 minbrightness;
|
||||
u8 i2caddr;
|
||||
u8 brightnesscmd;
|
||||
/*FIXME: more...*/
|
||||
} __attribute__((packed));
|
||||
|
||||
/* LFP pointer table contains entries to the struct below */
|
||||
struct bdb_lvds_lfp_data_ptr {
|
||||
u16 fp_timing_offset; /* offsets are from start of bdb */
|
||||
u8 fp_table_size;
|
||||
u16 dvo_timing_offset;
|
||||
u8 dvo_table_size;
|
||||
u16 panel_pnp_id_offset;
|
||||
u8 pnp_table_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_lfp_data_ptrs {
|
||||
u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
|
||||
struct bdb_lvds_lfp_data_ptr ptr[16];
|
||||
} __attribute__((packed));
|
||||
|
||||
/* LFP data has 3 blocks per entry */
|
||||
struct lvds_fp_timing {
|
||||
u16 x_res;
|
||||
u16 y_res;
|
||||
u32 lvds_reg;
|
||||
u32 lvds_reg_val;
|
||||
u32 pp_on_reg;
|
||||
u32 pp_on_reg_val;
|
||||
u32 pp_off_reg;
|
||||
u32 pp_off_reg_val;
|
||||
u32 pp_cycle_reg;
|
||||
u32 pp_cycle_reg_val;
|
||||
u32 pfit_reg;
|
||||
u32 pfit_reg_val;
|
||||
u16 terminator;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct lvds_dvo_timing {
|
||||
u16 clock; /**< In 10khz */
|
||||
u8 hactive_lo;
|
||||
u8 hblank_lo;
|
||||
u8 hblank_hi:4;
|
||||
u8 hactive_hi:4;
|
||||
u8 vactive_lo;
|
||||
u8 vblank_lo;
|
||||
u8 vblank_hi:4;
|
||||
u8 vactive_hi:4;
|
||||
u8 hsync_off_lo;
|
||||
u8 hsync_pulse_width;
|
||||
u8 vsync_pulse_width:4;
|
||||
u8 vsync_off:4;
|
||||
u8 rsvd0:6;
|
||||
u8 hsync_off_hi:2;
|
||||
u8 h_image;
|
||||
u8 v_image;
|
||||
u8 max_hv;
|
||||
u8 h_border;
|
||||
u8 v_border;
|
||||
u8 rsvd1:3;
|
||||
u8 digital:2;
|
||||
u8 vsync_positive:1;
|
||||
u8 hsync_positive:1;
|
||||
u8 rsvd2:1;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct lvds_pnp_id {
|
||||
u16 mfg_name;
|
||||
u16 product_code;
|
||||
u32 serial;
|
||||
u8 mfg_week;
|
||||
u8 mfg_year;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_lfp_data_entry {
|
||||
struct lvds_fp_timing fp_timing;
|
||||
struct lvds_dvo_timing dvo_timing;
|
||||
struct lvds_pnp_id pnp_id;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_lfp_data {
|
||||
struct bdb_lvds_lfp_data_entry data[16];
|
||||
} __attribute__((packed));
|
||||
|
||||
struct aimdb_header {
|
||||
char signature[16];
|
||||
char oem_device[20];
|
||||
u16 aimdb_version;
|
||||
u16 aimdb_header_size;
|
||||
u16 aimdb_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct aimdb_block {
|
||||
u8 aimdb_id;
|
||||
u16 aimdb_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct vch_panel_data {
|
||||
u16 fp_timing_offset;
|
||||
u8 fp_timing_size;
|
||||
u16 dvo_timing_offset;
|
||||
u8 dvo_timing_size;
|
||||
u16 text_fitting_offset;
|
||||
u8 text_fitting_size;
|
||||
u16 graphics_fitting_offset;
|
||||
u8 graphics_fitting_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct vch_bdb_22 {
|
||||
struct aimdb_block aimdb_block;
|
||||
struct vch_panel_data panels[16];
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_sdvo_lvds_options {
|
||||
u8 panel_backlight;
|
||||
u8 h40_set_panel_type;
|
||||
u8 panel_type;
|
||||
u8 ssc_clk_freq;
|
||||
u16 als_low_trip;
|
||||
u16 als_high_trip;
|
||||
u8 sclalarcoeff_tab_row_num;
|
||||
u8 sclalarcoeff_tab_row_size;
|
||||
u8 coefficient[8];
|
||||
u8 panel_misc_bits_1;
|
||||
u8 panel_misc_bits_2;
|
||||
u8 panel_misc_bits_3;
|
||||
u8 panel_misc_bits_4;
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
extern bool psb_intel_init_bios(struct drm_device *dev);
|
||||
extern void psb_intel_destroy_bios(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* Driver<->VBIOS interaction occurs through scratch bits in
|
||||
* GR18 & SWF*.
|
||||
*/
|
||||
|
||||
/* GR18 bits are set on display switch and hotkey events */
|
||||
#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
|
||||
#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
|
||||
#define GR18_HK_NONE (0x0<<3)
|
||||
#define GR18_HK_LFP_STRETCH (0x1<<3)
|
||||
#define GR18_HK_TOGGLE_DISP (0x2<<3)
|
||||
#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
|
||||
#define GR18_HK_POPUP_DISABLED (0x6<<3)
|
||||
#define GR18_HK_POPUP_ENABLED (0x7<<3)
|
||||
#define GR18_HK_PFIT (0x8<<3)
|
||||
#define GR18_HK_APM_CHANGE (0xa<<3)
|
||||
#define GR18_HK_MULTIPLE (0xc<<3)
|
||||
#define GR18_USER_INT_EN (1<<2)
|
||||
#define GR18_A0000_FLUSH_EN (1<<1)
|
||||
#define GR18_SMM_EN (1<<0)
|
||||
|
||||
/* Set by driver, cleared by VBIOS */
|
||||
#define SWF00_YRES_SHIFT 16
|
||||
#define SWF00_XRES_SHIFT 0
|
||||
#define SWF00_RES_MASK 0xffff
|
||||
|
||||
/* Set by VBIOS at boot time and driver at runtime */
|
||||
#define SWF01_TV2_FORMAT_SHIFT 8
|
||||
#define SWF01_TV1_FORMAT_SHIFT 0
|
||||
#define SWF01_TV_FORMAT_MASK 0xffff
|
||||
|
||||
#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
|
||||
#define SWF10_GTT_OVERRIDE_EN (1<<28)
|
||||
#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
|
||||
#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
|
||||
#define SWF10_OLD_TOGGLE 0x0
|
||||
#define SWF10_TOGGLE_LIST_1 0x1
|
||||
#define SWF10_TOGGLE_LIST_2 0x2
|
||||
#define SWF10_TOGGLE_LIST_3 0x3
|
||||
#define SWF10_TOGGLE_LIST_4 0x4
|
||||
#define SWF10_PANNING_EN (1<<23)
|
||||
#define SWF10_DRIVER_LOADED (1<<22)
|
||||
#define SWF10_EXTENDED_DESKTOP (1<<21)
|
||||
#define SWF10_EXCLUSIVE_MODE (1<<20)
|
||||
#define SWF10_OVERLAY_EN (1<<19)
|
||||
#define SWF10_PLANEB_HOLDOFF (1<<18)
|
||||
#define SWF10_PLANEA_HOLDOFF (1<<17)
|
||||
#define SWF10_VGA_HOLDOFF (1<<16)
|
||||
#define SWF10_ACTIVE_DISP_MASK 0xffff
|
||||
#define SWF10_PIPEB_LFP2 (1<<15)
|
||||
#define SWF10_PIPEB_EFP2 (1<<14)
|
||||
#define SWF10_PIPEB_TV2 (1<<13)
|
||||
#define SWF10_PIPEB_CRT2 (1<<12)
|
||||
#define SWF10_PIPEB_LFP (1<<11)
|
||||
#define SWF10_PIPEB_EFP (1<<10)
|
||||
#define SWF10_PIPEB_TV (1<<9)
|
||||
#define SWF10_PIPEB_CRT (1<<8)
|
||||
#define SWF10_PIPEA_LFP2 (1<<7)
|
||||
#define SWF10_PIPEA_EFP2 (1<<6)
|
||||
#define SWF10_PIPEA_TV2 (1<<5)
|
||||
#define SWF10_PIPEA_CRT2 (1<<4)
|
||||
#define SWF10_PIPEA_LFP (1<<3)
|
||||
#define SWF10_PIPEA_EFP (1<<2)
|
||||
#define SWF10_PIPEA_TV (1<<1)
|
||||
#define SWF10_PIPEA_CRT (1<<0)
|
||||
|
||||
#define SWF11_MEMORY_SIZE_SHIFT 16
|
||||
#define SWF11_SV_TEST_EN (1<<15)
|
||||
#define SWF11_IS_AGP (1<<14)
|
||||
#define SWF11_DISPLAY_HOLDOFF (1<<13)
|
||||
#define SWF11_DPMS_REDUCED (1<<12)
|
||||
#define SWF11_IS_VBE_MODE (1<<11)
|
||||
#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
|
||||
#define SWF11_DPMS_MASK 0x07
|
||||
#define SWF11_DPMS_OFF (1<<2)
|
||||
#define SWF11_DPMS_SUSPEND (1<<1)
|
||||
#define SWF11_DPMS_STANDBY (1<<0)
|
||||
#define SWF11_DPMS_ON 0
|
||||
|
||||
#define SWF14_GFX_PFIT_EN (1<<31)
|
||||
#define SWF14_TEXT_PFIT_EN (1<<30)
|
||||
#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
|
||||
#define SWF14_POPUP_EN (1<<28)
|
||||
#define SWF14_DISPLAY_HOLDOFF (1<<27)
|
||||
#define SWF14_DISP_DETECT_EN (1<<26)
|
||||
#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
|
||||
#define SWF14_DRIVER_STATUS (1<<24)
|
||||
#define SWF14_OS_TYPE_WIN9X (1<<23)
|
||||
#define SWF14_OS_TYPE_WINNT (1<<22)
|
||||
/* 21:19 rsvd */
|
||||
#define SWF14_PM_TYPE_MASK 0x00070000
|
||||
#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
|
||||
#define SWF14_PM_ACPI (0x3 << 16)
|
||||
#define SWF14_PM_APM_12 (0x2 << 16)
|
||||
#define SWF14_PM_APM_11 (0x1 << 16)
|
||||
#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
|
||||
/* if GR18 indicates a display switch */
|
||||
#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
|
||||
#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
|
||||
#define SWF14_DS_PIPEB_TV2_EN (1<<13)
|
||||
#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
|
||||
#define SWF14_DS_PIPEB_LFP_EN (1<<11)
|
||||
#define SWF14_DS_PIPEB_EFP_EN (1<<10)
|
||||
#define SWF14_DS_PIPEB_TV_EN (1<<9)
|
||||
#define SWF14_DS_PIPEB_CRT_EN (1<<8)
|
||||
#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
|
||||
#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
|
||||
#define SWF14_DS_PIPEA_TV2_EN (1<<5)
|
||||
#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
|
||||
#define SWF14_DS_PIPEA_LFP_EN (1<<3)
|
||||
#define SWF14_DS_PIPEA_EFP_EN (1<<2)
|
||||
#define SWF14_DS_PIPEA_TV_EN (1<<1)
|
||||
#define SWF14_DS_PIPEA_CRT_EN (1<<0)
|
||||
/* if GR18 indicates a panel fitting request */
|
||||
#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
|
||||
/* if GR18 indicates an APM change request */
|
||||
#define SWF14_APM_HIBERNATE 0x4
|
||||
#define SWF14_APM_SUSPEND 0x3
|
||||
#define SWF14_APM_STANDBY 0x1
|
||||
#define SWF14_APM_RESTORE 0x0
|
||||
|
||||
#endif /* _I830_BIOS_H_ */
|
169
drivers/gpu/drm/gma500/intel_i2c.c
Normal file
169
drivers/gpu/drm/gma500/intel_i2c.c
Normal file
@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright © 2006-2007 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*/
|
||||
#include <linux/export.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-algo-bit.h>
|
||||
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
|
||||
/*
|
||||
* Intel GPIO access functions
|
||||
*/
|
||||
|
||||
#define I2C_RISEFALL_TIME 20
|
||||
|
||||
static int get_clock(void *data)
|
||||
{
|
||||
struct psb_intel_i2c_chan *chan = data;
|
||||
struct drm_device *dev = chan->drm_dev;
|
||||
u32 val;
|
||||
|
||||
val = REG_READ(chan->reg);
|
||||
return (val & GPIO_CLOCK_VAL_IN) != 0;
|
||||
}
|
||||
|
||||
static int get_data(void *data)
|
||||
{
|
||||
struct psb_intel_i2c_chan *chan = data;
|
||||
struct drm_device *dev = chan->drm_dev;
|
||||
u32 val;
|
||||
|
||||
val = REG_READ(chan->reg);
|
||||
return (val & GPIO_DATA_VAL_IN) != 0;
|
||||
}
|
||||
|
||||
static void set_clock(void *data, int state_high)
|
||||
{
|
||||
struct psb_intel_i2c_chan *chan = data;
|
||||
struct drm_device *dev = chan->drm_dev;
|
||||
u32 reserved = 0, clock_bits;
|
||||
|
||||
/* On most chips, these bits must be preserved in software. */
|
||||
reserved =
|
||||
REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
|
||||
GPIO_CLOCK_PULLUP_DISABLE);
|
||||
|
||||
if (state_high)
|
||||
clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
|
||||
else
|
||||
clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
|
||||
GPIO_CLOCK_VAL_MASK;
|
||||
REG_WRITE(chan->reg, reserved | clock_bits);
|
||||
udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
|
||||
}
|
||||
|
||||
static void set_data(void *data, int state_high)
|
||||
{
|
||||
struct psb_intel_i2c_chan *chan = data;
|
||||
struct drm_device *dev = chan->drm_dev;
|
||||
u32 reserved = 0, data_bits;
|
||||
|
||||
/* On most chips, these bits must be preserved in software. */
|
||||
reserved =
|
||||
REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |
|
||||
GPIO_CLOCK_PULLUP_DISABLE);
|
||||
|
||||
if (state_high)
|
||||
data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
|
||||
else
|
||||
data_bits =
|
||||
GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
|
||||
GPIO_DATA_VAL_MASK;
|
||||
|
||||
REG_WRITE(chan->reg, reserved | data_bits);
|
||||
udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
|
||||
* @dev: DRM device
|
||||
* @output: driver specific output device
|
||||
* @reg: GPIO reg to use
|
||||
* @name: name for this bus
|
||||
*
|
||||
* Creates and registers a new i2c bus with the Linux i2c layer, for use
|
||||
* in output probing and control (e.g. DDC or SDVO control functions).
|
||||
*
|
||||
* Possible values for @reg include:
|
||||
* %GPIOA
|
||||
* %GPIOB
|
||||
* %GPIOC
|
||||
* %GPIOD
|
||||
* %GPIOE
|
||||
* %GPIOF
|
||||
* %GPIOG
|
||||
* %GPIOH
|
||||
* see PRM for details on how these different busses are used.
|
||||
*/
|
||||
struct psb_intel_i2c_chan *psb_intel_i2c_create(struct drm_device *dev,
|
||||
const u32 reg, const char *name)
|
||||
{
|
||||
struct psb_intel_i2c_chan *chan;
|
||||
|
||||
chan = kzalloc(sizeof(struct psb_intel_i2c_chan), GFP_KERNEL);
|
||||
if (!chan)
|
||||
goto out_free;
|
||||
|
||||
chan->drm_dev = dev;
|
||||
chan->reg = reg;
|
||||
snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name);
|
||||
chan->adapter.owner = THIS_MODULE;
|
||||
chan->adapter.algo_data = &chan->algo;
|
||||
chan->adapter.dev.parent = &dev->pdev->dev;
|
||||
chan->algo.setsda = set_data;
|
||||
chan->algo.setscl = set_clock;
|
||||
chan->algo.getsda = get_data;
|
||||
chan->algo.getscl = get_clock;
|
||||
chan->algo.udelay = 20;
|
||||
chan->algo.timeout = usecs_to_jiffies(2200);
|
||||
chan->algo.data = chan;
|
||||
|
||||
i2c_set_adapdata(&chan->adapter, chan);
|
||||
|
||||
if (i2c_bit_add_bus(&chan->adapter))
|
||||
goto out_free;
|
||||
|
||||
/* JJJ: raise SCL and SDA? */
|
||||
set_data(chan, 1);
|
||||
set_clock(chan, 1);
|
||||
udelay(20);
|
||||
|
||||
return chan;
|
||||
|
||||
out_free:
|
||||
kfree(chan);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_intel_i2c_destroy - unregister and free i2c bus resources
|
||||
* @output: channel to free
|
||||
*
|
||||
* Unregister the adapter from the i2c layer, then free the structure.
|
||||
*/
|
||||
void psb_intel_i2c_destroy(struct psb_intel_i2c_chan *chan)
|
||||
{
|
||||
if (!chan)
|
||||
return;
|
||||
|
||||
i2c_del_adapter(&chan->adapter);
|
||||
kfree(chan);
|
||||
}
|
80
drivers/gpu/drm/gma500/intel_opregion.c
Normal file
80
drivers/gpu/drm/gma500/intel_opregion.c
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright 2010 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "psb_drv.h"
|
||||
|
||||
struct opregion_header {
|
||||
u8 signature[16];
|
||||
u32 size;
|
||||
u32 opregion_ver;
|
||||
u8 bios_ver[32];
|
||||
u8 vbios_ver[16];
|
||||
u8 driver_ver[16];
|
||||
u32 mboxes;
|
||||
u8 reserved[164];
|
||||
} __packed;
|
||||
|
||||
struct opregion_apci {
|
||||
/*FIXME: add it later*/
|
||||
} __packed;
|
||||
|
||||
struct opregion_swsci {
|
||||
/*FIXME: add it later*/
|
||||
} __packed;
|
||||
|
||||
struct opregion_acpi {
|
||||
/*FIXME: add it later*/
|
||||
} __packed;
|
||||
|
||||
int gma_intel_opregion_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 opregion_phy;
|
||||
void *base;
|
||||
u32 *lid_state;
|
||||
|
||||
dev_priv->lid_state = NULL;
|
||||
|
||||
pci_read_config_dword(dev->pdev, 0xfc, &opregion_phy);
|
||||
if (opregion_phy == 0)
|
||||
return -ENOTSUPP;
|
||||
|
||||
base = ioremap(opregion_phy, 8*1024);
|
||||
if (!base)
|
||||
return -ENOMEM;
|
||||
|
||||
lid_state = base + 0x01ac;
|
||||
|
||||
dev_priv->lid_state = lid_state;
|
||||
dev_priv->lid_last_state = readl(lid_state);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gma_intel_opregion_exit(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
if (dev_priv->lid_state)
|
||||
iounmap(dev_priv->lid_state);
|
||||
return 0;
|
||||
}
|
243
drivers/gpu/drm/gma500/mid_bios.c
Normal file
243
drivers/gpu/drm/gma500/mid_bios.c
Normal file
@ -0,0 +1,243 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/* TODO
|
||||
* - Split functions by vbt type
|
||||
* - Make them all take drm_device
|
||||
* - Check ioremap failures
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_drm.h"
|
||||
#include "psb_drv.h"
|
||||
#include "mid_bios.h"
|
||||
|
||||
static void mid_get_fuse_settings(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
uint32_t fuse_value = 0;
|
||||
uint32_t fuse_value_tmp = 0;
|
||||
|
||||
#define FB_REG06 0xD0810600
|
||||
#define FB_MIPI_DISABLE (1 << 11)
|
||||
#define FB_REG09 0xD0810900
|
||||
#define FB_REG09 0xD0810900
|
||||
#define FB_SKU_MASK 0x7000
|
||||
#define FB_SKU_SHIFT 12
|
||||
#define FB_SKU_100 0
|
||||
#define FB_SKU_100L 1
|
||||
#define FB_SKU_83 2
|
||||
pci_write_config_dword(pci_root, 0xD0, FB_REG06);
|
||||
pci_read_config_dword(pci_root, 0xD4, &fuse_value);
|
||||
|
||||
/* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
|
||||
if (IS_MRST(dev))
|
||||
dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
|
||||
|
||||
DRM_INFO("internal display is %s\n",
|
||||
dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
|
||||
|
||||
/* Prevent runtime suspend at start*/
|
||||
if (dev_priv->iLVDS_enable) {
|
||||
dev_priv->is_lvds_on = true;
|
||||
dev_priv->is_mipi_on = false;
|
||||
} else {
|
||||
dev_priv->is_mipi_on = true;
|
||||
dev_priv->is_lvds_on = false;
|
||||
}
|
||||
|
||||
dev_priv->video_device_fuse = fuse_value;
|
||||
|
||||
pci_write_config_dword(pci_root, 0xD0, FB_REG09);
|
||||
pci_read_config_dword(pci_root, 0xD4, &fuse_value);
|
||||
|
||||
dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
|
||||
fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
|
||||
|
||||
dev_priv->fuse_reg_value = fuse_value;
|
||||
|
||||
switch (fuse_value_tmp) {
|
||||
case FB_SKU_100:
|
||||
dev_priv->core_freq = 200;
|
||||
break;
|
||||
case FB_SKU_100L:
|
||||
dev_priv->core_freq = 100;
|
||||
break;
|
||||
case FB_SKU_83:
|
||||
dev_priv->core_freq = 166;
|
||||
break;
|
||||
default:
|
||||
dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
|
||||
fuse_value_tmp);
|
||||
dev_priv->core_freq = 0;
|
||||
}
|
||||
dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the revison ID, B0:D2:F0;0x08
|
||||
*/
|
||||
static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
|
||||
{
|
||||
uint32_t platform_rev_id = 0;
|
||||
struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
|
||||
|
||||
pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
|
||||
dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
|
||||
pci_dev_put(pci_gfx_root);
|
||||
dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
|
||||
dev_priv->platform_rev_id);
|
||||
}
|
||||
|
||||
static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
|
||||
{
|
||||
struct drm_device *dev = dev_priv->dev;
|
||||
struct oaktrail_vbt *vbt = &dev_priv->vbt_data;
|
||||
u32 addr;
|
||||
u16 new_size;
|
||||
u8 *vbt_virtual;
|
||||
u8 bpi;
|
||||
u8 number_desc = 0;
|
||||
struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
|
||||
struct gct_r10_timing_info ti;
|
||||
void *pGCT;
|
||||
struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
|
||||
|
||||
/* Get the address of the platform config vbt, B0:D2:F0;0xFC */
|
||||
pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
|
||||
pci_dev_put(pci_gfx_root);
|
||||
|
||||
dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
|
||||
|
||||
/* check for platform config address == 0. */
|
||||
/* this means fw doesn't support vbt */
|
||||
|
||||
if (addr == 0) {
|
||||
vbt->size = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* get the virtual address of the vbt */
|
||||
vbt_virtual = ioremap(addr, sizeof(*vbt));
|
||||
|
||||
memcpy(vbt, vbt_virtual, sizeof(*vbt));
|
||||
iounmap(vbt_virtual); /* Free virtual address space */
|
||||
|
||||
dev_dbg(dev->dev, "GCT revision is %x\n", vbt->revision);
|
||||
|
||||
switch (vbt->revision) {
|
||||
case 0:
|
||||
vbt->oaktrail_gct = ioremap(addr + sizeof(*vbt) - 4,
|
||||
vbt->size - sizeof(*vbt) + 4);
|
||||
pGCT = vbt->oaktrail_gct;
|
||||
bpi = ((struct oaktrail_gct_v1 *)pGCT)->PD.BootPanelIndex;
|
||||
dev_priv->gct_data.bpi = bpi;
|
||||
dev_priv->gct_data.pt =
|
||||
((struct oaktrail_gct_v1 *)pGCT)->PD.PanelType;
|
||||
memcpy(&dev_priv->gct_data.DTD,
|
||||
&((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].DTD,
|
||||
sizeof(struct oaktrail_timing_info));
|
||||
dev_priv->gct_data.Panel_Port_Control =
|
||||
((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
|
||||
((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
|
||||
break;
|
||||
case 1:
|
||||
vbt->oaktrail_gct = ioremap(addr + sizeof(*vbt) - 4,
|
||||
vbt->size - sizeof(*vbt) + 4);
|
||||
pGCT = vbt->oaktrail_gct;
|
||||
bpi = ((struct oaktrail_gct_v2 *)pGCT)->PD.BootPanelIndex;
|
||||
dev_priv->gct_data.bpi = bpi;
|
||||
dev_priv->gct_data.pt =
|
||||
((struct oaktrail_gct_v2 *)pGCT)->PD.PanelType;
|
||||
memcpy(&dev_priv->gct_data.DTD,
|
||||
&((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].DTD,
|
||||
sizeof(struct oaktrail_timing_info));
|
||||
dev_priv->gct_data.Panel_Port_Control =
|
||||
((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
|
||||
((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
|
||||
break;
|
||||
case 0x10:
|
||||
/*header definition changed from rev 01 (v2) to rev 10h. */
|
||||
/*so, some values have changed location*/
|
||||
new_size = vbt->checksum; /*checksum contains lo size byte*/
|
||||
/*LSB of oaktrail_gct contains hi size byte*/
|
||||
new_size |= ((0xff & (unsigned int)vbt->oaktrail_gct)) << 8;
|
||||
|
||||
vbt->checksum = vbt->size; /*size contains the checksum*/
|
||||
if (new_size > 0xff)
|
||||
vbt->size = 0xff; /*restrict size to 255*/
|
||||
else
|
||||
vbt->size = new_size;
|
||||
|
||||
/* number of descriptors defined in the GCT */
|
||||
number_desc = ((0xff00 & (unsigned int)vbt->oaktrail_gct)) >> 8;
|
||||
bpi = ((0xff0000 & (unsigned int)vbt->oaktrail_gct)) >> 16;
|
||||
vbt->oaktrail_gct = ioremap(addr + GCT_R10_HEADER_SIZE,
|
||||
GCT_R10_DISPLAY_DESC_SIZE * number_desc);
|
||||
pGCT = vbt->oaktrail_gct;
|
||||
pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
|
||||
dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
|
||||
|
||||
/*copy the GCT display timings into a temp structure*/
|
||||
memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
|
||||
|
||||
/*now copy the temp struct into the dev_priv->gct_data*/
|
||||
dp_ti->pixel_clock = ti.pixel_clock;
|
||||
dp_ti->hactive_hi = ti.hactive_hi;
|
||||
dp_ti->hactive_lo = ti.hactive_lo;
|
||||
dp_ti->hblank_hi = ti.hblank_hi;
|
||||
dp_ti->hblank_lo = ti.hblank_lo;
|
||||
dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
|
||||
dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
|
||||
dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
|
||||
dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
|
||||
dp_ti->vactive_hi = ti.vactive_hi;
|
||||
dp_ti->vactive_lo = ti.vactive_lo;
|
||||
dp_ti->vblank_hi = ti.vblank_hi;
|
||||
dp_ti->vblank_lo = ti.vblank_lo;
|
||||
dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
|
||||
dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
|
||||
dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
|
||||
dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
|
||||
|
||||
/* Move the MIPI_Display_Descriptor data from GCT to dev priv */
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
|
||||
*((u8 *)pGCT + 0x0d);
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
|
||||
(*((u8 *)pGCT + 0x0e)) << 8;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "Unknown revision of GCT!\n");
|
||||
vbt->size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
int mid_chip_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
mid_get_fuse_settings(dev);
|
||||
mid_get_vbt_data(dev_priv);
|
||||
mid_get_pci_revID(dev_priv);
|
||||
return 0;
|
||||
}
|
21
drivers/gpu/drm/gma500/mid_bios.h
Normal file
21
drivers/gpu/drm/gma500/mid_bios.h
Normal file
@ -0,0 +1,21 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
extern int mid_chip_setup(struct drm_device *dev);
|
||||
|
858
drivers/gpu/drm/gma500/mmu.c
Normal file
858
drivers/gpu/drm/gma500/mmu.c
Normal file
@ -0,0 +1,858 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
#include <drm/drmP.h>
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
|
||||
/*
|
||||
* Code for the SGX MMU:
|
||||
*/
|
||||
|
||||
/*
|
||||
* clflush on one processor only:
|
||||
* clflush should apparently flush the cache line on all processors in an
|
||||
* SMP system.
|
||||
*/
|
||||
|
||||
/*
|
||||
* kmap atomic:
|
||||
* The usage of the slots must be completely encapsulated within a spinlock, and
|
||||
* no other functions that may be using the locks for other purposed may be
|
||||
* called from within the locked region.
|
||||
* Since the slots are per processor, this will guarantee that we are the only
|
||||
* user.
|
||||
*/
|
||||
|
||||
/*
|
||||
* TODO: Inserting ptes from an interrupt handler:
|
||||
* This may be desirable for some SGX functionality where the GPU can fault in
|
||||
* needed pages. For that, we need to make an atomic insert_pages function, that
|
||||
* may fail.
|
||||
* If it fails, the caller need to insert the page using a workqueue function,
|
||||
* but on average it should be fast.
|
||||
*/
|
||||
|
||||
struct psb_mmu_driver {
|
||||
/* protects driver- and pd structures. Always take in read mode
|
||||
* before taking the page table spinlock.
|
||||
*/
|
||||
struct rw_semaphore sem;
|
||||
|
||||
/* protects page tables, directory tables and pt tables.
|
||||
* and pt structures.
|
||||
*/
|
||||
spinlock_t lock;
|
||||
|
||||
atomic_t needs_tlbflush;
|
||||
|
||||
uint8_t __iomem *register_map;
|
||||
struct psb_mmu_pd *default_pd;
|
||||
/*uint32_t bif_ctrl;*/
|
||||
int has_clflush;
|
||||
int clflush_add;
|
||||
unsigned long clflush_mask;
|
||||
|
||||
struct drm_psb_private *dev_priv;
|
||||
};
|
||||
|
||||
struct psb_mmu_pd;
|
||||
|
||||
struct psb_mmu_pt {
|
||||
struct psb_mmu_pd *pd;
|
||||
uint32_t index;
|
||||
uint32_t count;
|
||||
struct page *p;
|
||||
uint32_t *v;
|
||||
};
|
||||
|
||||
struct psb_mmu_pd {
|
||||
struct psb_mmu_driver *driver;
|
||||
int hw_context;
|
||||
struct psb_mmu_pt **tables;
|
||||
struct page *p;
|
||||
struct page *dummy_pt;
|
||||
struct page *dummy_page;
|
||||
uint32_t pd_mask;
|
||||
uint32_t invalid_pde;
|
||||
uint32_t invalid_pte;
|
||||
};
|
||||
|
||||
static inline uint32_t psb_mmu_pt_index(uint32_t offset)
|
||||
{
|
||||
return (offset >> PSB_PTE_SHIFT) & 0x3FF;
|
||||
}
|
||||
|
||||
static inline uint32_t psb_mmu_pd_index(uint32_t offset)
|
||||
{
|
||||
return offset >> PSB_PDE_SHIFT;
|
||||
}
|
||||
|
||||
static inline void psb_clflush(void *addr)
|
||||
{
|
||||
__asm__ __volatile__("clflush (%0)\n" : : "r"(addr) : "memory");
|
||||
}
|
||||
|
||||
static inline void psb_mmu_clflush(struct psb_mmu_driver *driver,
|
||||
void *addr)
|
||||
{
|
||||
if (!driver->has_clflush)
|
||||
return;
|
||||
|
||||
mb();
|
||||
psb_clflush(addr);
|
||||
mb();
|
||||
}
|
||||
|
||||
static void psb_page_clflush(struct psb_mmu_driver *driver, struct page* page)
|
||||
{
|
||||
uint32_t clflush_add = driver->clflush_add >> PAGE_SHIFT;
|
||||
uint32_t clflush_count = PAGE_SIZE / clflush_add;
|
||||
int i;
|
||||
uint8_t *clf;
|
||||
|
||||
clf = kmap_atomic(page, KM_USER0);
|
||||
mb();
|
||||
for (i = 0; i < clflush_count; ++i) {
|
||||
psb_clflush(clf);
|
||||
clf += clflush_add;
|
||||
}
|
||||
mb();
|
||||
kunmap_atomic(clf, KM_USER0);
|
||||
}
|
||||
|
||||
static void psb_pages_clflush(struct psb_mmu_driver *driver,
|
||||
struct page *page[], unsigned long num_pages)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!driver->has_clflush)
|
||||
return ;
|
||||
|
||||
for (i = 0; i < num_pages; i++)
|
||||
psb_page_clflush(driver, *page++);
|
||||
}
|
||||
|
||||
static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver,
|
||||
int force)
|
||||
{
|
||||
atomic_set(&driver->needs_tlbflush, 0);
|
||||
}
|
||||
|
||||
static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
|
||||
{
|
||||
down_write(&driver->sem);
|
||||
psb_mmu_flush_pd_locked(driver, force);
|
||||
up_write(&driver->sem);
|
||||
}
|
||||
|
||||
void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot)
|
||||
{
|
||||
if (rc_prot)
|
||||
down_write(&driver->sem);
|
||||
if (rc_prot)
|
||||
up_write(&driver->sem);
|
||||
}
|
||||
|
||||
void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
|
||||
{
|
||||
/*ttm_tt_cache_flush(&pd->p, 1);*/
|
||||
psb_pages_clflush(pd->driver, &pd->p, 1);
|
||||
down_write(&pd->driver->sem);
|
||||
wmb();
|
||||
psb_mmu_flush_pd_locked(pd->driver, 1);
|
||||
pd->hw_context = hw_context;
|
||||
up_write(&pd->driver->sem);
|
||||
|
||||
}
|
||||
|
||||
static inline unsigned long psb_pd_addr_end(unsigned long addr,
|
||||
unsigned long end)
|
||||
{
|
||||
|
||||
addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
|
||||
return (addr < end) ? addr : end;
|
||||
}
|
||||
|
||||
static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
|
||||
{
|
||||
uint32_t mask = PSB_PTE_VALID;
|
||||
|
||||
if (type & PSB_MMU_CACHED_MEMORY)
|
||||
mask |= PSB_PTE_CACHED;
|
||||
if (type & PSB_MMU_RO_MEMORY)
|
||||
mask |= PSB_PTE_RO;
|
||||
if (type & PSB_MMU_WO_MEMORY)
|
||||
mask |= PSB_PTE_WO;
|
||||
|
||||
return (pfn << PAGE_SHIFT) | mask;
|
||||
}
|
||||
|
||||
struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
|
||||
int trap_pagefaults, int invalid_type)
|
||||
{
|
||||
struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
|
||||
uint32_t *v;
|
||||
int i;
|
||||
|
||||
if (!pd)
|
||||
return NULL;
|
||||
|
||||
pd->p = alloc_page(GFP_DMA32);
|
||||
if (!pd->p)
|
||||
goto out_err1;
|
||||
pd->dummy_pt = alloc_page(GFP_DMA32);
|
||||
if (!pd->dummy_pt)
|
||||
goto out_err2;
|
||||
pd->dummy_page = alloc_page(GFP_DMA32);
|
||||
if (!pd->dummy_page)
|
||||
goto out_err3;
|
||||
|
||||
if (!trap_pagefaults) {
|
||||
pd->invalid_pde =
|
||||
psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
|
||||
invalid_type);
|
||||
pd->invalid_pte =
|
||||
psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
|
||||
invalid_type);
|
||||
} else {
|
||||
pd->invalid_pde = 0;
|
||||
pd->invalid_pte = 0;
|
||||
}
|
||||
|
||||
v = kmap(pd->dummy_pt);
|
||||
for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
|
||||
v[i] = pd->invalid_pte;
|
||||
|
||||
kunmap(pd->dummy_pt);
|
||||
|
||||
v = kmap(pd->p);
|
||||
for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
|
||||
v[i] = pd->invalid_pde;
|
||||
|
||||
kunmap(pd->p);
|
||||
|
||||
clear_page(kmap(pd->dummy_page));
|
||||
kunmap(pd->dummy_page);
|
||||
|
||||
pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
|
||||
if (!pd->tables)
|
||||
goto out_err4;
|
||||
|
||||
pd->hw_context = -1;
|
||||
pd->pd_mask = PSB_PTE_VALID;
|
||||
pd->driver = driver;
|
||||
|
||||
return pd;
|
||||
|
||||
out_err4:
|
||||
__free_page(pd->dummy_page);
|
||||
out_err3:
|
||||
__free_page(pd->dummy_pt);
|
||||
out_err2:
|
||||
__free_page(pd->p);
|
||||
out_err1:
|
||||
kfree(pd);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void psb_mmu_free_pt(struct psb_mmu_pt *pt)
|
||||
{
|
||||
__free_page(pt->p);
|
||||
kfree(pt);
|
||||
}
|
||||
|
||||
void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
|
||||
{
|
||||
struct psb_mmu_driver *driver = pd->driver;
|
||||
struct psb_mmu_pt *pt;
|
||||
int i;
|
||||
|
||||
down_write(&driver->sem);
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush_pd_locked(driver, 1);
|
||||
|
||||
/* Should take the spinlock here, but we don't need to do that
|
||||
since we have the semaphore in write mode. */
|
||||
|
||||
for (i = 0; i < 1024; ++i) {
|
||||
pt = pd->tables[i];
|
||||
if (pt)
|
||||
psb_mmu_free_pt(pt);
|
||||
}
|
||||
|
||||
vfree(pd->tables);
|
||||
__free_page(pd->dummy_page);
|
||||
__free_page(pd->dummy_pt);
|
||||
__free_page(pd->p);
|
||||
kfree(pd);
|
||||
up_write(&driver->sem);
|
||||
}
|
||||
|
||||
static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
|
||||
{
|
||||
struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
|
||||
void *v;
|
||||
uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
|
||||
uint32_t clflush_count = PAGE_SIZE / clflush_add;
|
||||
spinlock_t *lock = &pd->driver->lock;
|
||||
uint8_t *clf;
|
||||
uint32_t *ptes;
|
||||
int i;
|
||||
|
||||
if (!pt)
|
||||
return NULL;
|
||||
|
||||
pt->p = alloc_page(GFP_DMA32);
|
||||
if (!pt->p) {
|
||||
kfree(pt);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
spin_lock(lock);
|
||||
|
||||
v = kmap_atomic(pt->p, KM_USER0);
|
||||
clf = (uint8_t *) v;
|
||||
ptes = (uint32_t *) v;
|
||||
for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
|
||||
*ptes++ = pd->invalid_pte;
|
||||
|
||||
|
||||
if (pd->driver->has_clflush && pd->hw_context != -1) {
|
||||
mb();
|
||||
for (i = 0; i < clflush_count; ++i) {
|
||||
psb_clflush(clf);
|
||||
clf += clflush_add;
|
||||
}
|
||||
mb();
|
||||
}
|
||||
|
||||
kunmap_atomic(v, KM_USER0);
|
||||
spin_unlock(lock);
|
||||
|
||||
pt->count = 0;
|
||||
pt->pd = pd;
|
||||
pt->index = 0;
|
||||
|
||||
return pt;
|
||||
}
|
||||
|
||||
struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
|
||||
unsigned long addr)
|
||||
{
|
||||
uint32_t index = psb_mmu_pd_index(addr);
|
||||
struct psb_mmu_pt *pt;
|
||||
uint32_t *v;
|
||||
spinlock_t *lock = &pd->driver->lock;
|
||||
|
||||
spin_lock(lock);
|
||||
pt = pd->tables[index];
|
||||
while (!pt) {
|
||||
spin_unlock(lock);
|
||||
pt = psb_mmu_alloc_pt(pd);
|
||||
if (!pt)
|
||||
return NULL;
|
||||
spin_lock(lock);
|
||||
|
||||
if (pd->tables[index]) {
|
||||
spin_unlock(lock);
|
||||
psb_mmu_free_pt(pt);
|
||||
spin_lock(lock);
|
||||
pt = pd->tables[index];
|
||||
continue;
|
||||
}
|
||||
|
||||
v = kmap_atomic(pd->p, KM_USER0);
|
||||
pd->tables[index] = pt;
|
||||
v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
|
||||
pt->index = index;
|
||||
kunmap_atomic((void *) v, KM_USER0);
|
||||
|
||||
if (pd->hw_context != -1) {
|
||||
psb_mmu_clflush(pd->driver, (void *) &v[index]);
|
||||
atomic_set(&pd->driver->needs_tlbflush, 1);
|
||||
}
|
||||
}
|
||||
pt->v = kmap_atomic(pt->p, KM_USER0);
|
||||
return pt;
|
||||
}
|
||||
|
||||
static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
|
||||
unsigned long addr)
|
||||
{
|
||||
uint32_t index = psb_mmu_pd_index(addr);
|
||||
struct psb_mmu_pt *pt;
|
||||
spinlock_t *lock = &pd->driver->lock;
|
||||
|
||||
spin_lock(lock);
|
||||
pt = pd->tables[index];
|
||||
if (!pt) {
|
||||
spin_unlock(lock);
|
||||
return NULL;
|
||||
}
|
||||
pt->v = kmap_atomic(pt->p, KM_USER0);
|
||||
return pt;
|
||||
}
|
||||
|
||||
static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
|
||||
{
|
||||
struct psb_mmu_pd *pd = pt->pd;
|
||||
uint32_t *v;
|
||||
|
||||
kunmap_atomic(pt->v, KM_USER0);
|
||||
if (pt->count == 0) {
|
||||
v = kmap_atomic(pd->p, KM_USER0);
|
||||
v[pt->index] = pd->invalid_pde;
|
||||
pd->tables[pt->index] = NULL;
|
||||
|
||||
if (pd->hw_context != -1) {
|
||||
psb_mmu_clflush(pd->driver,
|
||||
(void *) &v[pt->index]);
|
||||
atomic_set(&pd->driver->needs_tlbflush, 1);
|
||||
}
|
||||
kunmap_atomic(pt->v, KM_USER0);
|
||||
spin_unlock(&pd->driver->lock);
|
||||
psb_mmu_free_pt(pt);
|
||||
return;
|
||||
}
|
||||
spin_unlock(&pd->driver->lock);
|
||||
}
|
||||
|
||||
static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt,
|
||||
unsigned long addr, uint32_t pte)
|
||||
{
|
||||
pt->v[psb_mmu_pt_index(addr)] = pte;
|
||||
}
|
||||
|
||||
static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
|
||||
unsigned long addr)
|
||||
{
|
||||
pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
|
||||
}
|
||||
|
||||
|
||||
void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd,
|
||||
uint32_t mmu_offset, uint32_t gtt_start,
|
||||
uint32_t gtt_pages)
|
||||
{
|
||||
uint32_t *v;
|
||||
uint32_t start = psb_mmu_pd_index(mmu_offset);
|
||||
struct psb_mmu_driver *driver = pd->driver;
|
||||
int num_pages = gtt_pages;
|
||||
|
||||
down_read(&driver->sem);
|
||||
spin_lock(&driver->lock);
|
||||
|
||||
v = kmap_atomic(pd->p, KM_USER0);
|
||||
v += start;
|
||||
|
||||
while (gtt_pages--) {
|
||||
*v++ = gtt_start | pd->pd_mask;
|
||||
gtt_start += PAGE_SIZE;
|
||||
}
|
||||
|
||||
/*ttm_tt_cache_flush(&pd->p, num_pages);*/
|
||||
psb_pages_clflush(pd->driver, &pd->p, num_pages);
|
||||
kunmap_atomic(v, KM_USER0);
|
||||
spin_unlock(&driver->lock);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
atomic_set(&pd->driver->needs_tlbflush, 1);
|
||||
|
||||
up_read(&pd->driver->sem);
|
||||
psb_mmu_flush_pd(pd->driver, 0);
|
||||
}
|
||||
|
||||
struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
|
||||
{
|
||||
struct psb_mmu_pd *pd;
|
||||
|
||||
/* down_read(&driver->sem); */
|
||||
pd = driver->default_pd;
|
||||
/* up_read(&driver->sem); */
|
||||
|
||||
return pd;
|
||||
}
|
||||
|
||||
/* Returns the physical address of the PD shared by sgx/msvdx */
|
||||
uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver)
|
||||
{
|
||||
struct psb_mmu_pd *pd;
|
||||
|
||||
pd = psb_mmu_get_default_pd(driver);
|
||||
return page_to_pfn(pd->p) << PAGE_SHIFT;
|
||||
}
|
||||
|
||||
void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
|
||||
{
|
||||
psb_mmu_free_pagedir(driver->default_pd);
|
||||
kfree(driver);
|
||||
}
|
||||
|
||||
struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
|
||||
int trap_pagefaults,
|
||||
int invalid_type,
|
||||
struct drm_psb_private *dev_priv)
|
||||
{
|
||||
struct psb_mmu_driver *driver;
|
||||
|
||||
driver = kmalloc(sizeof(*driver), GFP_KERNEL);
|
||||
|
||||
if (!driver)
|
||||
return NULL;
|
||||
driver->dev_priv = dev_priv;
|
||||
|
||||
driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
|
||||
invalid_type);
|
||||
if (!driver->default_pd)
|
||||
goto out_err1;
|
||||
|
||||
spin_lock_init(&driver->lock);
|
||||
init_rwsem(&driver->sem);
|
||||
down_write(&driver->sem);
|
||||
driver->register_map = registers;
|
||||
atomic_set(&driver->needs_tlbflush, 1);
|
||||
|
||||
driver->has_clflush = 0;
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_CLFLSH)) {
|
||||
uint32_t tfms, misc, cap0, cap4, clflush_size;
|
||||
|
||||
/*
|
||||
* clflush size is determined at kernel setup for x86_64
|
||||
* but not for i386. We have to do it here.
|
||||
*/
|
||||
|
||||
cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
|
||||
clflush_size = ((misc >> 8) & 0xff) * 8;
|
||||
driver->has_clflush = 1;
|
||||
driver->clflush_add =
|
||||
PAGE_SIZE * clflush_size / sizeof(uint32_t);
|
||||
driver->clflush_mask = driver->clflush_add - 1;
|
||||
driver->clflush_mask = ~driver->clflush_mask;
|
||||
}
|
||||
|
||||
up_write(&driver->sem);
|
||||
return driver;
|
||||
|
||||
out_err1:
|
||||
kfree(driver);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride)
|
||||
{
|
||||
struct psb_mmu_pt *pt;
|
||||
uint32_t rows = 1;
|
||||
uint32_t i;
|
||||
unsigned long addr;
|
||||
unsigned long end;
|
||||
unsigned long next;
|
||||
unsigned long add;
|
||||
unsigned long row_add;
|
||||
unsigned long clflush_add = pd->driver->clflush_add;
|
||||
unsigned long clflush_mask = pd->driver->clflush_mask;
|
||||
|
||||
if (!pd->driver->has_clflush) {
|
||||
/*ttm_tt_cache_flush(&pd->p, num_pages);*/
|
||||
psb_pages_clflush(pd->driver, &pd->p, num_pages);
|
||||
return;
|
||||
}
|
||||
|
||||
if (hw_tile_stride)
|
||||
rows = num_pages / desired_tile_stride;
|
||||
else
|
||||
desired_tile_stride = num_pages;
|
||||
|
||||
add = desired_tile_stride << PAGE_SHIFT;
|
||||
row_add = hw_tile_stride << PAGE_SHIFT;
|
||||
mb();
|
||||
for (i = 0; i < rows; ++i) {
|
||||
|
||||
addr = address;
|
||||
end = addr + add;
|
||||
|
||||
do {
|
||||
next = psb_pd_addr_end(addr, end);
|
||||
pt = psb_mmu_pt_map_lock(pd, addr);
|
||||
if (!pt)
|
||||
continue;
|
||||
do {
|
||||
psb_clflush(&pt->v
|
||||
[psb_mmu_pt_index(addr)]);
|
||||
} while (addr +=
|
||||
clflush_add,
|
||||
(addr & clflush_mask) < next);
|
||||
|
||||
psb_mmu_pt_unmap_unlock(pt);
|
||||
} while (addr = next, next != end);
|
||||
address += row_add;
|
||||
}
|
||||
mb();
|
||||
}
|
||||
|
||||
void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
|
||||
unsigned long address, uint32_t num_pages)
|
||||
{
|
||||
struct psb_mmu_pt *pt;
|
||||
unsigned long addr;
|
||||
unsigned long end;
|
||||
unsigned long next;
|
||||
unsigned long f_address = address;
|
||||
|
||||
down_read(&pd->driver->sem);
|
||||
|
||||
addr = address;
|
||||
end = addr + (num_pages << PAGE_SHIFT);
|
||||
|
||||
do {
|
||||
next = psb_pd_addr_end(addr, end);
|
||||
pt = psb_mmu_pt_alloc_map_lock(pd, addr);
|
||||
if (!pt)
|
||||
goto out;
|
||||
do {
|
||||
psb_mmu_invalidate_pte(pt, addr);
|
||||
--pt->count;
|
||||
} while (addr += PAGE_SIZE, addr < next);
|
||||
psb_mmu_pt_unmap_unlock(pt);
|
||||
|
||||
} while (addr = next, next != end);
|
||||
|
||||
out:
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
|
||||
|
||||
up_read(&pd->driver->sem);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 0);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
|
||||
uint32_t num_pages, uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride)
|
||||
{
|
||||
struct psb_mmu_pt *pt;
|
||||
uint32_t rows = 1;
|
||||
uint32_t i;
|
||||
unsigned long addr;
|
||||
unsigned long end;
|
||||
unsigned long next;
|
||||
unsigned long add;
|
||||
unsigned long row_add;
|
||||
unsigned long f_address = address;
|
||||
|
||||
if (hw_tile_stride)
|
||||
rows = num_pages / desired_tile_stride;
|
||||
else
|
||||
desired_tile_stride = num_pages;
|
||||
|
||||
add = desired_tile_stride << PAGE_SHIFT;
|
||||
row_add = hw_tile_stride << PAGE_SHIFT;
|
||||
|
||||
/* down_read(&pd->driver->sem); */
|
||||
|
||||
/* Make sure we only need to flush this processor's cache */
|
||||
|
||||
for (i = 0; i < rows; ++i) {
|
||||
|
||||
addr = address;
|
||||
end = addr + add;
|
||||
|
||||
do {
|
||||
next = psb_pd_addr_end(addr, end);
|
||||
pt = psb_mmu_pt_map_lock(pd, addr);
|
||||
if (!pt)
|
||||
continue;
|
||||
do {
|
||||
psb_mmu_invalidate_pte(pt, addr);
|
||||
--pt->count;
|
||||
|
||||
} while (addr += PAGE_SIZE, addr < next);
|
||||
psb_mmu_pt_unmap_unlock(pt);
|
||||
|
||||
} while (addr = next, next != end);
|
||||
address += row_add;
|
||||
}
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush_ptes(pd, f_address, num_pages,
|
||||
desired_tile_stride, hw_tile_stride);
|
||||
|
||||
/* up_read(&pd->driver->sem); */
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 0);
|
||||
}
|
||||
|
||||
int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
int type)
|
||||
{
|
||||
struct psb_mmu_pt *pt;
|
||||
uint32_t pte;
|
||||
unsigned long addr;
|
||||
unsigned long end;
|
||||
unsigned long next;
|
||||
unsigned long f_address = address;
|
||||
int ret = 0;
|
||||
|
||||
down_read(&pd->driver->sem);
|
||||
|
||||
addr = address;
|
||||
end = addr + (num_pages << PAGE_SHIFT);
|
||||
|
||||
do {
|
||||
next = psb_pd_addr_end(addr, end);
|
||||
pt = psb_mmu_pt_alloc_map_lock(pd, addr);
|
||||
if (!pt) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
do {
|
||||
pte = psb_mmu_mask_pte(start_pfn++, type);
|
||||
psb_mmu_set_pte(pt, addr, pte);
|
||||
pt->count++;
|
||||
} while (addr += PAGE_SIZE, addr < next);
|
||||
psb_mmu_pt_unmap_unlock(pt);
|
||||
|
||||
} while (addr = next, next != end);
|
||||
|
||||
out:
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
|
||||
|
||||
up_read(&pd->driver->sem);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 1);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride, int type)
|
||||
{
|
||||
struct psb_mmu_pt *pt;
|
||||
uint32_t rows = 1;
|
||||
uint32_t i;
|
||||
uint32_t pte;
|
||||
unsigned long addr;
|
||||
unsigned long end;
|
||||
unsigned long next;
|
||||
unsigned long add;
|
||||
unsigned long row_add;
|
||||
unsigned long f_address = address;
|
||||
int ret = 0;
|
||||
|
||||
if (hw_tile_stride) {
|
||||
if (num_pages % desired_tile_stride != 0)
|
||||
return -EINVAL;
|
||||
rows = num_pages / desired_tile_stride;
|
||||
} else {
|
||||
desired_tile_stride = num_pages;
|
||||
}
|
||||
|
||||
add = desired_tile_stride << PAGE_SHIFT;
|
||||
row_add = hw_tile_stride << PAGE_SHIFT;
|
||||
|
||||
down_read(&pd->driver->sem);
|
||||
|
||||
for (i = 0; i < rows; ++i) {
|
||||
|
||||
addr = address;
|
||||
end = addr + add;
|
||||
|
||||
do {
|
||||
next = psb_pd_addr_end(addr, end);
|
||||
pt = psb_mmu_pt_alloc_map_lock(pd, addr);
|
||||
if (!pt) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
do {
|
||||
pte =
|
||||
psb_mmu_mask_pte(page_to_pfn(*pages++),
|
||||
type);
|
||||
psb_mmu_set_pte(pt, addr, pte);
|
||||
pt->count++;
|
||||
} while (addr += PAGE_SIZE, addr < next);
|
||||
psb_mmu_pt_unmap_unlock(pt);
|
||||
|
||||
} while (addr = next, next != end);
|
||||
|
||||
address += row_add;
|
||||
}
|
||||
out:
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush_ptes(pd, f_address, num_pages,
|
||||
desired_tile_stride, hw_tile_stride);
|
||||
|
||||
up_read(&pd->driver->sem);
|
||||
|
||||
if (pd->hw_context != -1)
|
||||
psb_mmu_flush(pd->driver, 1);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
|
||||
unsigned long *pfn)
|
||||
{
|
||||
int ret;
|
||||
struct psb_mmu_pt *pt;
|
||||
uint32_t tmp;
|
||||
spinlock_t *lock = &pd->driver->lock;
|
||||
|
||||
down_read(&pd->driver->sem);
|
||||
pt = psb_mmu_pt_map_lock(pd, virtual);
|
||||
if (!pt) {
|
||||
uint32_t *v;
|
||||
|
||||
spin_lock(lock);
|
||||
v = kmap_atomic(pd->p, KM_USER0);
|
||||
tmp = v[psb_mmu_pd_index(virtual)];
|
||||
kunmap_atomic(v, KM_USER0);
|
||||
spin_unlock(lock);
|
||||
|
||||
if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
|
||||
!(pd->invalid_pte & PSB_PTE_VALID)) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
ret = 0;
|
||||
*pfn = pd->invalid_pte >> PAGE_SHIFT;
|
||||
goto out;
|
||||
}
|
||||
tmp = pt->v[psb_mmu_pt_index(virtual)];
|
||||
if (!(tmp & PSB_PTE_VALID)) {
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
ret = 0;
|
||||
*pfn = tmp >> PAGE_SHIFT;
|
||||
}
|
||||
psb_mmu_pt_unmap_unlock(pt);
|
||||
out:
|
||||
up_read(&pd->driver->sem);
|
||||
return ret;
|
||||
}
|
252
drivers/gpu/drm/gma500/oaktrail.h
Normal file
252
drivers/gpu/drm/gma500/oaktrail.h
Normal file
@ -0,0 +1,252 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/* MID device specific descriptors */
|
||||
|
||||
struct oaktrail_vbt {
|
||||
s8 signature[4]; /*4 bytes,"$GCT" */
|
||||
u8 revision;
|
||||
u8 size;
|
||||
u8 checksum;
|
||||
void *oaktrail_gct;
|
||||
} __packed;
|
||||
|
||||
struct oaktrail_timing_info {
|
||||
u16 pixel_clock;
|
||||
u8 hactive_lo;
|
||||
u8 hblank_lo;
|
||||
u8 hblank_hi:4;
|
||||
u8 hactive_hi:4;
|
||||
u8 vactive_lo;
|
||||
u8 vblank_lo;
|
||||
u8 vblank_hi:4;
|
||||
u8 vactive_hi:4;
|
||||
u8 hsync_offset_lo;
|
||||
u8 hsync_pulse_width_lo;
|
||||
u8 vsync_pulse_width_lo:4;
|
||||
u8 vsync_offset_lo:4;
|
||||
u8 vsync_pulse_width_hi:2;
|
||||
u8 vsync_offset_hi:2;
|
||||
u8 hsync_pulse_width_hi:2;
|
||||
u8 hsync_offset_hi:2;
|
||||
u8 width_mm_lo;
|
||||
u8 height_mm_lo;
|
||||
u8 height_mm_hi:4;
|
||||
u8 width_mm_hi:4;
|
||||
u8 hborder;
|
||||
u8 vborder;
|
||||
u8 unknown0:1;
|
||||
u8 hsync_positive:1;
|
||||
u8 vsync_positive:1;
|
||||
u8 separate_sync:2;
|
||||
u8 stereo:1;
|
||||
u8 unknown6:1;
|
||||
u8 interlaced:1;
|
||||
} __packed;
|
||||
|
||||
struct gct_r10_timing_info {
|
||||
u16 pixel_clock;
|
||||
u32 hactive_lo:8;
|
||||
u32 hactive_hi:4;
|
||||
u32 hblank_lo:8;
|
||||
u32 hblank_hi:4;
|
||||
u32 hsync_offset_lo:8;
|
||||
u16 hsync_offset_hi:2;
|
||||
u16 hsync_pulse_width_lo:8;
|
||||
u16 hsync_pulse_width_hi:2;
|
||||
u16 hsync_positive:1;
|
||||
u16 rsvd_1:3;
|
||||
u8 vactive_lo:8;
|
||||
u16 vactive_hi:4;
|
||||
u16 vblank_lo:8;
|
||||
u16 vblank_hi:4;
|
||||
u16 vsync_offset_lo:4;
|
||||
u16 vsync_offset_hi:2;
|
||||
u16 vsync_pulse_width_lo:4;
|
||||
u16 vsync_pulse_width_hi:2;
|
||||
u16 vsync_positive:1;
|
||||
u16 rsvd_2:3;
|
||||
} __packed;
|
||||
|
||||
struct oaktrail_panel_descriptor_v1 {
|
||||
u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
|
||||
/* 0x61190 if MIPI */
|
||||
u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
|
||||
u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
|
||||
u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */
|
||||
/* Register 0x61210 */
|
||||
struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
|
||||
u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
|
||||
/* Bit 0, Frequency, 15 bits,0 - 32767Hz */
|
||||
/* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
|
||||
u16 Panel_MIPI_Display_Descriptor;
|
||||
/*16 bits, Defined as follows: */
|
||||
/* if MIPI, 0x0000 if LVDS */
|
||||
/* Bit 0, Type, 2 bits, */
|
||||
/* 0: Type-1, */
|
||||
/* 1: Type-2, */
|
||||
/* 2: Type-3, */
|
||||
/* 3: Type-4 */
|
||||
/* Bit 2, Pixel Format, 4 bits */
|
||||
/* Bit0: 16bpp (not supported in LNC), */
|
||||
/* Bit1: 18bpp loosely packed, */
|
||||
/* Bit2: 18bpp packed, */
|
||||
/* Bit3: 24bpp */
|
||||
/* Bit 6, Reserved, 2 bits, 00b */
|
||||
/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
|
||||
/* Bit 14, Reserved, 2 bits, 00b */
|
||||
} __packed;
|
||||
|
||||
struct oaktrail_panel_descriptor_v2 {
|
||||
u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
|
||||
/* 0x61190 if MIPI */
|
||||
u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
|
||||
u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
|
||||
u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */
|
||||
/* Register 0x61210 */
|
||||
struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
|
||||
u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
|
||||
/*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
|
||||
u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
|
||||
/*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
|
||||
u16 Panel_MIPI_Display_Descriptor;
|
||||
/*16 bits, Defined as follows: */
|
||||
/* if MIPI, 0x0000 if LVDS */
|
||||
/* Bit 0, Type, 2 bits, */
|
||||
/* 0: Type-1, */
|
||||
/* 1: Type-2, */
|
||||
/* 2: Type-3, */
|
||||
/* 3: Type-4 */
|
||||
/* Bit 2, Pixel Format, 4 bits */
|
||||
/* Bit0: 16bpp (not supported in LNC), */
|
||||
/* Bit1: 18bpp loosely packed, */
|
||||
/* Bit2: 18bpp packed, */
|
||||
/* Bit3: 24bpp */
|
||||
/* Bit 6, Reserved, 2 bits, 00b */
|
||||
/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
|
||||
/* Bit 14, Reserved, 2 bits, 00b */
|
||||
} __packed;
|
||||
|
||||
union oaktrail_panel_rx {
|
||||
struct {
|
||||
u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
|
||||
/* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
|
||||
u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
|
||||
/*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
|
||||
u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
|
||||
/* 1: Burst and non-burst */
|
||||
/* 2/3: Reserved */
|
||||
u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
|
||||
u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
|
||||
u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
|
||||
u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
|
||||
u16 Rsvd:5;/*5 bits,00000b */
|
||||
} panelrx;
|
||||
u16 panel_receiver;
|
||||
} __packed;
|
||||
|
||||
struct oaktrail_gct_v1 {
|
||||
union { /*8 bits,Defined as follows: */
|
||||
struct {
|
||||
u8 PanelType:4; /*4 bits, Bit field for panels*/
|
||||
/* 0 - 3: 0 = LVDS, 1 = MIPI*/
|
||||
/*2 bits,Specifies which of the*/
|
||||
u8 BootPanelIndex:2;
|
||||
/* 4 panels to use by default*/
|
||||
u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
|
||||
/* the 4 MIPI DSI receivers to use*/
|
||||
} PD;
|
||||
u8 PanelDescriptor;
|
||||
};
|
||||
struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
|
||||
union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
|
||||
} __packed;
|
||||
|
||||
struct oaktrail_gct_v2 {
|
||||
union { /*8 bits,Defined as follows: */
|
||||
struct {
|
||||
u8 PanelType:4; /*4 bits, Bit field for panels*/
|
||||
/* 0 - 3: 0 = LVDS, 1 = MIPI*/
|
||||
/*2 bits,Specifies which of the*/
|
||||
u8 BootPanelIndex:2;
|
||||
/* 4 panels to use by default*/
|
||||
u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
|
||||
/* the 4 MIPI DSI receivers to use*/
|
||||
} PD;
|
||||
u8 PanelDescriptor;
|
||||
};
|
||||
struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
|
||||
union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
|
||||
} __packed;
|
||||
|
||||
struct oaktrail_gct_data {
|
||||
u8 bpi; /* boot panel index, number of panel used during boot */
|
||||
u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
|
||||
struct oaktrail_timing_info DTD; /* timing info for the selected panel */
|
||||
u32 Panel_Port_Control;
|
||||
u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
|
||||
u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
|
||||
u32 PP_Cycle_Delay;
|
||||
u16 Panel_Backlight_Inverter_Descriptor;
|
||||
u16 Panel_MIPI_Display_Descriptor;
|
||||
} __packed;
|
||||
|
||||
#define MODE_SETTING_IN_CRTC 0x1
|
||||
#define MODE_SETTING_IN_ENCODER 0x2
|
||||
#define MODE_SETTING_ON_GOING 0x3
|
||||
#define MODE_SETTING_IN_DSR 0x4
|
||||
#define MODE_SETTING_ENCODER_DONE 0x8
|
||||
|
||||
#define GCT_R10_HEADER_SIZE 16
|
||||
#define GCT_R10_DISPLAY_DESC_SIZE 28
|
||||
|
||||
/*
|
||||
* Moorestown HDMI interfaces
|
||||
*/
|
||||
|
||||
struct oaktrail_hdmi_dev {
|
||||
struct pci_dev *dev;
|
||||
void __iomem *regs;
|
||||
unsigned int mmio, mmio_len;
|
||||
int dpms_mode;
|
||||
struct hdmi_i2c_dev *i2c_dev;
|
||||
|
||||
/* register state */
|
||||
u32 saveDPLL_CTRL;
|
||||
u32 saveDPLL_DIV_CTRL;
|
||||
u32 saveDPLL_ADJUST;
|
||||
u32 saveDPLL_UPDATE;
|
||||
u32 saveDPLL_CLK_ENABLE;
|
||||
u32 savePCH_HTOTAL_B;
|
||||
u32 savePCH_HBLANK_B;
|
||||
u32 savePCH_HSYNC_B;
|
||||
u32 savePCH_VTOTAL_B;
|
||||
u32 savePCH_VBLANK_B;
|
||||
u32 savePCH_VSYNC_B;
|
||||
u32 savePCH_PIPEBCONF;
|
||||
u32 savePCH_PIPEBSRC;
|
||||
};
|
||||
|
||||
extern void oaktrail_hdmi_setup(struct drm_device *dev);
|
||||
extern void oaktrail_hdmi_teardown(struct drm_device *dev);
|
||||
extern int oaktrail_hdmi_i2c_init(struct pci_dev *dev);
|
||||
extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev);
|
||||
extern void oaktrail_hdmi_save(struct drm_device *dev);
|
||||
extern void oaktrail_hdmi_restore(struct drm_device *dev);
|
||||
extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev);
|
610
drivers/gpu/drm/gma500/oaktrail_crtc.c
Normal file
610
drivers/gpu/drm/gma500/oaktrail_crtc.c
Normal file
@ -0,0 +1,610 @@
|
||||
/*
|
||||
* Copyright © 2009 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include "framebuffer.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "psb_intel_display.h"
|
||||
#include "power.h"
|
||||
|
||||
struct psb_intel_range_t {
|
||||
int min, max;
|
||||
};
|
||||
|
||||
struct oaktrail_limit_t {
|
||||
struct psb_intel_range_t dot, m, p1;
|
||||
};
|
||||
|
||||
struct oaktrail_clock_t {
|
||||
/* derived values */
|
||||
int dot;
|
||||
int m;
|
||||
int p1;
|
||||
};
|
||||
|
||||
#define MRST_LIMIT_LVDS_100L 0
|
||||
#define MRST_LIMIT_LVDS_83 1
|
||||
#define MRST_LIMIT_LVDS_100 2
|
||||
|
||||
#define MRST_DOT_MIN 19750
|
||||
#define MRST_DOT_MAX 120000
|
||||
#define MRST_M_MIN_100L 20
|
||||
#define MRST_M_MIN_100 10
|
||||
#define MRST_M_MIN_83 12
|
||||
#define MRST_M_MAX_100L 34
|
||||
#define MRST_M_MAX_100 17
|
||||
#define MRST_M_MAX_83 20
|
||||
#define MRST_P1_MIN 2
|
||||
#define MRST_P1_MAX_0 7
|
||||
#define MRST_P1_MAX_1 8
|
||||
|
||||
static const struct oaktrail_limit_t oaktrail_limits[] = {
|
||||
{ /* MRST_LIMIT_LVDS_100L */
|
||||
.dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
|
||||
.m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
|
||||
.p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
|
||||
},
|
||||
{ /* MRST_LIMIT_LVDS_83L */
|
||||
.dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
|
||||
.m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
|
||||
.p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
|
||||
},
|
||||
{ /* MRST_LIMIT_LVDS_100 */
|
||||
.dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
|
||||
.m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
|
||||
.p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
|
||||
},
|
||||
};
|
||||
|
||||
#define MRST_M_MIN 10
|
||||
static const u32 oaktrail_m_converts[] = {
|
||||
0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
|
||||
0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
|
||||
0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
|
||||
};
|
||||
|
||||
static const struct oaktrail_limit_t *oaktrail_limit(struct drm_crtc *crtc)
|
||||
{
|
||||
const struct oaktrail_limit_t *limit = NULL;
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
|
||||
|| psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
|
||||
switch (dev_priv->core_freq) {
|
||||
case 100:
|
||||
limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L];
|
||||
break;
|
||||
case 166:
|
||||
limit = &oaktrail_limits[MRST_LIMIT_LVDS_83];
|
||||
break;
|
||||
case 200:
|
||||
limit = &oaktrail_limits[MRST_LIMIT_LVDS_100];
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
limit = NULL;
|
||||
dev_err(dev->dev, "oaktrail_limit Wrong display type.\n");
|
||||
}
|
||||
|
||||
return limit;
|
||||
}
|
||||
|
||||
/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
|
||||
static void oaktrail_clock(int refclk, struct oaktrail_clock_t *clock)
|
||||
{
|
||||
clock->dot = (refclk * clock->m) / (14 * clock->p1);
|
||||
}
|
||||
|
||||
void mrstPrintPll(char *prefix, struct oaktrail_clock_t *clock)
|
||||
{
|
||||
pr_debug("%s: dotclock = %d, m = %d, p1 = %d.\n",
|
||||
prefix, clock->dot, clock->m, clock->p1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Returns a set of divisors for the desired target clock with the given refclk,
|
||||
* or FALSE. Divisor values are the actual divisors for
|
||||
*/
|
||||
static bool
|
||||
mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
|
||||
struct oaktrail_clock_t *best_clock)
|
||||
{
|
||||
struct oaktrail_clock_t clock;
|
||||
const struct oaktrail_limit_t *limit = oaktrail_limit(crtc);
|
||||
int err = target;
|
||||
|
||||
memset(best_clock, 0, sizeof(*best_clock));
|
||||
|
||||
for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
|
||||
for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
|
||||
clock.p1++) {
|
||||
int this_err;
|
||||
|
||||
oaktrail_clock(refclk, &clock);
|
||||
|
||||
this_err = abs(clock.dot - target);
|
||||
if (this_err < err) {
|
||||
*best_clock = clock;
|
||||
err = this_err;
|
||||
}
|
||||
}
|
||||
}
|
||||
dev_dbg(crtc->dev->dev, "mrstFindBestPLL err = %d.\n", err);
|
||||
return err != target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the power management mode of the pipe and plane.
|
||||
*
|
||||
* This code should probably grow support for turning the cursor off and back
|
||||
* on appropriately at the same time as we're turning the pipe off/on.
|
||||
*/
|
||||
static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int dspbase_reg = (pipe == 0) ? MRST_DSPABASE : DSPBBASE;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
u32 temp;
|
||||
bool enabled;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
/* XXX: When our outputs are all unaware of DPMS modes other than off
|
||||
* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
|
||||
*/
|
||||
switch (mode) {
|
||||
case DRM_MODE_DPMS_ON:
|
||||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
/* Enable the DPLL */
|
||||
temp = REG_READ(dpll_reg);
|
||||
if ((temp & DPLL_VCO_ENABLE) == 0) {
|
||||
REG_WRITE(dpll_reg, temp);
|
||||
REG_READ(dpll_reg);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
}
|
||||
/* Enable the pipe */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
if ((temp & PIPEACONF_ENABLE) == 0)
|
||||
REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
|
||||
/* Enable the plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
temp | DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
}
|
||||
|
||||
psb_intel_crtc_load_lut(crtc);
|
||||
|
||||
/* Give the overlay scaler a chance to enable
|
||||
if it's on this pipe */
|
||||
/* psb_intel_crtc_dpms_video(crtc, true); TODO */
|
||||
break;
|
||||
case DRM_MODE_DPMS_OFF:
|
||||
/* Give the overlay scaler a chance to disable
|
||||
* if it's on this pipe */
|
||||
/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
|
||||
|
||||
/* Disable the VGA plane that we never use */
|
||||
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
|
||||
/* Disable display plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
temp & ~DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_READ(dspbase_reg);
|
||||
}
|
||||
|
||||
/* Next, disable display pipes */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
if ((temp & PIPEACONF_ENABLE) != 0) {
|
||||
REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
|
||||
REG_READ(pipeconf_reg);
|
||||
}
|
||||
/* Wait for for the pipe disable to take effect. */
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
temp = REG_READ(dpll_reg);
|
||||
if ((temp & DPLL_VCO_ENABLE) != 0) {
|
||||
REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
}
|
||||
|
||||
/* Wait for the clocks to turn off. */
|
||||
udelay(150);
|
||||
break;
|
||||
}
|
||||
|
||||
enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
|
||||
|
||||
/*Set FIFO Watermarks*/
|
||||
REG_WRITE(DSPARB, 0x3FFF);
|
||||
REG_WRITE(DSPFW1, 0x3F88080A);
|
||||
REG_WRITE(DSPFW2, 0x0b060808);
|
||||
REG_WRITE(DSPFW3, 0x0);
|
||||
REG_WRITE(DSPFW4, 0x08030404);
|
||||
REG_WRITE(DSPFW5, 0x04040404);
|
||||
REG_WRITE(DSPFW6, 0x78);
|
||||
REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000);
|
||||
/* Must write Bit 14 of the Chicken Bit Register */
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the pipe currently connected to the panel fitter,
|
||||
* or -1 if the panel fitter is not present or not in use
|
||||
*/
|
||||
static int oaktrail_panel_fitter_pipe(struct drm_device *dev)
|
||||
{
|
||||
u32 pfit_control;
|
||||
|
||||
pfit_control = REG_READ(PFIT_CONTROL);
|
||||
|
||||
/* See if the panel fitter is in use */
|
||||
if ((pfit_control & PFIT_ENABLE) == 0)
|
||||
return -1;
|
||||
return (pfit_control >> 29) & 3;
|
||||
}
|
||||
|
||||
static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode,
|
||||
int x, int y,
|
||||
struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0;
|
||||
int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
|
||||
int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
|
||||
int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
|
||||
int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
|
||||
int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
|
||||
int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
|
||||
int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
|
||||
int refclk = 0;
|
||||
struct oaktrail_clock_t clock;
|
||||
u32 dpll = 0, fp = 0, dspcntr, pipeconf;
|
||||
bool ok, is_sdvo = false;
|
||||
bool is_crt = false, is_lvds = false, is_tv = false;
|
||||
bool is_mipi = false;
|
||||
struct drm_mode_config *mode_config = &dev->mode_config;
|
||||
struct psb_intel_output *psb_intel_output = NULL;
|
||||
uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
|
||||
struct drm_encoder *encoder;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return 0;
|
||||
|
||||
memcpy(&psb_intel_crtc->saved_mode,
|
||||
mode,
|
||||
sizeof(struct drm_display_mode));
|
||||
memcpy(&psb_intel_crtc->saved_adjusted_mode,
|
||||
adjusted_mode,
|
||||
sizeof(struct drm_display_mode));
|
||||
|
||||
list_for_each_entry(encoder, &mode_config->encoder_list, head) {
|
||||
|
||||
if (encoder->crtc != crtc)
|
||||
continue;
|
||||
|
||||
psb_intel_output = enc_to_psb_intel_output(encoder);
|
||||
switch (psb_intel_output->type) {
|
||||
case INTEL_OUTPUT_LVDS:
|
||||
is_lvds = true;
|
||||
break;
|
||||
case INTEL_OUTPUT_SDVO:
|
||||
is_sdvo = true;
|
||||
break;
|
||||
case INTEL_OUTPUT_TVOUT:
|
||||
is_tv = true;
|
||||
break;
|
||||
case INTEL_OUTPUT_ANALOG:
|
||||
is_crt = true;
|
||||
break;
|
||||
case INTEL_OUTPUT_MIPI:
|
||||
is_mipi = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable the VGA plane that we never use */
|
||||
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
|
||||
|
||||
/* Disable the panel fitter if it was on our pipe */
|
||||
if (oaktrail_panel_fitter_pipe(dev) == pipe)
|
||||
REG_WRITE(PFIT_CONTROL, 0);
|
||||
|
||||
REG_WRITE(pipesrc_reg,
|
||||
((mode->crtc_hdisplay - 1) << 16) |
|
||||
(mode->crtc_vdisplay - 1));
|
||||
|
||||
if (psb_intel_output)
|
||||
drm_connector_property_get_value(&psb_intel_output->base,
|
||||
dev->mode_config.scaling_mode_property, &scalingType);
|
||||
|
||||
if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
|
||||
/* Moorestown doesn't have register support for centering so
|
||||
* we need to mess with the h/vblank and h/vsync start and
|
||||
* ends to get centering */
|
||||
int offsetX = 0, offsetY = 0;
|
||||
|
||||
offsetX = (adjusted_mode->crtc_hdisplay -
|
||||
mode->crtc_hdisplay) / 2;
|
||||
offsetY = (adjusted_mode->crtc_vdisplay -
|
||||
mode->crtc_vdisplay) / 2;
|
||||
|
||||
REG_WRITE(htot_reg, (mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(hblank_reg,
|
||||
(adjusted_mode->crtc_hblank_start - offsetX - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
|
||||
REG_WRITE(hsync_reg,
|
||||
(adjusted_mode->crtc_hsync_start - offsetX - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
|
||||
REG_WRITE(vblank_reg,
|
||||
(adjusted_mode->crtc_vblank_start - offsetY - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
|
||||
REG_WRITE(vsync_reg,
|
||||
(adjusted_mode->crtc_vsync_start - offsetY - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
|
||||
} else {
|
||||
REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - 1) << 16));
|
||||
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - 1) << 16));
|
||||
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - 1) << 16));
|
||||
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - 1) << 16));
|
||||
}
|
||||
|
||||
/* Flush the plane changes */
|
||||
{
|
||||
struct drm_crtc_helper_funcs *crtc_funcs =
|
||||
crtc->helper_private;
|
||||
crtc_funcs->mode_set_base(crtc, x, y, old_fb);
|
||||
}
|
||||
|
||||
/* setup pipeconf */
|
||||
pipeconf = REG_READ(pipeconf_reg);
|
||||
|
||||
/* Set up the display plane register */
|
||||
dspcntr = REG_READ(dspcntr_reg);
|
||||
dspcntr |= DISPPLANE_GAMMA_ENABLE;
|
||||
|
||||
if (pipe == 0)
|
||||
dspcntr |= DISPPLANE_SEL_PIPE_A;
|
||||
else
|
||||
dspcntr |= DISPPLANE_SEL_PIPE_B;
|
||||
|
||||
dev_priv->dspcntr = dspcntr |= DISPLAY_PLANE_ENABLE;
|
||||
dev_priv->pipeconf = pipeconf |= PIPEACONF_ENABLE;
|
||||
|
||||
if (is_mipi)
|
||||
goto oaktrail_crtc_mode_set_exit;
|
||||
|
||||
refclk = dev_priv->core_freq * 1000;
|
||||
|
||||
dpll = 0; /*BIT16 = 0 for 100MHz reference */
|
||||
|
||||
ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock);
|
||||
|
||||
if (!ok) {
|
||||
dev_dbg(dev->dev, "mrstFindBestPLL fail in oaktrail_crtc_mode_set.\n");
|
||||
} else {
|
||||
dev_dbg(dev->dev, "oaktrail_crtc_mode_set pixel clock = %d,"
|
||||
"m = %x, p1 = %x.\n", clock.dot, clock.m,
|
||||
clock.p1);
|
||||
}
|
||||
|
||||
fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
|
||||
|
||||
dpll |= DPLL_VGA_MODE_DIS;
|
||||
|
||||
|
||||
dpll |= DPLL_VCO_ENABLE;
|
||||
|
||||
if (is_lvds)
|
||||
dpll |= DPLLA_MODE_LVDS;
|
||||
else
|
||||
dpll |= DPLLB_MODE_DAC_SERIAL;
|
||||
|
||||
if (is_sdvo) {
|
||||
int sdvo_pixel_multiply =
|
||||
adjusted_mode->clock / mode->clock;
|
||||
|
||||
dpll |= DPLL_DVO_HIGH_SPEED;
|
||||
dpll |=
|
||||
(sdvo_pixel_multiply -
|
||||
1) << SDVO_MULTIPLIER_SHIFT_HIRES;
|
||||
}
|
||||
|
||||
|
||||
/* compute bitmask from p1 value */
|
||||
dpll |= (1 << (clock.p1 - 2)) << 17;
|
||||
|
||||
dpll |= DPLL_VCO_ENABLE;
|
||||
|
||||
mrstPrintPll("chosen", &clock);
|
||||
|
||||
if (dpll & DPLL_VCO_ENABLE) {
|
||||
REG_WRITE(fp_reg, fp);
|
||||
REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
/* Check the DPLLA lock bit PIPEACONF[29] */
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
REG_WRITE(fp_reg, fp);
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_READ(dpll_reg);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
|
||||
/* write it again -- the BIOS does, after all */
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_READ(dpll_reg);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
|
||||
REG_WRITE(pipeconf_reg, pipeconf);
|
||||
REG_READ(pipeconf_reg);
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
oaktrail_crtc_mode_set_exit:
|
||||
gma_power_end(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool oaktrail_crtc_mode_fixup(struct drm_crtc *crtc,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
int oaktrail_pipe_set_base(struct drm_crtc *crtc,
|
||||
int x, int y, struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
/* struct drm_i915_master_private *master_priv; */
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
unsigned long start, offset;
|
||||
/* FIXME: check if we need this surely MRST is pipe 0 only */
|
||||
int dspbase = (pipe == 0 ? DSPALINOFF : DSPBBASE);
|
||||
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
|
||||
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
u32 dspcntr;
|
||||
int ret = 0;
|
||||
|
||||
/* no fb bound */
|
||||
if (!crtc->fb) {
|
||||
dev_dbg(dev->dev, "No FB bound\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return 0;
|
||||
|
||||
start = psbfb->gtt->offset;
|
||||
offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
|
||||
|
||||
REG_WRITE(dspstride, crtc->fb->pitch);
|
||||
|
||||
dspcntr = REG_READ(dspcntr_reg);
|
||||
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
|
||||
|
||||
switch (crtc->fb->bits_per_pixel) {
|
||||
case 8:
|
||||
dspcntr |= DISPPLANE_8BPP;
|
||||
break;
|
||||
case 16:
|
||||
if (crtc->fb->depth == 15)
|
||||
dspcntr |= DISPPLANE_15_16BPP;
|
||||
else
|
||||
dspcntr |= DISPPLANE_16BPP;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "Unknown color depth\n");
|
||||
ret = -EINVAL;
|
||||
goto pipe_set_base_exit;
|
||||
}
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
|
||||
if (0 /* FIXMEAC - check what PSB needs */) {
|
||||
REG_WRITE(dspbase, offset);
|
||||
REG_READ(dspbase);
|
||||
REG_WRITE(dspsurf, start);
|
||||
REG_READ(dspsurf);
|
||||
} else {
|
||||
REG_WRITE(dspbase, start + offset);
|
||||
REG_READ(dspbase);
|
||||
}
|
||||
|
||||
pipe_set_base_exit:
|
||||
gma_power_end(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void oaktrail_crtc_prepare(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
||||
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
|
||||
}
|
||||
|
||||
static void oaktrail_crtc_commit(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
||||
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
|
||||
}
|
||||
|
||||
const struct drm_crtc_helper_funcs oaktrail_helper_funcs = {
|
||||
.dpms = oaktrail_crtc_dpms,
|
||||
.mode_fixup = oaktrail_crtc_mode_fixup,
|
||||
.mode_set = oaktrail_crtc_mode_set,
|
||||
.mode_set_base = oaktrail_pipe_set_base,
|
||||
.prepare = oaktrail_crtc_prepare,
|
||||
.commit = oaktrail_crtc_commit,
|
||||
};
|
||||
|
489
drivers/gpu/drm/gma500/oaktrail_device.c
Normal file
489
drivers/gpu/drm/gma500/oaktrail_device.c
Normal file
@ -0,0 +1,489 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#include <linux/backlight.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_drm.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include <asm/mrst.h>
|
||||
#include <asm/intel_scu_ipc.h>
|
||||
#include "mid_bios.h"
|
||||
|
||||
static int oaktrail_output_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
if (dev_priv->iLVDS_enable)
|
||||
oaktrail_lvds_init(dev, &dev_priv->mode_dev);
|
||||
else
|
||||
dev_err(dev->dev, "DSI is not supported\n");
|
||||
if (dev_priv->hdmi_priv)
|
||||
oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Provide the low level interfaces for the Moorestown backlight
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
|
||||
#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
|
||||
#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
|
||||
#define BLC_PWM_FREQ_CALC_CONSTANT 32
|
||||
#define MHz 1000000
|
||||
#define BLC_ADJUSTMENT_MAX 100
|
||||
|
||||
static struct backlight_device *oaktrail_backlight_device;
|
||||
static int oaktrail_brightness;
|
||||
|
||||
static int oaktrail_set_brightness(struct backlight_device *bd)
|
||||
{
|
||||
struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int level = bd->props.brightness;
|
||||
u32 blc_pwm_ctl;
|
||||
u32 max_pwm_blc;
|
||||
|
||||
/* Percentage 1-100% being valid */
|
||||
if (level < 1)
|
||||
level = 1;
|
||||
|
||||
if (gma_power_begin(dev, 0)) {
|
||||
/* Calculate and set the brightness value */
|
||||
max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
|
||||
blc_pwm_ctl = level * max_pwm_blc / 100;
|
||||
|
||||
/* Adjust the backlight level with the percent in
|
||||
* dev_priv->blc_adj1;
|
||||
*/
|
||||
blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
|
||||
blc_pwm_ctl = blc_pwm_ctl / 100;
|
||||
|
||||
/* Adjust the backlight level with the percent in
|
||||
* dev_priv->blc_adj2;
|
||||
*/
|
||||
blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
|
||||
blc_pwm_ctl = blc_pwm_ctl / 100;
|
||||
|
||||
/* force PWM bit on */
|
||||
REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
|
||||
REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
|
||||
gma_power_end(dev);
|
||||
}
|
||||
oaktrail_brightness = level;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int oaktrail_get_brightness(struct backlight_device *bd)
|
||||
{
|
||||
/* return locally cached var instead of HW read (due to DPST etc.) */
|
||||
/* FIXME: ideally return actual value in case firmware fiddled with
|
||||
it */
|
||||
return oaktrail_brightness;
|
||||
}
|
||||
|
||||
static int device_backlight_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long core_clock;
|
||||
u16 bl_max_freq;
|
||||
uint32_t value;
|
||||
uint32_t blc_pwm_precision_factor;
|
||||
|
||||
dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
|
||||
dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
|
||||
bl_max_freq = 256;
|
||||
/* this needs to be set elsewhere */
|
||||
blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
|
||||
|
||||
core_clock = dev_priv->core_freq;
|
||||
|
||||
value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
|
||||
value *= blc_pwm_precision_factor;
|
||||
value /= bl_max_freq;
|
||||
value /= blc_pwm_precision_factor;
|
||||
|
||||
if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
|
||||
return -ERANGE;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
|
||||
REG_WRITE(BLC_PWM_CTL, value | (value << 16));
|
||||
gma_power_end(dev);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct backlight_ops oaktrail_ops = {
|
||||
.get_brightness = oaktrail_get_brightness,
|
||||
.update_status = oaktrail_set_brightness,
|
||||
};
|
||||
|
||||
int oaktrail_backlight_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
struct backlight_properties props;
|
||||
|
||||
memset(&props, 0, sizeof(struct backlight_properties));
|
||||
props.max_brightness = 100;
|
||||
props.type = BACKLIGHT_PLATFORM;
|
||||
|
||||
oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
|
||||
NULL, (void *)dev, &oaktrail_ops, &props);
|
||||
|
||||
if (IS_ERR(oaktrail_backlight_device))
|
||||
return PTR_ERR(oaktrail_backlight_device);
|
||||
|
||||
ret = device_backlight_init(dev);
|
||||
if (ret < 0) {
|
||||
backlight_device_unregister(oaktrail_backlight_device);
|
||||
return ret;
|
||||
}
|
||||
oaktrail_backlight_device->props.brightness = 100;
|
||||
oaktrail_backlight_device->props.max_brightness = 100;
|
||||
backlight_update_status(oaktrail_backlight_device);
|
||||
dev_priv->backlight_device = oaktrail_backlight_device;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Provide the Moorestown specific chip logic and low level methods
|
||||
* for power management
|
||||
*/
|
||||
|
||||
static void oaktrail_init_pm(struct drm_device *dev)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* oaktrail_save_display_registers - save registers lost on suspend
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Save the state we need in order to be able to restore the interface
|
||||
* upon resume from suspend
|
||||
*/
|
||||
static int oaktrail_save_display_registers(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int i;
|
||||
u32 pp_stat;
|
||||
|
||||
/* Display arbitration control + watermarks */
|
||||
dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
|
||||
dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1);
|
||||
dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2);
|
||||
dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3);
|
||||
dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4);
|
||||
dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5);
|
||||
dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
|
||||
dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
|
||||
|
||||
/* Pipe & plane A info */
|
||||
dev_priv->savePIPEACONF = PSB_RVDC32(PIPEACONF);
|
||||
dev_priv->savePIPEASRC = PSB_RVDC32(PIPEASRC);
|
||||
dev_priv->saveFPA0 = PSB_RVDC32(MRST_FPA0);
|
||||
dev_priv->saveFPA1 = PSB_RVDC32(MRST_FPA1);
|
||||
dev_priv->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A);
|
||||
dev_priv->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A);
|
||||
dev_priv->saveHBLANK_A = PSB_RVDC32(HBLANK_A);
|
||||
dev_priv->saveHSYNC_A = PSB_RVDC32(HSYNC_A);
|
||||
dev_priv->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A);
|
||||
dev_priv->saveVBLANK_A = PSB_RVDC32(VBLANK_A);
|
||||
dev_priv->saveVSYNC_A = PSB_RVDC32(VSYNC_A);
|
||||
dev_priv->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
|
||||
dev_priv->saveDSPACNTR = PSB_RVDC32(DSPACNTR);
|
||||
dev_priv->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE);
|
||||
dev_priv->saveDSPAADDR = PSB_RVDC32(DSPABASE);
|
||||
dev_priv->saveDSPASURF = PSB_RVDC32(DSPASURF);
|
||||
dev_priv->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF);
|
||||
dev_priv->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF);
|
||||
|
||||
/* Save cursor regs */
|
||||
dev_priv->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
|
||||
dev_priv->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
|
||||
dev_priv->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
|
||||
|
||||
/* Save palette (gamma) */
|
||||
for (i = 0; i < 256; i++)
|
||||
dev_priv->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2));
|
||||
|
||||
if (dev_priv->hdmi_priv)
|
||||
oaktrail_hdmi_save(dev);
|
||||
|
||||
/* Save performance state */
|
||||
dev_priv->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
|
||||
|
||||
/* LVDS state */
|
||||
dev_priv->savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
|
||||
dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
|
||||
dev_priv->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
|
||||
dev_priv->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
|
||||
dev_priv->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
|
||||
dev_priv->saveLVDS = PSB_RVDC32(LVDS);
|
||||
dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
|
||||
dev_priv->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
|
||||
dev_priv->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
|
||||
dev_priv->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
|
||||
|
||||
/* HW overlay */
|
||||
dev_priv->saveOV_OVADD = PSB_RVDC32(OV_OVADD);
|
||||
dev_priv->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
|
||||
dev_priv->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
|
||||
dev_priv->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
|
||||
dev_priv->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
|
||||
dev_priv->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
|
||||
dev_priv->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
|
||||
|
||||
/* DPST registers */
|
||||
dev_priv->saveHISTOGRAM_INT_CONTROL_REG =
|
||||
PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG =
|
||||
PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
|
||||
dev_priv->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
|
||||
if (dev_priv->iLVDS_enable) {
|
||||
/* Shut down the panel */
|
||||
PSB_WVDC32(0, PP_CONTROL);
|
||||
|
||||
do {
|
||||
pp_stat = PSB_RVDC32(PP_STATUS);
|
||||
} while (pp_stat & 0x80000000);
|
||||
|
||||
/* Turn off the plane */
|
||||
PSB_WVDC32(0x58000000, DSPACNTR);
|
||||
/* Trigger the plane disable */
|
||||
PSB_WVDC32(0, DSPASURF);
|
||||
|
||||
/* Wait ~4 ticks */
|
||||
msleep(4);
|
||||
|
||||
/* Turn off pipe */
|
||||
PSB_WVDC32(0x0, PIPEACONF);
|
||||
/* Wait ~8 ticks */
|
||||
msleep(8);
|
||||
|
||||
/* Turn off PLLs */
|
||||
PSB_WVDC32(0, MRST_DPLL_A);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* oaktrail_restore_display_registers - restore lost register state
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Restore register state that was lost during suspend and resume.
|
||||
*/
|
||||
static int oaktrail_restore_display_registers(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 pp_stat;
|
||||
int i;
|
||||
|
||||
/* Display arbitration + watermarks */
|
||||
PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
|
||||
PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);
|
||||
|
||||
/* Make sure VGA plane is off. it initializes to on after reset!*/
|
||||
PSB_WVDC32(0x80000000, VGACNTRL);
|
||||
|
||||
/* set the plls */
|
||||
PSB_WVDC32(dev_priv->saveFPA0, MRST_FPA0);
|
||||
PSB_WVDC32(dev_priv->saveFPA1, MRST_FPA1);
|
||||
|
||||
/* Actually enable it */
|
||||
PSB_WVDC32(dev_priv->saveDPLL_A, MRST_DPLL_A);
|
||||
DRM_UDELAY(150);
|
||||
|
||||
/* Restore mode */
|
||||
PSB_WVDC32(dev_priv->saveHTOTAL_A, HTOTAL_A);
|
||||
PSB_WVDC32(dev_priv->saveHBLANK_A, HBLANK_A);
|
||||
PSB_WVDC32(dev_priv->saveHSYNC_A, HSYNC_A);
|
||||
PSB_WVDC32(dev_priv->saveVTOTAL_A, VTOTAL_A);
|
||||
PSB_WVDC32(dev_priv->saveVBLANK_A, VBLANK_A);
|
||||
PSB_WVDC32(dev_priv->saveVSYNC_A, VSYNC_A);
|
||||
PSB_WVDC32(dev_priv->savePIPEASRC, PIPEASRC);
|
||||
PSB_WVDC32(dev_priv->saveBCLRPAT_A, BCLRPAT_A);
|
||||
|
||||
/* Restore performance mode*/
|
||||
PSB_WVDC32(dev_priv->savePERF_MODE, MRST_PERF_MODE);
|
||||
|
||||
/* Enable the pipe*/
|
||||
if (dev_priv->iLVDS_enable)
|
||||
PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF);
|
||||
|
||||
/* Set up the plane*/
|
||||
PSB_WVDC32(dev_priv->saveDSPALINOFF, DSPALINOFF);
|
||||
PSB_WVDC32(dev_priv->saveDSPASTRIDE, DSPASTRIDE);
|
||||
PSB_WVDC32(dev_priv->saveDSPATILEOFF, DSPATILEOFF);
|
||||
|
||||
/* Enable the plane */
|
||||
PSB_WVDC32(dev_priv->saveDSPACNTR, DSPACNTR);
|
||||
PSB_WVDC32(dev_priv->saveDSPASURF, DSPASURF);
|
||||
|
||||
/* Enable Cursor A */
|
||||
PSB_WVDC32(dev_priv->saveDSPACURSOR_CTRL, CURACNTR);
|
||||
PSB_WVDC32(dev_priv->saveDSPACURSOR_POS, CURAPOS);
|
||||
PSB_WVDC32(dev_priv->saveDSPACURSOR_BASE, CURABASE);
|
||||
|
||||
/* Restore palette (gamma) */
|
||||
for (i = 0; i < 256; i++)
|
||||
PSB_WVDC32(dev_priv->save_palette_a[i], PALETTE_A + (i << 2));
|
||||
|
||||
if (dev_priv->hdmi_priv)
|
||||
oaktrail_hdmi_restore(dev);
|
||||
|
||||
if (dev_priv->iLVDS_enable) {
|
||||
PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
|
||||
PSB_WVDC32(dev_priv->saveLVDS, LVDS); /*port 61180h*/
|
||||
PSB_WVDC32(dev_priv->savePFIT_CONTROL, PFIT_CONTROL);
|
||||
PSB_WVDC32(dev_priv->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
|
||||
PSB_WVDC32(dev_priv->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
|
||||
PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL);
|
||||
PSB_WVDC32(dev_priv->savePP_ON_DELAYS, LVDSPP_ON);
|
||||
PSB_WVDC32(dev_priv->savePP_OFF_DELAYS, LVDSPP_OFF);
|
||||
PSB_WVDC32(dev_priv->savePP_DIVISOR, PP_CYCLE);
|
||||
PSB_WVDC32(dev_priv->savePP_CONTROL, PP_CONTROL);
|
||||
}
|
||||
|
||||
/* Wait for cycle delay */
|
||||
do {
|
||||
pp_stat = PSB_RVDC32(PP_STATUS);
|
||||
} while (pp_stat & 0x08000000);
|
||||
|
||||
/* Wait for panel power up */
|
||||
do {
|
||||
pp_stat = PSB_RVDC32(PP_STATUS);
|
||||
} while (pp_stat & 0x10000000);
|
||||
|
||||
/* Restore HW overlay */
|
||||
PSB_WVDC32(dev_priv->saveOV_OVADD, OV_OVADD);
|
||||
PSB_WVDC32(dev_priv->saveOV_OGAMC0, OV_OGAMC0);
|
||||
PSB_WVDC32(dev_priv->saveOV_OGAMC1, OV_OGAMC1);
|
||||
PSB_WVDC32(dev_priv->saveOV_OGAMC2, OV_OGAMC2);
|
||||
PSB_WVDC32(dev_priv->saveOV_OGAMC3, OV_OGAMC3);
|
||||
PSB_WVDC32(dev_priv->saveOV_OGAMC4, OV_OGAMC4);
|
||||
PSB_WVDC32(dev_priv->saveOV_OGAMC5, OV_OGAMC5);
|
||||
|
||||
/* DPST registers */
|
||||
PSB_WVDC32(dev_priv->saveHISTOGRAM_INT_CONTROL_REG,
|
||||
HISTOGRAM_INT_CONTROL);
|
||||
PSB_WVDC32(dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG,
|
||||
HISTOGRAM_LOGIC_CONTROL);
|
||||
PSB_WVDC32(dev_priv->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* oaktrail_power_down - power down the display island
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Power down the display interface of our device
|
||||
*/
|
||||
static int oaktrail_power_down(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 pwr_mask ;
|
||||
u32 pwr_sts;
|
||||
|
||||
pwr_mask = PSB_PWRGT_DISPLAY_MASK;
|
||||
outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
|
||||
|
||||
while (true) {
|
||||
pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
|
||||
if ((pwr_sts & pwr_mask) == pwr_mask)
|
||||
break;
|
||||
else
|
||||
udelay(10);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* oaktrail_power_up
|
||||
*
|
||||
* Restore power to the specified island(s) (powergating)
|
||||
*/
|
||||
static int oaktrail_power_up(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
|
||||
u32 pwr_sts, pwr_cnt;
|
||||
|
||||
pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
|
||||
pwr_cnt &= ~pwr_mask;
|
||||
outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
|
||||
|
||||
while (true) {
|
||||
pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
|
||||
if ((pwr_sts & pwr_mask) == 0)
|
||||
break;
|
||||
else
|
||||
udelay(10);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void oaktrail_teardown(struct drm_device *dev)
|
||||
{
|
||||
oaktrail_hdmi_teardown(dev);
|
||||
}
|
||||
|
||||
const struct psb_ops oaktrail_chip_ops = {
|
||||
.name = "Oaktrail",
|
||||
.accel_2d = 1,
|
||||
.pipes = 2,
|
||||
.crtcs = 2,
|
||||
.sgx_offset = MRST_SGX_OFFSET,
|
||||
|
||||
.chip_setup = mid_chip_setup,
|
||||
.chip_teardown = oaktrail_teardown,
|
||||
.crtc_helper = &oaktrail_helper_funcs,
|
||||
.crtc_funcs = &psb_intel_crtc_funcs,
|
||||
|
||||
.output_init = oaktrail_output_init,
|
||||
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
.backlight_init = oaktrail_backlight_init,
|
||||
#endif
|
||||
|
||||
.init_pm = oaktrail_init_pm,
|
||||
.save_regs = oaktrail_save_display_registers,
|
||||
.restore_regs = oaktrail_restore_display_registers,
|
||||
.power_down = oaktrail_power_down,
|
||||
.power_up = oaktrail_power_up,
|
||||
|
||||
.i2c_bus = 1,
|
||||
};
|
852
drivers/gpu/drm/gma500/oaktrail_hdmi.c
Normal file
852
drivers/gpu/drm/gma500/oaktrail_hdmi.c
Normal file
@ -0,0 +1,852 @@
|
||||
/*
|
||||
* Copyright © 2010 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Li Peng <peng.li@intel.com>
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "psb_drv.h"
|
||||
|
||||
#define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
|
||||
#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
|
||||
|
||||
#define HDMI_HCR 0x1000
|
||||
#define HCR_ENABLE_HDCP (1 << 5)
|
||||
#define HCR_ENABLE_AUDIO (1 << 2)
|
||||
#define HCR_ENABLE_PIXEL (1 << 1)
|
||||
#define HCR_ENABLE_TMDS (1 << 0)
|
||||
|
||||
#define HDMI_HICR 0x1004
|
||||
#define HDMI_HSR 0x1008
|
||||
#define HDMI_HISR 0x100C
|
||||
#define HDMI_DETECT_HDP (1 << 0)
|
||||
|
||||
#define HDMI_VIDEO_REG 0x3000
|
||||
#define HDMI_UNIT_EN (1 << 7)
|
||||
#define HDMI_MODE_OUTPUT (1 << 0)
|
||||
#define HDMI_HBLANK_A 0x3100
|
||||
|
||||
#define HDMI_AUDIO_CTRL 0x4000
|
||||
#define HDMI_ENABLE_AUDIO (1 << 0)
|
||||
|
||||
#define PCH_HTOTAL_B 0x3100
|
||||
#define PCH_HBLANK_B 0x3104
|
||||
#define PCH_HSYNC_B 0x3108
|
||||
#define PCH_VTOTAL_B 0x310C
|
||||
#define PCH_VBLANK_B 0x3110
|
||||
#define PCH_VSYNC_B 0x3114
|
||||
#define PCH_PIPEBSRC 0x311C
|
||||
|
||||
#define PCH_PIPEB_DSL 0x3800
|
||||
#define PCH_PIPEB_SLC 0x3804
|
||||
#define PCH_PIPEBCONF 0x3808
|
||||
#define PCH_PIPEBSTAT 0x3824
|
||||
|
||||
#define CDVO_DFT 0x5000
|
||||
#define CDVO_SLEWRATE 0x5004
|
||||
#define CDVO_STRENGTH 0x5008
|
||||
#define CDVO_RCOMP 0x500C
|
||||
|
||||
#define DPLL_CTRL 0x6000
|
||||
#define DPLL_PDIV_SHIFT 16
|
||||
#define DPLL_PDIV_MASK (0xf << 16)
|
||||
#define DPLL_PWRDN (1 << 4)
|
||||
#define DPLL_RESET (1 << 3)
|
||||
#define DPLL_FASTEN (1 << 2)
|
||||
#define DPLL_ENSTAT (1 << 1)
|
||||
#define DPLL_DITHEN (1 << 0)
|
||||
|
||||
#define DPLL_DIV_CTRL 0x6004
|
||||
#define DPLL_CLKF_MASK 0xffffffc0
|
||||
#define DPLL_CLKR_MASK (0x3f)
|
||||
|
||||
#define DPLL_CLK_ENABLE 0x6008
|
||||
#define DPLL_EN_DISP (1 << 31)
|
||||
#define DPLL_SEL_HDMI (1 << 8)
|
||||
#define DPLL_EN_HDMI (1 << 1)
|
||||
#define DPLL_EN_VGA (1 << 0)
|
||||
|
||||
#define DPLL_ADJUST 0x600C
|
||||
#define DPLL_STATUS 0x6010
|
||||
#define DPLL_UPDATE 0x6014
|
||||
#define DPLL_DFT 0x6020
|
||||
|
||||
struct intel_range {
|
||||
int min, max;
|
||||
};
|
||||
|
||||
struct oaktrail_hdmi_limit {
|
||||
struct intel_range vco, np, nr, nf;
|
||||
};
|
||||
|
||||
struct oaktrail_hdmi_clock {
|
||||
int np;
|
||||
int nr;
|
||||
int nf;
|
||||
int dot;
|
||||
};
|
||||
|
||||
#define VCO_MIN 320000
|
||||
#define VCO_MAX 1650000
|
||||
#define NP_MIN 1
|
||||
#define NP_MAX 15
|
||||
#define NR_MIN 1
|
||||
#define NR_MAX 64
|
||||
#define NF_MIN 2
|
||||
#define NF_MAX 4095
|
||||
|
||||
static const struct oaktrail_hdmi_limit oaktrail_hdmi_limit = {
|
||||
.vco = { .min = VCO_MIN, .max = VCO_MAX },
|
||||
.np = { .min = NP_MIN, .max = NP_MAX },
|
||||
.nr = { .min = NR_MIN, .max = NR_MAX },
|
||||
.nf = { .min = NF_MIN, .max = NF_MAX },
|
||||
};
|
||||
|
||||
static void wait_for_vblank(struct drm_device *dev)
|
||||
{
|
||||
/* FIXME: Can we do this as a sleep ? */
|
||||
/* Wait for 20ms, i.e. one cycle at 50hz. */
|
||||
mdelay(20);
|
||||
}
|
||||
|
||||
static void scu_busy_loop(void *scu_base)
|
||||
{
|
||||
u32 status = 0;
|
||||
u32 loop_count = 0;
|
||||
|
||||
status = readl(scu_base + 0x04);
|
||||
while (status & 1) {
|
||||
udelay(1); /* scu processing time is in few u secods */
|
||||
status = readl(scu_base + 0x04);
|
||||
loop_count++;
|
||||
/* break if scu doesn't reset busy bit after huge retry */
|
||||
if (loop_count > 1000) {
|
||||
DRM_DEBUG_KMS("SCU IPC timed out");
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void oaktrail_hdmi_reset(struct drm_device *dev)
|
||||
{
|
||||
void *base;
|
||||
/* FIXME: at least make these defines */
|
||||
unsigned int scu_ipc_mmio = 0xff11c000;
|
||||
int scu_len = 1024;
|
||||
|
||||
base = ioremap((resource_size_t)scu_ipc_mmio, scu_len);
|
||||
if (base == NULL) {
|
||||
DRM_ERROR("failed to map SCU mmio\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* scu ipc: assert hdmi controller reset */
|
||||
writel(0xff11d118, base + 0x0c);
|
||||
writel(0x7fffffdf, base + 0x80);
|
||||
writel(0x42005, base + 0x0);
|
||||
scu_busy_loop(base);
|
||||
|
||||
/* scu ipc: de-assert hdmi controller reset */
|
||||
writel(0xff11d118, base + 0x0c);
|
||||
writel(0x7fffffff, base + 0x80);
|
||||
writel(0x42005, base + 0x0);
|
||||
scu_busy_loop(base);
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
static void oaktrail_hdmi_audio_enable(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
|
||||
HDMI_WRITE(HDMI_HCR, 0x67);
|
||||
HDMI_READ(HDMI_HCR);
|
||||
|
||||
HDMI_WRITE(0x51a8, 0x10);
|
||||
HDMI_READ(0x51a8);
|
||||
|
||||
HDMI_WRITE(HDMI_AUDIO_CTRL, 0x1);
|
||||
HDMI_READ(HDMI_AUDIO_CTRL);
|
||||
}
|
||||
|
||||
static void oaktrail_hdmi_audio_disable(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
|
||||
HDMI_WRITE(0x51a8, 0x0);
|
||||
HDMI_READ(0x51a8);
|
||||
|
||||
HDMI_WRITE(HDMI_AUDIO_CTRL, 0x0);
|
||||
HDMI_READ(HDMI_AUDIO_CTRL);
|
||||
|
||||
HDMI_WRITE(HDMI_HCR, 0x47);
|
||||
HDMI_READ(HDMI_HCR);
|
||||
}
|
||||
|
||||
void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
u32 temp;
|
||||
|
||||
switch (mode) {
|
||||
case DRM_MODE_DPMS_OFF:
|
||||
/* Disable VGACNTRL */
|
||||
REG_WRITE(VGACNTRL, 0x80000000);
|
||||
|
||||
/* Disable plane */
|
||||
temp = REG_READ(DSPBCNTR);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
|
||||
REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
|
||||
REG_READ(DSPBCNTR);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
|
||||
REG_READ(DSPBSURF);
|
||||
}
|
||||
|
||||
/* Disable pipe B */
|
||||
temp = REG_READ(PIPEBCONF);
|
||||
if ((temp & PIPEACONF_ENABLE) != 0) {
|
||||
REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
|
||||
REG_READ(PIPEBCONF);
|
||||
}
|
||||
|
||||
/* Disable LNW Pipes, etc */
|
||||
temp = REG_READ(PCH_PIPEBCONF);
|
||||
if ((temp & PIPEACONF_ENABLE) != 0) {
|
||||
REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
|
||||
REG_READ(PCH_PIPEBCONF);
|
||||
}
|
||||
/* wait for pipe off */
|
||||
udelay(150);
|
||||
/* Disable dpll */
|
||||
temp = REG_READ(DPLL_CTRL);
|
||||
if ((temp & DPLL_PWRDN) == 0) {
|
||||
REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
|
||||
REG_WRITE(DPLL_STATUS, 0x1);
|
||||
}
|
||||
/* wait for dpll off */
|
||||
udelay(150);
|
||||
break;
|
||||
case DRM_MODE_DPMS_ON:
|
||||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
/* Enable dpll */
|
||||
temp = REG_READ(DPLL_CTRL);
|
||||
if ((temp & DPLL_PWRDN) != 0) {
|
||||
REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
|
||||
temp = REG_READ(DPLL_CLK_ENABLE);
|
||||
REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
|
||||
REG_READ(DPLL_CLK_ENABLE);
|
||||
}
|
||||
/* wait for dpll warm up */
|
||||
udelay(150);
|
||||
|
||||
/* Enable pipe B */
|
||||
temp = REG_READ(PIPEBCONF);
|
||||
if ((temp & PIPEACONF_ENABLE) == 0) {
|
||||
REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
|
||||
REG_READ(PIPEBCONF);
|
||||
}
|
||||
|
||||
/* Enable LNW Pipe B */
|
||||
temp = REG_READ(PCH_PIPEBCONF);
|
||||
if ((temp & PIPEACONF_ENABLE) == 0) {
|
||||
REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
|
||||
REG_READ(PCH_PIPEBCONF);
|
||||
}
|
||||
wait_for_vblank(dev);
|
||||
|
||||
/* Enable plane */
|
||||
temp = REG_READ(DSPBCNTR);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
|
||||
REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
|
||||
REG_READ(DSPBSURF);
|
||||
}
|
||||
psb_intel_crtc_load_lut(crtc);
|
||||
}
|
||||
/* DSPARB */
|
||||
REG_WRITE(DSPARB, 0x00003fbf);
|
||||
/* FW1 */
|
||||
REG_WRITE(0x70034, 0x3f880a0a);
|
||||
/* FW2 */
|
||||
REG_WRITE(0x70038, 0x0b060808);
|
||||
/* FW4 */
|
||||
REG_WRITE(0x70050, 0x08030404);
|
||||
/* FW5 */
|
||||
REG_WRITE(0x70054, 0x04040404);
|
||||
/* LNC Chicken Bits */
|
||||
REG_WRITE(0x70400, 0x4000);
|
||||
}
|
||||
|
||||
|
||||
static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
static int dpms_mode = -1;
|
||||
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
u32 temp;
|
||||
|
||||
if (dpms_mode == mode)
|
||||
return;
|
||||
|
||||
if (mode != DRM_MODE_DPMS_ON)
|
||||
temp = 0x0;
|
||||
else
|
||||
temp = 0x99;
|
||||
|
||||
dpms_mode = mode;
|
||||
HDMI_WRITE(HDMI_VIDEO_REG, temp);
|
||||
}
|
||||
|
||||
static unsigned int htotal_calculate(struct drm_display_mode *mode)
|
||||
{
|
||||
u32 htotal, new_crtc_htotal;
|
||||
|
||||
htotal = (mode->crtc_hdisplay - 1) | ((mode->crtc_htotal - 1) << 16);
|
||||
|
||||
/*
|
||||
* 1024 x 768 new_crtc_htotal = 0x1024;
|
||||
* 1280 x 1024 new_crtc_htotal = 0x0c34;
|
||||
*/
|
||||
new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock;
|
||||
|
||||
return (mode->crtc_hdisplay - 1) | (new_crtc_htotal << 16);
|
||||
}
|
||||
|
||||
static void oaktrail_hdmi_find_dpll(struct drm_crtc *crtc, int target,
|
||||
int refclk, struct oaktrail_hdmi_clock *best_clock)
|
||||
{
|
||||
int np_min, np_max, nr_min, nr_max;
|
||||
int np, nr, nf;
|
||||
|
||||
np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10);
|
||||
np_max = oaktrail_hdmi_limit.vco.max / (target * 10);
|
||||
if (np_min < oaktrail_hdmi_limit.np.min)
|
||||
np_min = oaktrail_hdmi_limit.np.min;
|
||||
if (np_max > oaktrail_hdmi_limit.np.max)
|
||||
np_max = oaktrail_hdmi_limit.np.max;
|
||||
|
||||
nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max));
|
||||
nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min));
|
||||
if (nr_min < oaktrail_hdmi_limit.nr.min)
|
||||
nr_min = oaktrail_hdmi_limit.nr.min;
|
||||
if (nr_max > oaktrail_hdmi_limit.nr.max)
|
||||
nr_max = oaktrail_hdmi_limit.nr.max;
|
||||
|
||||
np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max));
|
||||
nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np));
|
||||
nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk);
|
||||
DRM_DEBUG_KMS("np, nr, nf %d %d %d\n", np, nr, nf);
|
||||
|
||||
/*
|
||||
* 1024 x 768 np = 1; nr = 0x26; nf = 0x0fd8000;
|
||||
* 1280 x 1024 np = 1; nr = 0x17; nf = 0x1034000;
|
||||
*/
|
||||
best_clock->np = np;
|
||||
best_clock->nr = nr - 1;
|
||||
best_clock->nf = (nf << 14);
|
||||
}
|
||||
|
||||
int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode,
|
||||
int x, int y,
|
||||
struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
int pipe = 1;
|
||||
int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
|
||||
int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
|
||||
int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
|
||||
int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
|
||||
int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
|
||||
int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
|
||||
int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
|
||||
int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
|
||||
int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
int refclk;
|
||||
struct oaktrail_hdmi_clock clock;
|
||||
u32 dspcntr, pipeconf, dpll, temp;
|
||||
int dspcntr_reg = DSPBCNTR;
|
||||
|
||||
/* Disable the VGA plane that we never use */
|
||||
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
|
||||
|
||||
/* XXX: Disable the panel fitter if it was on our pipe */
|
||||
|
||||
/* Disable dpll if necessary */
|
||||
dpll = REG_READ(DPLL_CTRL);
|
||||
if ((dpll & DPLL_PWRDN) == 0) {
|
||||
REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));
|
||||
REG_WRITE(DPLL_DIV_CTRL, 0x00000000);
|
||||
REG_WRITE(DPLL_STATUS, 0x1);
|
||||
}
|
||||
udelay(150);
|
||||
|
||||
/* reset controller: FIXME - can we sort out the ioremap mess ? */
|
||||
iounmap(hdmi_dev->regs);
|
||||
oaktrail_hdmi_reset(dev);
|
||||
|
||||
/* program and enable dpll */
|
||||
refclk = 25000;
|
||||
oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock);
|
||||
|
||||
/* Setting DPLL */
|
||||
dpll = REG_READ(DPLL_CTRL);
|
||||
dpll &= ~DPLL_PDIV_MASK;
|
||||
dpll &= ~(DPLL_PWRDN | DPLL_RESET);
|
||||
REG_WRITE(DPLL_CTRL, 0x00000008);
|
||||
REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));
|
||||
REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));
|
||||
REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));
|
||||
REG_WRITE(DPLL_UPDATE, 0x80000000);
|
||||
REG_WRITE(DPLL_CLK_ENABLE, 0x80050102);
|
||||
udelay(150);
|
||||
|
||||
hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
|
||||
if (hdmi_dev->regs == NULL) {
|
||||
DRM_ERROR("failed to do hdmi mmio mapping\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* configure HDMI */
|
||||
HDMI_WRITE(0x1004, 0x1fd);
|
||||
HDMI_WRITE(0x2000, 0x1);
|
||||
HDMI_WRITE(0x2008, 0x0);
|
||||
HDMI_WRITE(0x3130, 0x8);
|
||||
HDMI_WRITE(0x101c, 0x1800810);
|
||||
|
||||
temp = htotal_calculate(adjusted_mode);
|
||||
REG_WRITE(htot_reg, temp);
|
||||
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
|
||||
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
|
||||
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
|
||||
REG_WRITE(pipesrc_reg,
|
||||
((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
|
||||
|
||||
REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
|
||||
REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
|
||||
REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
|
||||
REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
|
||||
REG_WRITE(PCH_PIPEBSRC,
|
||||
((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
|
||||
|
||||
temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
|
||||
HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp);
|
||||
|
||||
REG_WRITE(dspsize_reg,
|
||||
((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
|
||||
REG_WRITE(dsppos_reg, 0);
|
||||
|
||||
/* Flush the plane changes */
|
||||
{
|
||||
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
||||
crtc_funcs->mode_set_base(crtc, x, y, old_fb);
|
||||
}
|
||||
|
||||
/* Set up the display plane register */
|
||||
dspcntr = REG_READ(dspcntr_reg);
|
||||
dspcntr |= DISPPLANE_GAMMA_ENABLE;
|
||||
dspcntr |= DISPPLANE_SEL_PIPE_B;
|
||||
dspcntr |= DISPLAY_PLANE_ENABLE;
|
||||
|
||||
/* setup pipeconf */
|
||||
pipeconf = REG_READ(pipeconf_reg);
|
||||
pipeconf |= PIPEACONF_ENABLE;
|
||||
|
||||
REG_WRITE(pipeconf_reg, pipeconf);
|
||||
REG_READ(pipeconf_reg);
|
||||
|
||||
REG_WRITE(PCH_PIPEBCONF, pipeconf);
|
||||
REG_READ(PCH_PIPEBCONF);
|
||||
wait_for_vblank(dev);
|
||||
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
wait_for_vblank(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int oaktrail_hdmi_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
if (mode->clock > 165000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
if (mode->clock < 20000)
|
||||
return MODE_CLOCK_LOW;
|
||||
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
static bool oaktrail_hdmi_mode_fixup(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static enum drm_connector_status
|
||||
oaktrail_hdmi_detect(struct drm_connector *connector, bool force)
|
||||
{
|
||||
enum drm_connector_status status;
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
u32 temp;
|
||||
|
||||
temp = HDMI_READ(HDMI_HSR);
|
||||
DRM_DEBUG_KMS("HDMI_HSR %x\n", temp);
|
||||
|
||||
if ((temp & HDMI_DETECT_HDP) != 0)
|
||||
status = connector_status_connected;
|
||||
else
|
||||
status = connector_status_disconnected;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static const unsigned char raw_edid[] = {
|
||||
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xac, 0x2f, 0xa0,
|
||||
0x53, 0x55, 0x33, 0x30, 0x16, 0x13, 0x01, 0x03, 0x0e, 0x3a, 0x24, 0x78,
|
||||
0xea, 0xe9, 0xf5, 0xac, 0x51, 0x30, 0xb4, 0x25, 0x11, 0x50, 0x54, 0xa5,
|
||||
0x4b, 0x00, 0x81, 0x80, 0xa9, 0x40, 0x71, 0x4f, 0xb3, 0x00, 0x01, 0x01,
|
||||
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
|
||||
0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x46, 0x6c, 0x21, 0x00, 0x00, 0x1a,
|
||||
0x00, 0x00, 0x00, 0xff, 0x00, 0x47, 0x4e, 0x37, 0x32, 0x31, 0x39, 0x35,
|
||||
0x52, 0x30, 0x33, 0x55, 0x53, 0x0a, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x44,
|
||||
0x45, 0x4c, 0x4c, 0x20, 0x32, 0x37, 0x30, 0x39, 0x57, 0x0a, 0x20, 0x20,
|
||||
0x00, 0x00, 0x00, 0xfd, 0x00, 0x38, 0x4c, 0x1e, 0x53, 0x11, 0x00, 0x0a,
|
||||
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x8d
|
||||
};
|
||||
|
||||
static int oaktrail_hdmi_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct i2c_adapter *i2c_adap;
|
||||
struct edid *edid;
|
||||
struct drm_display_mode *mode, *t;
|
||||
int i = 0, ret = 0;
|
||||
|
||||
i2c_adap = i2c_get_adapter(3);
|
||||
if (i2c_adap == NULL) {
|
||||
DRM_ERROR("No ddc adapter available!\n");
|
||||
edid = (struct edid *)raw_edid;
|
||||
} else {
|
||||
edid = (struct edid *)raw_edid;
|
||||
/* FIXME ? edid = drm_get_edid(connector, i2c_adap); */
|
||||
}
|
||||
|
||||
if (edid) {
|
||||
drm_mode_connector_update_edid_property(connector, edid);
|
||||
ret = drm_add_edid_modes(connector, edid);
|
||||
connector->display_info.raw_edid = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* prune modes that require frame buffer bigger than stolen mem
|
||||
*/
|
||||
list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
|
||||
if ((mode->hdisplay * mode->vdisplay * 4) >= dev_priv->vram_stolen_size) {
|
||||
i++;
|
||||
drm_mode_remove(connector, mode);
|
||||
}
|
||||
}
|
||||
return ret - i;
|
||||
}
|
||||
|
||||
static void oaktrail_hdmi_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
|
||||
oaktrail_hdmi_audio_enable(dev);
|
||||
return;
|
||||
}
|
||||
|
||||
static void oaktrail_hdmi_destroy(struct drm_connector *connector)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = {
|
||||
.dpms = oaktrail_hdmi_dpms,
|
||||
.mode_fixup = oaktrail_hdmi_mode_fixup,
|
||||
.prepare = psb_intel_encoder_prepare,
|
||||
.mode_set = oaktrail_hdmi_mode_set,
|
||||
.commit = psb_intel_encoder_commit,
|
||||
};
|
||||
|
||||
static const struct drm_connector_helper_funcs
|
||||
oaktrail_hdmi_connector_helper_funcs = {
|
||||
.get_modes = oaktrail_hdmi_get_modes,
|
||||
.mode_valid = oaktrail_hdmi_mode_valid,
|
||||
.best_encoder = psb_intel_best_encoder,
|
||||
};
|
||||
|
||||
static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = {
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.detect = oaktrail_hdmi_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.destroy = oaktrail_hdmi_destroy,
|
||||
};
|
||||
|
||||
static void oaktrail_hdmi_enc_destroy(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_encoder_cleanup(encoder);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_funcs oaktrail_hdmi_enc_funcs = {
|
||||
.destroy = oaktrail_hdmi_enc_destroy,
|
||||
};
|
||||
|
||||
void oaktrail_hdmi_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output;
|
||||
struct drm_connector *connector;
|
||||
struct drm_encoder *encoder;
|
||||
|
||||
psb_intel_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
|
||||
if (!psb_intel_output)
|
||||
return;
|
||||
|
||||
psb_intel_output->mode_dev = mode_dev;
|
||||
connector = &psb_intel_output->base;
|
||||
encoder = &psb_intel_output->enc;
|
||||
drm_connector_init(dev, &psb_intel_output->base,
|
||||
&oaktrail_hdmi_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_DVID);
|
||||
|
||||
drm_encoder_init(dev, &psb_intel_output->enc,
|
||||
&oaktrail_hdmi_enc_funcs,
|
||||
DRM_MODE_ENCODER_TMDS);
|
||||
|
||||
drm_mode_connector_attach_encoder(&psb_intel_output->base,
|
||||
&psb_intel_output->enc);
|
||||
|
||||
psb_intel_output->type = INTEL_OUTPUT_HDMI;
|
||||
drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs);
|
||||
drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs);
|
||||
|
||||
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = false;
|
||||
connector->doublescan_allowed = false;
|
||||
drm_sysfs_connector_add(connector);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) },
|
||||
{}
|
||||
};
|
||||
|
||||
void oaktrail_hdmi_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct pci_dev *pdev;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev;
|
||||
int ret;
|
||||
|
||||
pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x080d, NULL);
|
||||
if (!pdev)
|
||||
return;
|
||||
|
||||
hdmi_dev = kzalloc(sizeof(struct oaktrail_hdmi_dev), GFP_KERNEL);
|
||||
if (!hdmi_dev) {
|
||||
dev_err(dev->dev, "failed to allocate memory\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "failed to enable hdmi controller\n");
|
||||
goto free;
|
||||
}
|
||||
|
||||
hdmi_dev->mmio = pci_resource_start(pdev, 0);
|
||||
hdmi_dev->mmio_len = pci_resource_len(pdev, 0);
|
||||
hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
|
||||
if (!hdmi_dev->regs) {
|
||||
dev_err(dev->dev, "failed to map hdmi mmio\n");
|
||||
goto free;
|
||||
}
|
||||
|
||||
hdmi_dev->dev = pdev;
|
||||
pci_set_drvdata(pdev, hdmi_dev);
|
||||
|
||||
/* Initialize i2c controller */
|
||||
ret = oaktrail_hdmi_i2c_init(hdmi_dev->dev);
|
||||
if (ret)
|
||||
dev_err(dev->dev, "HDMI I2C initialization failed\n");
|
||||
|
||||
dev_priv->hdmi_priv = hdmi_dev;
|
||||
oaktrail_hdmi_audio_disable(dev);
|
||||
return;
|
||||
|
||||
free:
|
||||
kfree(hdmi_dev);
|
||||
out:
|
||||
return;
|
||||
}
|
||||
|
||||
void oaktrail_hdmi_teardown(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
if (hdmi_dev) {
|
||||
pdev = hdmi_dev->dev;
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
oaktrail_hdmi_i2c_exit(pdev);
|
||||
iounmap(hdmi_dev->regs);
|
||||
kfree(hdmi_dev);
|
||||
pci_dev_put(pdev);
|
||||
}
|
||||
}
|
||||
|
||||
/* save HDMI register state */
|
||||
void oaktrail_hdmi_save(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
int i;
|
||||
|
||||
/* dpll */
|
||||
hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL);
|
||||
hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL);
|
||||
hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST);
|
||||
hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE);
|
||||
hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
|
||||
|
||||
/* pipe B */
|
||||
dev_priv->savePIPEBCONF = PSB_RVDC32(PIPEBCONF);
|
||||
dev_priv->savePIPEBSRC = PSB_RVDC32(PIPEBSRC);
|
||||
dev_priv->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B);
|
||||
dev_priv->saveHBLANK_B = PSB_RVDC32(HBLANK_B);
|
||||
dev_priv->saveHSYNC_B = PSB_RVDC32(HSYNC_B);
|
||||
dev_priv->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B);
|
||||
dev_priv->saveVBLANK_B = PSB_RVDC32(VBLANK_B);
|
||||
dev_priv->saveVSYNC_B = PSB_RVDC32(VSYNC_B);
|
||||
|
||||
hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
|
||||
hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
|
||||
hdmi_dev->savePCH_HTOTAL_B = PSB_RVDC32(PCH_HTOTAL_B);
|
||||
hdmi_dev->savePCH_HBLANK_B = PSB_RVDC32(PCH_HBLANK_B);
|
||||
hdmi_dev->savePCH_HSYNC_B = PSB_RVDC32(PCH_HSYNC_B);
|
||||
hdmi_dev->savePCH_VTOTAL_B = PSB_RVDC32(PCH_VTOTAL_B);
|
||||
hdmi_dev->savePCH_VBLANK_B = PSB_RVDC32(PCH_VBLANK_B);
|
||||
hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
|
||||
|
||||
/* plane */
|
||||
dev_priv->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR);
|
||||
dev_priv->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE);
|
||||
dev_priv->saveDSPBADDR = PSB_RVDC32(DSPBBASE);
|
||||
dev_priv->saveDSPBSURF = PSB_RVDC32(DSPBSURF);
|
||||
dev_priv->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF);
|
||||
dev_priv->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF);
|
||||
|
||||
/* cursor B */
|
||||
dev_priv->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
|
||||
dev_priv->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
|
||||
dev_priv->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
|
||||
|
||||
/* save palette */
|
||||
for (i = 0; i < 256; i++)
|
||||
dev_priv->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2));
|
||||
}
|
||||
|
||||
/* restore HDMI register state */
|
||||
void oaktrail_hdmi_restore(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
|
||||
int i;
|
||||
|
||||
/* dpll */
|
||||
PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL);
|
||||
PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL);
|
||||
PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST);
|
||||
PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE);
|
||||
PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE);
|
||||
DRM_UDELAY(150);
|
||||
|
||||
/* pipe */
|
||||
PSB_WVDC32(dev_priv->savePIPEBSRC, PIPEBSRC);
|
||||
PSB_WVDC32(dev_priv->saveHTOTAL_B, HTOTAL_B);
|
||||
PSB_WVDC32(dev_priv->saveHBLANK_B, HBLANK_B);
|
||||
PSB_WVDC32(dev_priv->saveHSYNC_B, HSYNC_B);
|
||||
PSB_WVDC32(dev_priv->saveVTOTAL_B, VTOTAL_B);
|
||||
PSB_WVDC32(dev_priv->saveVBLANK_B, VBLANK_B);
|
||||
PSB_WVDC32(dev_priv->saveVSYNC_B, VSYNC_B);
|
||||
|
||||
PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
|
||||
PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
|
||||
PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B);
|
||||
PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B, PCH_HSYNC_B);
|
||||
PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B);
|
||||
PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
|
||||
PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
|
||||
|
||||
PSB_WVDC32(dev_priv->savePIPEBCONF, PIPEBCONF);
|
||||
PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
|
||||
|
||||
/* plane */
|
||||
PSB_WVDC32(dev_priv->saveDSPBLINOFF, DSPBLINOFF);
|
||||
PSB_WVDC32(dev_priv->saveDSPBSTRIDE, DSPBSTRIDE);
|
||||
PSB_WVDC32(dev_priv->saveDSPBTILEOFF, DSPBTILEOFF);
|
||||
PSB_WVDC32(dev_priv->saveDSPBCNTR, DSPBCNTR);
|
||||
PSB_WVDC32(dev_priv->saveDSPBSURF, DSPBSURF);
|
||||
|
||||
/* cursor B */
|
||||
PSB_WVDC32(dev_priv->saveDSPBCURSOR_CTRL, CURBCNTR);
|
||||
PSB_WVDC32(dev_priv->saveDSPBCURSOR_POS, CURBPOS);
|
||||
PSB_WVDC32(dev_priv->saveDSPBCURSOR_BASE, CURBBASE);
|
||||
|
||||
/* restore palette */
|
||||
for (i = 0; i < 256; i++)
|
||||
PSB_WVDC32(dev_priv->save_palette_b[i], PALETTE_B + (i << 2));
|
||||
}
|
328
drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c
Normal file
328
drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c
Normal file
@ -0,0 +1,328 @@
|
||||
/*
|
||||
* Copyright © 2010 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Li Peng <peng.li@intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/export.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/delay.h>
|
||||
#include "psb_drv.h"
|
||||
|
||||
#define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
|
||||
#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
|
||||
|
||||
#define HDMI_HCR 0x1000
|
||||
#define HCR_DETECT_HDP (1 << 6)
|
||||
#define HCR_ENABLE_HDCP (1 << 5)
|
||||
#define HCR_ENABLE_AUDIO (1 << 2)
|
||||
#define HCR_ENABLE_PIXEL (1 << 1)
|
||||
#define HCR_ENABLE_TMDS (1 << 0)
|
||||
#define HDMI_HICR 0x1004
|
||||
#define HDMI_INTR_I2C_ERROR (1 << 4)
|
||||
#define HDMI_INTR_I2C_FULL (1 << 3)
|
||||
#define HDMI_INTR_I2C_DONE (1 << 2)
|
||||
#define HDMI_INTR_HPD (1 << 0)
|
||||
#define HDMI_HSR 0x1008
|
||||
#define HDMI_HISR 0x100C
|
||||
#define HDMI_HI2CRDB0 0x1200
|
||||
#define HDMI_HI2CHCR 0x1240
|
||||
#define HI2C_HDCP_WRITE (0 << 2)
|
||||
#define HI2C_HDCP_RI_READ (1 << 2)
|
||||
#define HI2C_HDCP_READ (2 << 2)
|
||||
#define HI2C_EDID_READ (3 << 2)
|
||||
#define HI2C_READ_CONTINUE (1 << 1)
|
||||
#define HI2C_ENABLE_TRANSACTION (1 << 0)
|
||||
|
||||
#define HDMI_ICRH 0x1100
|
||||
#define HDMI_HI2CTDR0 0x1244
|
||||
#define HDMI_HI2CTDR1 0x1248
|
||||
|
||||
#define I2C_STAT_INIT 0
|
||||
#define I2C_READ_DONE 1
|
||||
#define I2C_TRANSACTION_DONE 2
|
||||
|
||||
struct hdmi_i2c_dev {
|
||||
struct i2c_adapter *adap;
|
||||
struct mutex i2c_lock;
|
||||
struct completion complete;
|
||||
int status;
|
||||
struct i2c_msg *msg;
|
||||
int buf_offset;
|
||||
};
|
||||
|
||||
static void hdmi_i2c_irq_enable(struct oaktrail_hdmi_dev *hdmi_dev)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
temp = HDMI_READ(HDMI_HICR);
|
||||
temp |= (HDMI_INTR_I2C_ERROR | HDMI_INTR_I2C_FULL | HDMI_INTR_I2C_DONE);
|
||||
HDMI_WRITE(HDMI_HICR, temp);
|
||||
HDMI_READ(HDMI_HICR);
|
||||
}
|
||||
|
||||
static void hdmi_i2c_irq_disable(struct oaktrail_hdmi_dev *hdmi_dev)
|
||||
{
|
||||
HDMI_WRITE(HDMI_HICR, 0x0);
|
||||
HDMI_READ(HDMI_HICR);
|
||||
}
|
||||
|
||||
static int xfer_read(struct i2c_adapter *adap, struct i2c_msg *pmsg)
|
||||
{
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
|
||||
struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
|
||||
u32 temp;
|
||||
|
||||
i2c_dev->status = I2C_STAT_INIT;
|
||||
i2c_dev->msg = pmsg;
|
||||
i2c_dev->buf_offset = 0;
|
||||
INIT_COMPLETION(i2c_dev->complete);
|
||||
|
||||
/* Enable I2C transaction */
|
||||
temp = ((pmsg->len) << 20) | HI2C_EDID_READ | HI2C_ENABLE_TRANSACTION;
|
||||
HDMI_WRITE(HDMI_HI2CHCR, temp);
|
||||
HDMI_READ(HDMI_HI2CHCR);
|
||||
|
||||
while (i2c_dev->status != I2C_TRANSACTION_DONE)
|
||||
wait_for_completion_interruptible_timeout(&i2c_dev->complete,
|
||||
10 * HZ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xfer_write(struct i2c_adapter *adap, struct i2c_msg *pmsg)
|
||||
{
|
||||
/*
|
||||
* XXX: i2c write seems isn't useful for EDID probe, don't do anything
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int oaktrail_hdmi_i2c_access(struct i2c_adapter *adap,
|
||||
struct i2c_msg *pmsg,
|
||||
int num)
|
||||
{
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
|
||||
struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
|
||||
int i, err = 0;
|
||||
|
||||
mutex_lock(&i2c_dev->i2c_lock);
|
||||
|
||||
/* Enable i2c unit */
|
||||
HDMI_WRITE(HDMI_ICRH, 0x00008760);
|
||||
|
||||
/* Enable irq */
|
||||
hdmi_i2c_irq_enable(hdmi_dev);
|
||||
for (i = 0; i < num; i++) {
|
||||
if (pmsg->len && pmsg->buf) {
|
||||
if (pmsg->flags & I2C_M_RD)
|
||||
err = xfer_read(adap, pmsg);
|
||||
else
|
||||
err = xfer_write(adap, pmsg);
|
||||
}
|
||||
pmsg++; /* next message */
|
||||
}
|
||||
|
||||
/* Disable irq */
|
||||
hdmi_i2c_irq_disable(hdmi_dev);
|
||||
|
||||
mutex_unlock(&i2c_dev->i2c_lock);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static u32 oaktrail_hdmi_i2c_func(struct i2c_adapter *adapter)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm oaktrail_hdmi_i2c_algorithm = {
|
||||
.master_xfer = oaktrail_hdmi_i2c_access,
|
||||
.functionality = oaktrail_hdmi_i2c_func,
|
||||
};
|
||||
|
||||
static struct i2c_adapter oaktrail_hdmi_i2c_adapter = {
|
||||
.name = "oaktrail_hdmi_i2c",
|
||||
.nr = 3,
|
||||
.owner = THIS_MODULE,
|
||||
.class = I2C_CLASS_DDC,
|
||||
.algo = &oaktrail_hdmi_i2c_algorithm,
|
||||
};
|
||||
|
||||
static void hdmi_i2c_read(struct oaktrail_hdmi_dev *hdmi_dev)
|
||||
{
|
||||
struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
|
||||
struct i2c_msg *msg = i2c_dev->msg;
|
||||
u8 *buf = msg->buf;
|
||||
u32 temp;
|
||||
int i, offset;
|
||||
|
||||
offset = i2c_dev->buf_offset;
|
||||
for (i = 0; i < 0x10; i++) {
|
||||
temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4));
|
||||
memcpy(buf + (offset + i * 4), &temp, 4);
|
||||
}
|
||||
i2c_dev->buf_offset += (0x10 * 4);
|
||||
|
||||
/* clearing read buffer full intr */
|
||||
temp = HDMI_READ(HDMI_HISR);
|
||||
HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_FULL);
|
||||
HDMI_READ(HDMI_HISR);
|
||||
|
||||
/* continue read transaction */
|
||||
temp = HDMI_READ(HDMI_HI2CHCR);
|
||||
HDMI_WRITE(HDMI_HI2CHCR, temp | HI2C_READ_CONTINUE);
|
||||
HDMI_READ(HDMI_HI2CHCR);
|
||||
|
||||
i2c_dev->status = I2C_READ_DONE;
|
||||
return;
|
||||
}
|
||||
|
||||
static void hdmi_i2c_transaction_done(struct oaktrail_hdmi_dev *hdmi_dev)
|
||||
{
|
||||
struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
|
||||
u32 temp;
|
||||
|
||||
/* clear transaction done intr */
|
||||
temp = HDMI_READ(HDMI_HISR);
|
||||
HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_DONE);
|
||||
HDMI_READ(HDMI_HISR);
|
||||
|
||||
|
||||
temp = HDMI_READ(HDMI_HI2CHCR);
|
||||
HDMI_WRITE(HDMI_HI2CHCR, temp & ~HI2C_ENABLE_TRANSACTION);
|
||||
HDMI_READ(HDMI_HI2CHCR);
|
||||
|
||||
i2c_dev->status = I2C_TRANSACTION_DONE;
|
||||
return;
|
||||
}
|
||||
|
||||
static irqreturn_t oaktrail_hdmi_i2c_handler(int this_irq, void *dev)
|
||||
{
|
||||
struct oaktrail_hdmi_dev *hdmi_dev = dev;
|
||||
struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
|
||||
u32 stat;
|
||||
|
||||
stat = HDMI_READ(HDMI_HISR);
|
||||
|
||||
if (stat & HDMI_INTR_HPD) {
|
||||
HDMI_WRITE(HDMI_HISR, stat | HDMI_INTR_HPD);
|
||||
HDMI_READ(HDMI_HISR);
|
||||
}
|
||||
|
||||
if (stat & HDMI_INTR_I2C_FULL)
|
||||
hdmi_i2c_read(hdmi_dev);
|
||||
|
||||
if (stat & HDMI_INTR_I2C_DONE)
|
||||
hdmi_i2c_transaction_done(hdmi_dev);
|
||||
|
||||
complete(&i2c_dev->complete);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/*
|
||||
* choose alternate function 2 of GPIO pin 52, 53,
|
||||
* which is used by HDMI I2C logic
|
||||
*/
|
||||
static void oaktrail_hdmi_i2c_gpio_fix(void)
|
||||
{
|
||||
void *base;
|
||||
unsigned int gpio_base = 0xff12c000;
|
||||
int gpio_len = 0x1000;
|
||||
u32 temp;
|
||||
|
||||
base = ioremap((resource_size_t)gpio_base, gpio_len);
|
||||
if (base == NULL) {
|
||||
DRM_ERROR("gpio ioremap fail\n");
|
||||
return;
|
||||
}
|
||||
|
||||
temp = readl(base + 0x44);
|
||||
DRM_DEBUG_DRIVER("old gpio val %x\n", temp);
|
||||
writel((temp | 0x00000a00), (base + 0x44));
|
||||
temp = readl(base + 0x44);
|
||||
DRM_DEBUG_DRIVER("new gpio val %x\n", temp);
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
int oaktrail_hdmi_i2c_init(struct pci_dev *dev)
|
||||
{
|
||||
struct oaktrail_hdmi_dev *hdmi_dev;
|
||||
struct hdmi_i2c_dev *i2c_dev;
|
||||
int ret;
|
||||
|
||||
hdmi_dev = pci_get_drvdata(dev);
|
||||
|
||||
i2c_dev = kzalloc(sizeof(struct hdmi_i2c_dev), GFP_KERNEL);
|
||||
if (i2c_dev == NULL) {
|
||||
DRM_ERROR("Can't allocate interface\n");
|
||||
ret = -ENOMEM;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
i2c_dev->adap = &oaktrail_hdmi_i2c_adapter;
|
||||
i2c_dev->status = I2C_STAT_INIT;
|
||||
init_completion(&i2c_dev->complete);
|
||||
mutex_init(&i2c_dev->i2c_lock);
|
||||
i2c_set_adapdata(&oaktrail_hdmi_i2c_adapter, hdmi_dev);
|
||||
hdmi_dev->i2c_dev = i2c_dev;
|
||||
|
||||
/* Enable HDMI I2C function on gpio */
|
||||
oaktrail_hdmi_i2c_gpio_fix();
|
||||
|
||||
/* request irq */
|
||||
ret = request_irq(dev->irq, oaktrail_hdmi_i2c_handler, IRQF_SHARED,
|
||||
oaktrail_hdmi_i2c_adapter.name, hdmi_dev);
|
||||
if (ret) {
|
||||
DRM_ERROR("Failed to request IRQ for I2C controller\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Adapter registration */
|
||||
ret = i2c_add_numbered_adapter(&oaktrail_hdmi_i2c_adapter);
|
||||
return ret;
|
||||
|
||||
err:
|
||||
kfree(i2c_dev);
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void oaktrail_hdmi_i2c_exit(struct pci_dev *dev)
|
||||
{
|
||||
struct oaktrail_hdmi_dev *hdmi_dev;
|
||||
struct hdmi_i2c_dev *i2c_dev;
|
||||
|
||||
hdmi_dev = pci_get_drvdata(dev);
|
||||
if (i2c_del_adapter(&oaktrail_hdmi_i2c_adapter))
|
||||
DRM_DEBUG_DRIVER("Failed to delete hdmi-i2c adapter\n");
|
||||
|
||||
i2c_dev = hdmi_dev->i2c_dev;
|
||||
kfree(i2c_dev);
|
||||
free_irq(dev->irq, hdmi_dev);
|
||||
}
|
406
drivers/gpu/drm/gma500/oaktrail_lvds.c
Normal file
406
drivers/gpu/drm/gma500/oaktrail_lvds.c
Normal file
@ -0,0 +1,406 @@
|
||||
/*
|
||||
* Copyright © 2006-2009 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
* Dave Airlie <airlied@linux.ie>
|
||||
* Jesse Barnes <jesse.barnes@intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <drm/drmP.h>
|
||||
#include <asm/mrst.h>
|
||||
|
||||
#include "intel_bios.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "power.h"
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
/* The max/min PWM frequency in BPCR[31:17] - */
|
||||
/* The smallest number is 1 (not 0) that can fit in the
|
||||
* 15-bit field of the and then*/
|
||||
/* shifts to the left by one bit to get the actual 16-bit
|
||||
* value that the 15-bits correspond to.*/
|
||||
#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
|
||||
#define BRIGHTNESS_MAX_LEVEL 100
|
||||
|
||||
/**
|
||||
* Sets the power state for the panel.
|
||||
*/
|
||||
static void oaktrail_lvds_set_power(struct drm_device *dev,
|
||||
struct psb_intel_output *output, bool on)
|
||||
{
|
||||
u32 pp_status;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
if (on) {
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
|
||||
POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
|
||||
dev_priv->is_lvds_on = true;
|
||||
if (dev_priv->ops->lvds_bl_power)
|
||||
dev_priv->ops->lvds_bl_power(dev, true);
|
||||
} else {
|
||||
if (dev_priv->ops->lvds_bl_power)
|
||||
dev_priv->ops->lvds_bl_power(dev, false);
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
|
||||
~POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while (pp_status & PP_ON);
|
||||
dev_priv->is_lvds_on = false;
|
||||
pm_request_idle(&dev->pdev->dev);
|
||||
}
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
|
||||
if (mode == DRM_MODE_DPMS_ON)
|
||||
oaktrail_lvds_set_power(dev, output, true);
|
||||
else
|
||||
oaktrail_lvds_set_power(dev, output, false);
|
||||
|
||||
/* XXX: We never power down the LVDS pairs. */
|
||||
}
|
||||
|
||||
static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct psb_intel_mode_device *mode_dev =
|
||||
enc_to_psb_intel_output(encoder)->mode_dev;
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 lvds_port;
|
||||
uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
/*
|
||||
* The LVDS pin pair will already have been turned on in the
|
||||
* psb_intel_crtc_mode_set since it has a large impact on the DPLL
|
||||
* settings.
|
||||
*/
|
||||
lvds_port = (REG_READ(LVDS) &
|
||||
(~LVDS_PIPEB_SELECT)) |
|
||||
LVDS_PORT_EN |
|
||||
LVDS_BORDER_EN;
|
||||
|
||||
/* If the firmware says dither on Moorestown, or the BIOS does
|
||||
on Oaktrail then enable dithering */
|
||||
if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
|
||||
lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
|
||||
|
||||
REG_WRITE(LVDS, lvds_port);
|
||||
|
||||
drm_connector_property_get_value(
|
||||
&enc_to_psb_intel_output(encoder)->base,
|
||||
dev->mode_config.scaling_mode_property,
|
||||
&v);
|
||||
|
||||
if (v == DRM_MODE_SCALE_NO_SCALE)
|
||||
REG_WRITE(PFIT_CONTROL, 0);
|
||||
else if (v == DRM_MODE_SCALE_ASPECT) {
|
||||
if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
|
||||
(mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
|
||||
if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
|
||||
(mode->hdisplay * adjusted_mode->crtc_vdisplay))
|
||||
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
|
||||
else if ((adjusted_mode->crtc_hdisplay *
|
||||
mode->vdisplay) > (mode->hdisplay *
|
||||
adjusted_mode->crtc_vdisplay))
|
||||
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
|
||||
PFIT_SCALING_MODE_PILLARBOX);
|
||||
else
|
||||
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
|
||||
PFIT_SCALING_MODE_LETTERBOX);
|
||||
} else
|
||||
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
|
||||
} else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
|
||||
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct psb_intel_mode_device *mode_dev = output->mode_dev;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
|
||||
mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
|
||||
BACKLIGHT_DUTY_CYCLE_MASK);
|
||||
oaktrail_lvds_set_power(dev, output, false);
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 ret;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
ret = ((REG_READ(BLC_PWM_CTL) &
|
||||
BACKLIGHT_MODULATION_FREQ_MASK) >>
|
||||
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
|
||||
|
||||
gma_power_end(dev);
|
||||
} else
|
||||
ret = ((dev_priv->saveBLC_PWM_CTL &
|
||||
BACKLIGHT_MODULATION_FREQ_MASK) >>
|
||||
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void oaktrail_lvds_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct psb_intel_mode_device *mode_dev = output->mode_dev;
|
||||
|
||||
if (mode_dev->backlight_duty_cycle == 0)
|
||||
mode_dev->backlight_duty_cycle =
|
||||
oaktrail_lvds_get_max_backlight(dev);
|
||||
oaktrail_lvds_set_power(dev, output, true);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
|
||||
.dpms = oaktrail_lvds_dpms,
|
||||
.mode_fixup = psb_intel_lvds_mode_fixup,
|
||||
.prepare = oaktrail_lvds_prepare,
|
||||
.mode_set = oaktrail_lvds_mode_set,
|
||||
.commit = oaktrail_lvds_commit,
|
||||
};
|
||||
|
||||
static struct drm_display_mode lvds_configuration_modes[] = {
|
||||
/* hard coded fixed mode for TPO LTPS LPJ040K001A */
|
||||
{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 33264, 800, 836,
|
||||
846, 1056, 0, 480, 489, 491, 525, 0, 0) },
|
||||
/* hard coded fixed mode for LVDS 800x480 */
|
||||
{ DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30994, 800, 801,
|
||||
802, 1024, 0, 480, 481, 482, 525, 0, 0) },
|
||||
/* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
|
||||
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1072,
|
||||
1104, 1184, 0, 600, 603, 604, 608, 0, 0) },
|
||||
/* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
|
||||
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1104,
|
||||
1136, 1184, 0, 600, 603, 604, 608, 0, 0) },
|
||||
/* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */
|
||||
{ DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 48885, 1024, 1124,
|
||||
1204, 1312, 0, 600, 607, 610, 621, 0, 0) },
|
||||
/* hard coded fixed mode for LVDS 1024x768 */
|
||||
{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
|
||||
1184, 1344, 0, 768, 771, 777, 806, 0, 0) },
|
||||
/* hard coded fixed mode for LVDS 1366x768 */
|
||||
{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 77500, 1366, 1430,
|
||||
1558, 1664, 0, 768, 769, 770, 776, 0, 0) },
|
||||
};
|
||||
|
||||
/* Returns the panel fixed mode from configuration. */
|
||||
|
||||
static struct drm_display_mode *
|
||||
oaktrail_lvds_get_configuration_mode(struct drm_device *dev)
|
||||
{
|
||||
struct drm_display_mode *mode = NULL;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
|
||||
|
||||
if (dev_priv->vbt_data.size != 0x00) { /*if non-zero, then use vbt*/
|
||||
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
|
||||
if (!mode)
|
||||
return NULL;
|
||||
|
||||
mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
|
||||
mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
|
||||
mode->hsync_start = mode->hdisplay + \
|
||||
((ti->hsync_offset_hi << 8) | \
|
||||
ti->hsync_offset_lo);
|
||||
mode->hsync_end = mode->hsync_start + \
|
||||
((ti->hsync_pulse_width_hi << 8) | \
|
||||
ti->hsync_pulse_width_lo);
|
||||
mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
|
||||
ti->hblank_lo);
|
||||
mode->vsync_start = \
|
||||
mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
|
||||
ti->vsync_offset_lo);
|
||||
mode->vsync_end = \
|
||||
mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
|
||||
ti->vsync_pulse_width_lo);
|
||||
mode->vtotal = mode->vdisplay + \
|
||||
((ti->vblank_hi << 8) | ti->vblank_lo);
|
||||
mode->clock = ti->pixel_clock * 10;
|
||||
#if 0
|
||||
printk(KERN_INFO "hdisplay is %d\n", mode->hdisplay);
|
||||
printk(KERN_INFO "vdisplay is %d\n", mode->vdisplay);
|
||||
printk(KERN_INFO "HSS is %d\n", mode->hsync_start);
|
||||
printk(KERN_INFO "HSE is %d\n", mode->hsync_end);
|
||||
printk(KERN_INFO "htotal is %d\n", mode->htotal);
|
||||
printk(KERN_INFO "VSS is %d\n", mode->vsync_start);
|
||||
printk(KERN_INFO "VSE is %d\n", mode->vsync_end);
|
||||
printk(KERN_INFO "vtotal is %d\n", mode->vtotal);
|
||||
printk(KERN_INFO "clock is %d\n", mode->clock);
|
||||
#endif
|
||||
} else
|
||||
mode = drm_mode_duplicate(dev, &lvds_configuration_modes[2]);
|
||||
|
||||
drm_mode_set_name(mode);
|
||||
drm_mode_set_crtcinfo(mode, 0);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* oaktrail_lvds_init - setup LVDS connectors on this device
|
||||
* @dev: drm device
|
||||
*
|
||||
* Create the connector, register the LVDS DDC bus, and try to figure out what
|
||||
* modes we can display on the LVDS panel (if present).
|
||||
*/
|
||||
void oaktrail_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output;
|
||||
struct drm_connector *connector;
|
||||
struct drm_encoder *encoder;
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
struct edid *edid;
|
||||
int ret = 0;
|
||||
struct i2c_adapter *i2c_adap;
|
||||
struct drm_display_mode *scan; /* *modes, *bios_mode; */
|
||||
|
||||
psb_intel_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
|
||||
if (!psb_intel_output)
|
||||
return;
|
||||
|
||||
psb_intel_output->mode_dev = mode_dev;
|
||||
connector = &psb_intel_output->base;
|
||||
encoder = &psb_intel_output->enc;
|
||||
dev_priv->is_lvds_on = true;
|
||||
drm_connector_init(dev, &psb_intel_output->base,
|
||||
&psb_intel_lvds_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_LVDS);
|
||||
|
||||
drm_encoder_init(dev, &psb_intel_output->enc, &psb_intel_lvds_enc_funcs,
|
||||
DRM_MODE_ENCODER_LVDS);
|
||||
|
||||
drm_mode_connector_attach_encoder(&psb_intel_output->base,
|
||||
&psb_intel_output->enc);
|
||||
psb_intel_output->type = INTEL_OUTPUT_LVDS;
|
||||
|
||||
drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
|
||||
drm_connector_helper_add(connector,
|
||||
&psb_intel_lvds_connector_helper_funcs);
|
||||
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = false;
|
||||
connector->doublescan_allowed = false;
|
||||
|
||||
drm_connector_attach_property(connector,
|
||||
dev->mode_config.scaling_mode_property,
|
||||
DRM_MODE_SCALE_FULLSCREEN);
|
||||
drm_connector_attach_property(connector,
|
||||
dev_priv->backlight_property,
|
||||
BRIGHTNESS_MAX_LEVEL);
|
||||
|
||||
mode_dev->panel_wants_dither = false;
|
||||
if (dev_priv->vbt_data.size != 0x00)
|
||||
mode_dev->panel_wants_dither = (dev_priv->gct_data.
|
||||
Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
|
||||
|
||||
/*
|
||||
* LVDS discovery:
|
||||
* 1) check for EDID on DDC
|
||||
* 2) check for VBT data
|
||||
* 3) check to see if LVDS is already on
|
||||
* if none of the above, no panel
|
||||
* 4) make sure lid is open
|
||||
* if closed, act like it's not there for now
|
||||
*/
|
||||
|
||||
i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
|
||||
if (i2c_adap == NULL)
|
||||
dev_err(dev->dev, "No ddc adapter available!\n");
|
||||
/*
|
||||
* Attempt to get the fixed panel mode from DDC. Assume that the
|
||||
* preferred mode is the right one.
|
||||
*/
|
||||
if (i2c_adap) {
|
||||
edid = drm_get_edid(connector, i2c_adap);
|
||||
if (edid) {
|
||||
drm_mode_connector_update_edid_property(connector,
|
||||
edid);
|
||||
ret = drm_add_edid_modes(connector, edid);
|
||||
kfree(edid);
|
||||
}
|
||||
|
||||
list_for_each_entry(scan, &connector->probed_modes, head) {
|
||||
if (scan->type & DRM_MODE_TYPE_PREFERRED) {
|
||||
mode_dev->panel_fixed_mode =
|
||||
drm_mode_duplicate(dev, scan);
|
||||
goto out; /* FIXME: check for quirks */
|
||||
}
|
||||
}
|
||||
}
|
||||
/*
|
||||
* If we didn't get EDID, try geting panel timing
|
||||
* from configuration data
|
||||
*/
|
||||
mode_dev->panel_fixed_mode = oaktrail_lvds_get_configuration_mode(dev);
|
||||
|
||||
if (mode_dev->panel_fixed_mode) {
|
||||
mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
|
||||
goto out; /* FIXME: check for quirks */
|
||||
}
|
||||
|
||||
/* If we still don't have a mode after all that, give up. */
|
||||
if (!mode_dev->panel_fixed_mode) {
|
||||
dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
|
||||
goto failed_find;
|
||||
}
|
||||
|
||||
out:
|
||||
drm_sysfs_connector_add(connector);
|
||||
return;
|
||||
|
||||
failed_find:
|
||||
dev_dbg(dev->dev, "No LVDS modes found, disabling.\n");
|
||||
if (psb_intel_output->ddc_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->ddc_bus);
|
||||
|
||||
/* failed_ddc: */
|
||||
|
||||
drm_encoder_cleanup(encoder);
|
||||
drm_connector_cleanup(connector);
|
||||
kfree(connector);
|
||||
}
|
||||
|
316
drivers/gpu/drm/gma500/power.c
Normal file
316
drivers/gpu/drm/gma500/power.c
Normal file
@ -0,0 +1,316 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Benjamin Defnet <benjamin.r.defnet@intel.com>
|
||||
* Rajesh Poornachandran <rajesh.poornachandran@intel.com>
|
||||
* Massively reworked
|
||||
* Alan Cox <alan@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include "power.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
static struct mutex power_mutex; /* Serialize power ops */
|
||||
static spinlock_t power_ctrl_lock; /* Serialize power claim */
|
||||
|
||||
/**
|
||||
* gma_power_init - initialise power manager
|
||||
* @dev: our device
|
||||
*
|
||||
* Set up for power management tracking of our hardware.
|
||||
*/
|
||||
void gma_power_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
/* FIXME: Move APM/OSPM base into relevant device code */
|
||||
dev_priv->apm_base = dev_priv->apm_reg & 0xffff;
|
||||
dev_priv->ospm_base &= 0xffff;
|
||||
|
||||
dev_priv->display_power = true; /* We start active */
|
||||
dev_priv->display_count = 0; /* Currently no users */
|
||||
dev_priv->suspended = false; /* And not suspended */
|
||||
spin_lock_init(&power_ctrl_lock);
|
||||
mutex_init(&power_mutex);
|
||||
|
||||
dev_priv->ops->init_pm(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_power_uninit - end power manager
|
||||
* @dev: device to end for
|
||||
*
|
||||
* Undo the effects of gma_power_init
|
||||
*/
|
||||
void gma_power_uninit(struct drm_device *dev)
|
||||
{
|
||||
pm_runtime_disable(&dev->pdev->dev);
|
||||
pm_runtime_set_suspended(&dev->pdev->dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_suspend_display - suspend the display logic
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Suspend the display logic of the graphics interface
|
||||
*/
|
||||
static void gma_suspend_display(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (dev_priv->suspended)
|
||||
return;
|
||||
dev_priv->ops->save_regs(dev);
|
||||
dev_priv->ops->power_down(dev);
|
||||
dev_priv->display_power = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_resume_display - resume display side logic
|
||||
*
|
||||
* Resume the display hardware restoring state and enabling
|
||||
* as necessary.
|
||||
*/
|
||||
static void gma_resume_display(struct pci_dev *pdev)
|
||||
{
|
||||
struct drm_device *dev = pci_get_drvdata(pdev);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (dev_priv->suspended == false)
|
||||
return;
|
||||
|
||||
/* turn on the display power island */
|
||||
dev_priv->ops->power_up(dev);
|
||||
dev_priv->suspended = false;
|
||||
dev_priv->display_power = true;
|
||||
|
||||
PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
|
||||
pci_write_config_word(pdev, PSB_GMCH_CTRL,
|
||||
dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
|
||||
dev_priv->ops->restore_regs(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_suspend_pci - suspend PCI side
|
||||
* @pdev: PCI device
|
||||
*
|
||||
* Perform the suspend processing on our PCI device state
|
||||
*/
|
||||
static void gma_suspend_pci(struct pci_dev *pdev)
|
||||
{
|
||||
struct drm_device *dev = pci_get_drvdata(pdev);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int bsm, vbt;
|
||||
|
||||
if (dev_priv->suspended)
|
||||
return;
|
||||
|
||||
pci_save_state(pdev);
|
||||
pci_read_config_dword(pdev, 0x5C, &bsm);
|
||||
dev_priv->saveBSM = bsm;
|
||||
pci_read_config_dword(pdev, 0xFC, &vbt);
|
||||
dev_priv->saveVBT = vbt;
|
||||
pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr);
|
||||
pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data);
|
||||
|
||||
pci_disable_device(pdev);
|
||||
pci_set_power_state(pdev, PCI_D3hot);
|
||||
|
||||
dev_priv->suspended = true;
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_resume_pci - resume helper
|
||||
* @dev: our PCI device
|
||||
*
|
||||
* Perform the resume processing on our PCI device state - rewrite
|
||||
* register state and re-enable the PCI device
|
||||
*/
|
||||
static bool gma_resume_pci(struct pci_dev *pdev)
|
||||
{
|
||||
struct drm_device *dev = pci_get_drvdata(pdev);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
if (!dev_priv->suspended)
|
||||
return true;
|
||||
|
||||
pci_set_power_state(pdev, PCI_D0);
|
||||
pci_restore_state(pdev);
|
||||
pci_write_config_dword(pdev, 0x5c, dev_priv->saveBSM);
|
||||
pci_write_config_dword(pdev, 0xFC, dev_priv->saveVBT);
|
||||
/* restoring MSI address and data in PCIx space */
|
||||
pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr);
|
||||
pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data);
|
||||
ret = pci_enable_device(pdev);
|
||||
|
||||
if (ret != 0)
|
||||
dev_err(&pdev->dev, "pci_enable failed: %d\n", ret);
|
||||
else
|
||||
dev_priv->suspended = false;
|
||||
return !dev_priv->suspended;
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_power_suspend - bus callback for suspend
|
||||
* @pdev: our PCI device
|
||||
* @state: suspend type
|
||||
*
|
||||
* Called back by the PCI layer during a suspend of the system. We
|
||||
* perform the necessary shut down steps and save enough state that
|
||||
* we can undo this when resume is called.
|
||||
*/
|
||||
int gma_power_suspend(struct device *_dev)
|
||||
{
|
||||
struct pci_dev *pdev = container_of(_dev, struct pci_dev, dev);
|
||||
struct drm_device *dev = pci_get_drvdata(pdev);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
mutex_lock(&power_mutex);
|
||||
if (!dev_priv->suspended) {
|
||||
if (dev_priv->display_count) {
|
||||
mutex_unlock(&power_mutex);
|
||||
return -EBUSY;
|
||||
}
|
||||
psb_irq_uninstall(dev);
|
||||
gma_suspend_display(dev);
|
||||
gma_suspend_pci(pdev);
|
||||
}
|
||||
mutex_unlock(&power_mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_power_resume - resume power
|
||||
* @pdev: PCI device
|
||||
*
|
||||
* Resume the PCI side of the graphics and then the displays
|
||||
*/
|
||||
int gma_power_resume(struct device *_dev)
|
||||
{
|
||||
struct pci_dev *pdev = container_of(_dev, struct pci_dev, dev);
|
||||
struct drm_device *dev = pci_get_drvdata(pdev);
|
||||
|
||||
mutex_lock(&power_mutex);
|
||||
gma_resume_pci(pdev);
|
||||
gma_resume_display(pdev);
|
||||
psb_irq_preinstall(dev);
|
||||
psb_irq_postinstall(dev);
|
||||
mutex_unlock(&power_mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_power_is_on - returne true if power is on
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Returns true if the display island power is on at this moment
|
||||
*/
|
||||
bool gma_power_is_on(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
return dev_priv->display_power;
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_power_begin - begin requiring power
|
||||
* @dev: our DRM device
|
||||
* @force_on: true to force power on
|
||||
*
|
||||
* Begin an action that requires the display power island is enabled.
|
||||
* We refcount the islands.
|
||||
*/
|
||||
bool gma_power_begin(struct drm_device *dev, bool force_on)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&power_ctrl_lock, flags);
|
||||
/* Power already on ? */
|
||||
if (dev_priv->display_power) {
|
||||
dev_priv->display_count++;
|
||||
pm_runtime_get(&dev->pdev->dev);
|
||||
spin_unlock_irqrestore(&power_ctrl_lock, flags);
|
||||
return true;
|
||||
}
|
||||
if (force_on == false)
|
||||
goto out_false;
|
||||
|
||||
/* Ok power up needed */
|
||||
ret = gma_resume_pci(dev->pdev);
|
||||
if (ret == 0) {
|
||||
psb_irq_preinstall(dev);
|
||||
psb_irq_postinstall(dev);
|
||||
pm_runtime_get(&dev->pdev->dev);
|
||||
dev_priv->display_count++;
|
||||
spin_unlock_irqrestore(&power_ctrl_lock, flags);
|
||||
return true;
|
||||
}
|
||||
out_false:
|
||||
spin_unlock_irqrestore(&power_ctrl_lock, flags);
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* gma_power_end - end use of power
|
||||
* @dev: Our DRM device
|
||||
*
|
||||
* Indicate that one of our gma_power_begin() requested periods when
|
||||
* the diplay island power is needed has completed.
|
||||
*/
|
||||
void gma_power_end(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&power_ctrl_lock, flags);
|
||||
dev_priv->display_count--;
|
||||
WARN_ON(dev_priv->display_count < 0);
|
||||
spin_unlock_irqrestore(&power_ctrl_lock, flags);
|
||||
pm_runtime_put(&dev->pdev->dev);
|
||||
}
|
||||
|
||||
int psb_runtime_suspend(struct device *dev)
|
||||
{
|
||||
return gma_power_suspend(dev);
|
||||
}
|
||||
|
||||
int psb_runtime_resume(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int psb_runtime_idle(struct device *dev)
|
||||
{
|
||||
struct drm_device *drmdev = pci_get_drvdata(to_pci_dev(dev));
|
||||
struct drm_psb_private *dev_priv = drmdev->dev_private;
|
||||
if (dev_priv->display_count)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
67
drivers/gpu/drm/gma500/power.h
Normal file
67
drivers/gpu/drm/gma500/power.h
Normal file
@ -0,0 +1,67 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Benjamin Defnet <benjamin.r.defnet@intel.com>
|
||||
* Rajesh Poornachandran <rajesh.poornachandran@intel.com>
|
||||
* Massively reworked
|
||||
* Alan Cox <alan@linux.intel.com>
|
||||
*/
|
||||
#ifndef _PSB_POWERMGMT_H_
|
||||
#define _PSB_POWERMGMT_H_
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <drm/drmP.h>
|
||||
|
||||
void gma_power_init(struct drm_device *dev);
|
||||
void gma_power_uninit(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* The kernel bus power management will call these functions
|
||||
*/
|
||||
int gma_power_suspend(struct device *dev);
|
||||
int gma_power_resume(struct device *dev);
|
||||
|
||||
/*
|
||||
* These are the functions the driver should use to wrap all hw access
|
||||
* (i.e. register reads and writes)
|
||||
*/
|
||||
bool gma_power_begin(struct drm_device *dev, bool force);
|
||||
void gma_power_end(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* Use this function to do an instantaneous check for if the hw is on.
|
||||
* Only use this in cases where you know the mutex is already held such
|
||||
* as in irq install/uninstall and you need to
|
||||
* prevent a deadlock situation. Otherwise use gma_power_begin().
|
||||
*/
|
||||
bool gma_power_is_on(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* GFX-Runtime PM callbacks
|
||||
*/
|
||||
int psb_runtime_suspend(struct device *dev);
|
||||
int psb_runtime_resume(struct device *dev);
|
||||
int psb_runtime_idle(struct device *dev);
|
||||
|
||||
#endif /*_PSB_POWERMGMT_H_*/
|
353
drivers/gpu/drm/gma500/psb_device.c
Normal file
353
drivers/gpu/drm/gma500/psb_device.c
Normal file
@ -0,0 +1,353 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#include <linux/backlight.h>
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_drm.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "intel_bios.h"
|
||||
|
||||
|
||||
static int psb_output_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
psb_intel_lvds_init(dev, &dev_priv->mode_dev);
|
||||
psb_intel_sdvo_init(dev, SDVOB);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
|
||||
/*
|
||||
* Poulsbo Backlight Interfaces
|
||||
*/
|
||||
|
||||
#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
|
||||
#define BLC_PWM_FREQ_CALC_CONSTANT 32
|
||||
#define MHz 1000000
|
||||
|
||||
#define PSB_BLC_PWM_PRECISION_FACTOR 10
|
||||
#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
|
||||
#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
|
||||
|
||||
#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
|
||||
#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
|
||||
|
||||
static int psb_brightness;
|
||||
static struct backlight_device *psb_backlight_device;
|
||||
|
||||
static int psb_get_brightness(struct backlight_device *bd)
|
||||
{
|
||||
/* return locally cached var instead of HW read (due to DPST etc.) */
|
||||
/* FIXME: ideally return actual value in case firmware fiddled with
|
||||
it */
|
||||
return psb_brightness;
|
||||
}
|
||||
|
||||
|
||||
static int psb_backlight_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long core_clock;
|
||||
/* u32 bl_max_freq; */
|
||||
/* unsigned long value; */
|
||||
u16 bl_max_freq;
|
||||
uint32_t value;
|
||||
uint32_t blc_pwm_precision_factor;
|
||||
|
||||
/* get bl_max_freq and pol from dev_priv*/
|
||||
if (!dev_priv->lvds_bl) {
|
||||
dev_err(dev->dev, "Has no valid LVDS backlight info\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
bl_max_freq = dev_priv->lvds_bl->freq;
|
||||
blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
|
||||
|
||||
core_clock = dev_priv->core_freq;
|
||||
|
||||
value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
|
||||
value *= blc_pwm_precision_factor;
|
||||
value /= bl_max_freq;
|
||||
value /= blc_pwm_precision_factor;
|
||||
|
||||
if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
|
||||
value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
|
||||
return -ERANGE;
|
||||
else {
|
||||
value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
|
||||
REG_WRITE(BLC_PWM_CTL,
|
||||
(value << PSB_BACKLIGHT_PWM_CTL_SHIFT) | (value));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int psb_set_brightness(struct backlight_device *bd)
|
||||
{
|
||||
struct drm_device *dev = bl_get_data(psb_backlight_device);
|
||||
int level = bd->props.brightness;
|
||||
|
||||
/* Percentage 1-100% being valid */
|
||||
if (level < 1)
|
||||
level = 1;
|
||||
|
||||
psb_intel_lvds_set_brightness(dev, level);
|
||||
psb_brightness = level;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct backlight_ops psb_ops = {
|
||||
.get_brightness = psb_get_brightness,
|
||||
.update_status = psb_set_brightness,
|
||||
};
|
||||
|
||||
static int psb_backlight_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int ret;
|
||||
struct backlight_properties props;
|
||||
|
||||
memset(&props, 0, sizeof(struct backlight_properties));
|
||||
props.max_brightness = 100;
|
||||
props.type = BACKLIGHT_PLATFORM;
|
||||
|
||||
psb_backlight_device = backlight_device_register("psb-bl",
|
||||
NULL, (void *)dev, &psb_ops, &props);
|
||||
if (IS_ERR(psb_backlight_device))
|
||||
return PTR_ERR(psb_backlight_device);
|
||||
|
||||
ret = psb_backlight_setup(dev);
|
||||
if (ret < 0) {
|
||||
backlight_device_unregister(psb_backlight_device);
|
||||
psb_backlight_device = NULL;
|
||||
return ret;
|
||||
}
|
||||
psb_backlight_device->props.brightness = 100;
|
||||
psb_backlight_device->props.max_brightness = 100;
|
||||
backlight_update_status(psb_backlight_device);
|
||||
dev_priv->backlight_device = psb_backlight_device;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Provide the Poulsbo specific chip logic and low level methods
|
||||
* for power management
|
||||
*/
|
||||
|
||||
static void psb_init_pm(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
|
||||
gating &= ~3; /* Disable 2D clock gating */
|
||||
gating |= 1;
|
||||
PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
|
||||
PSB_RSGX32(PSB_CR_CLKGATECTL);
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_save_display_registers - save registers lost on suspend
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Save the state we need in order to be able to restore the interface
|
||||
* upon resume from suspend
|
||||
*/
|
||||
static int psb_save_display_registers(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_connector *connector;
|
||||
|
||||
/* Display arbitration control + watermarks */
|
||||
dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
|
||||
dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1);
|
||||
dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2);
|
||||
dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3);
|
||||
dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4);
|
||||
dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5);
|
||||
dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
|
||||
dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
|
||||
|
||||
/* Save crtc and output state */
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
||||
if (drm_helper_crtc_in_use(crtc))
|
||||
crtc->funcs->save(crtc);
|
||||
}
|
||||
|
||||
list_for_each_entry(connector, &dev->mode_config.connector_list, head)
|
||||
connector->funcs->save(connector);
|
||||
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_restore_display_registers - restore lost register state
|
||||
* @dev: our DRM device
|
||||
*
|
||||
* Restore register state that was lost during suspend and resume.
|
||||
*/
|
||||
static int psb_restore_display_registers(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_connector *connector;
|
||||
int pp_stat;
|
||||
|
||||
/* Display arbitration + watermarks */
|
||||
PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5);
|
||||
PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
|
||||
PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);
|
||||
|
||||
/*make sure VGA plane is off. it initializes to on after reset!*/
|
||||
PSB_WVDC32(0x80000000, VGACNTRL);
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
|
||||
if (drm_helper_crtc_in_use(crtc))
|
||||
crtc->funcs->restore(crtc);
|
||||
|
||||
list_for_each_entry(connector, &dev->mode_config.connector_list, head)
|
||||
connector->funcs->restore(connector);
|
||||
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
||||
if (dev_priv->iLVDS_enable) {
|
||||
/*shutdown the panel*/
|
||||
PSB_WVDC32(0, PP_CONTROL);
|
||||
do {
|
||||
pp_stat = PSB_RVDC32(PP_STATUS);
|
||||
} while (pp_stat & 0x80000000);
|
||||
|
||||
/* Turn off the plane */
|
||||
PSB_WVDC32(0x58000000, DSPACNTR);
|
||||
PSB_WVDC32(0, DSPASURF);/*trigger the plane disable*/
|
||||
/* Wait ~4 ticks */
|
||||
msleep(4);
|
||||
/* Turn off pipe */
|
||||
PSB_WVDC32(0x0, PIPEACONF);
|
||||
/* Wait ~8 ticks */
|
||||
msleep(8);
|
||||
|
||||
/* Turn off PLLs */
|
||||
PSB_WVDC32(0, MRST_DPLL_A);
|
||||
} else {
|
||||
PSB_WVDC32(DPI_SHUT_DOWN, DPI_CONTROL_REG);
|
||||
PSB_WVDC32(0x0, PIPEACONF);
|
||||
PSB_WVDC32(0x2faf0000, BLC_PWM_CTL);
|
||||
while (REG_READ(0x70008) & 0x40000000)
|
||||
cpu_relax();
|
||||
while ((PSB_RVDC32(GEN_FIFO_STAT_REG) & DPI_FIFO_EMPTY)
|
||||
!= DPI_FIFO_EMPTY)
|
||||
cpu_relax();
|
||||
PSB_WVDC32(0, DEVICE_READY_REG);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int psb_power_down(struct drm_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int psb_power_up(struct drm_device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void psb_get_core_freq(struct drm_device *dev)
|
||||
{
|
||||
uint32_t clock;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
|
||||
/*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
|
||||
/*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
|
||||
|
||||
pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
|
||||
pci_read_config_dword(pci_root, 0xD4, &clock);
|
||||
pci_dev_put(pci_root);
|
||||
|
||||
switch (clock & 0x07) {
|
||||
case 0:
|
||||
dev_priv->core_freq = 100;
|
||||
break;
|
||||
case 1:
|
||||
dev_priv->core_freq = 133;
|
||||
break;
|
||||
case 2:
|
||||
dev_priv->core_freq = 150;
|
||||
break;
|
||||
case 3:
|
||||
dev_priv->core_freq = 178;
|
||||
break;
|
||||
case 4:
|
||||
dev_priv->core_freq = 200;
|
||||
break;
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
dev_priv->core_freq = 266;
|
||||
default:
|
||||
dev_priv->core_freq = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int psb_chip_setup(struct drm_device *dev)
|
||||
{
|
||||
psb_get_core_freq(dev);
|
||||
gma_intel_opregion_init(dev);
|
||||
psb_intel_init_bios(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct psb_ops psb_chip_ops = {
|
||||
.name = "Poulsbo",
|
||||
.accel_2d = 1,
|
||||
.pipes = 2,
|
||||
.crtcs = 2,
|
||||
.sgx_offset = PSB_SGX_OFFSET,
|
||||
.chip_setup = psb_chip_setup,
|
||||
|
||||
.crtc_helper = &psb_intel_helper_funcs,
|
||||
.crtc_funcs = &psb_intel_crtc_funcs,
|
||||
|
||||
.output_init = psb_output_init,
|
||||
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
.backlight_init = psb_backlight_init,
|
||||
#endif
|
||||
|
||||
.init_pm = psb_init_pm,
|
||||
.save_regs = psb_save_display_registers,
|
||||
.restore_regs = psb_restore_display_registers,
|
||||
.power_down = psb_power_down,
|
||||
.power_up = psb_power_up,
|
||||
};
|
||||
|
207
drivers/gpu/drm/gma500/psb_drm.h
Normal file
207
drivers/gpu/drm/gma500/psb_drm.h
Normal file
@ -0,0 +1,207 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
* Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef _PSB_DRM_H_
|
||||
#define _PSB_DRM_H_
|
||||
|
||||
#define PSB_NUM_PIPE 3
|
||||
|
||||
#define PSB_GPU_ACCESS_READ (1ULL << 32)
|
||||
#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
|
||||
#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
|
||||
|
||||
#define PSB_BO_FLAG_COMMAND (1ULL << 52)
|
||||
|
||||
/*
|
||||
* Feedback components:
|
||||
*/
|
||||
|
||||
struct drm_psb_sizes_arg {
|
||||
u32 ta_mem_size;
|
||||
u32 mmu_size;
|
||||
u32 pds_size;
|
||||
u32 rastgeom_size;
|
||||
u32 tt_size;
|
||||
u32 vram_size;
|
||||
};
|
||||
|
||||
struct drm_psb_dpst_lut_arg {
|
||||
uint8_t lut[256];
|
||||
int output_id;
|
||||
};
|
||||
|
||||
#define PSB_DC_CRTC_SAVE 0x01
|
||||
#define PSB_DC_CRTC_RESTORE 0x02
|
||||
#define PSB_DC_OUTPUT_SAVE 0x04
|
||||
#define PSB_DC_OUTPUT_RESTORE 0x08
|
||||
#define PSB_DC_CRTC_MASK 0x03
|
||||
#define PSB_DC_OUTPUT_MASK 0x0C
|
||||
|
||||
struct drm_psb_dc_state_arg {
|
||||
u32 flags;
|
||||
u32 obj_id;
|
||||
};
|
||||
|
||||
struct drm_psb_mode_operation_arg {
|
||||
u32 obj_id;
|
||||
u16 operation;
|
||||
struct drm_mode_modeinfo mode;
|
||||
void *data;
|
||||
};
|
||||
|
||||
struct drm_psb_stolen_memory_arg {
|
||||
u32 base;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
/*Display Register Bits*/
|
||||
#define REGRWBITS_PFIT_CONTROLS (1 << 0)
|
||||
#define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
|
||||
#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
|
||||
#define REGRWBITS_PIPEASRC (1 << 3)
|
||||
#define REGRWBITS_PIPEBSRC (1 << 4)
|
||||
#define REGRWBITS_VTOTAL_A (1 << 5)
|
||||
#define REGRWBITS_VTOTAL_B (1 << 6)
|
||||
#define REGRWBITS_DSPACNTR (1 << 8)
|
||||
#define REGRWBITS_DSPBCNTR (1 << 9)
|
||||
#define REGRWBITS_DSPCCNTR (1 << 10)
|
||||
|
||||
/*Overlay Register Bits*/
|
||||
#define OV_REGRWBITS_OVADD (1 << 0)
|
||||
#define OV_REGRWBITS_OGAM_ALL (1 << 1)
|
||||
|
||||
#define OVC_REGRWBITS_OVADD (1 << 2)
|
||||
#define OVC_REGRWBITS_OGAM_ALL (1 << 3)
|
||||
|
||||
struct drm_psb_register_rw_arg {
|
||||
u32 b_force_hw_on;
|
||||
|
||||
u32 display_read_mask;
|
||||
u32 display_write_mask;
|
||||
|
||||
struct {
|
||||
u32 pfit_controls;
|
||||
u32 pfit_autoscale_ratios;
|
||||
u32 pfit_programmed_scale_ratios;
|
||||
u32 pipeasrc;
|
||||
u32 pipebsrc;
|
||||
u32 vtotal_a;
|
||||
u32 vtotal_b;
|
||||
} display;
|
||||
|
||||
u32 overlay_read_mask;
|
||||
u32 overlay_write_mask;
|
||||
|
||||
struct {
|
||||
u32 OVADD;
|
||||
u32 OGAMC0;
|
||||
u32 OGAMC1;
|
||||
u32 OGAMC2;
|
||||
u32 OGAMC3;
|
||||
u32 OGAMC4;
|
||||
u32 OGAMC5;
|
||||
u32 IEP_ENABLED;
|
||||
u32 IEP_BLE_MINMAX;
|
||||
u32 IEP_BSSCC_CONTROL;
|
||||
u32 b_wait_vblank;
|
||||
} overlay;
|
||||
|
||||
u32 sprite_enable_mask;
|
||||
u32 sprite_disable_mask;
|
||||
|
||||
struct {
|
||||
u32 dspa_control;
|
||||
u32 dspa_key_value;
|
||||
u32 dspa_key_mask;
|
||||
u32 dspc_control;
|
||||
u32 dspc_stride;
|
||||
u32 dspc_position;
|
||||
u32 dspc_linear_offset;
|
||||
u32 dspc_size;
|
||||
u32 dspc_surface;
|
||||
} sprite;
|
||||
|
||||
u32 subpicture_enable_mask;
|
||||
u32 subpicture_disable_mask;
|
||||
};
|
||||
|
||||
/* Controlling the kernel modesetting buffers */
|
||||
|
||||
#define DRM_PSB_SIZES 0x07
|
||||
#define DRM_PSB_FUSE_REG 0x08
|
||||
#define DRM_PSB_DC_STATE 0x0A
|
||||
#define DRM_PSB_ADB 0x0B
|
||||
#define DRM_PSB_MODE_OPERATION 0x0C
|
||||
#define DRM_PSB_STOLEN_MEMORY 0x0D
|
||||
#define DRM_PSB_REGISTER_RW 0x0E
|
||||
|
||||
/*
|
||||
* NOTE: Add new commands here, but increment
|
||||
* the values below and increment their
|
||||
* corresponding defines where they're
|
||||
* defined elsewhere.
|
||||
*/
|
||||
|
||||
#define DRM_PSB_GEM_CREATE 0x10
|
||||
#define DRM_PSB_2D_OP 0x11 /* Will be merged later */
|
||||
#define DRM_PSB_GEM_MMAP 0x12
|
||||
#define DRM_PSB_DPST 0x1B
|
||||
#define DRM_PSB_GAMMA 0x1C
|
||||
#define DRM_PSB_DPST_BL 0x1D
|
||||
#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
|
||||
|
||||
#define PSB_MODE_OPERATION_MODE_VALID 0x01
|
||||
#define PSB_MODE_OPERATION_SET_DC_BASE 0x02
|
||||
|
||||
struct drm_psb_get_pipe_from_crtc_id_arg {
|
||||
/** ID of CRTC being requested **/
|
||||
u32 crtc_id;
|
||||
|
||||
/** pipe of requested CRTC **/
|
||||
u32 pipe;
|
||||
};
|
||||
|
||||
/* FIXME: move this into a medfield header once we are sure it isn't needed for an
|
||||
ioctl */
|
||||
struct psb_drm_dpu_rect {
|
||||
int x, y;
|
||||
int width, height;
|
||||
};
|
||||
|
||||
struct drm_psb_gem_create {
|
||||
__u64 size;
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
#define PSB_GEM_CREATE_STOLEN 1 /* Stolen memory can be used */
|
||||
};
|
||||
|
||||
struct drm_psb_gem_mmap {
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
/**
|
||||
* Fake offset to use for subsequent mmap call
|
||||
*
|
||||
* This is a fixed-size type for 32/64 compatibility.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
#endif
|
1211
drivers/gpu/drm/gma500/psb_drv.c
Normal file
1211
drivers/gpu/drm/gma500/psb_drv.c
Normal file
File diff suppressed because it is too large
Load Diff
924
drivers/gpu/drm/gma500/psb_drv.h
Normal file
924
drivers/gpu/drm/gma500/psb_drv.h
Normal file
@ -0,0 +1,924 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef _PSB_DRV_H_
|
||||
#define _PSB_DRV_H_
|
||||
|
||||
#include <linux/kref.h>
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include "drm_global.h"
|
||||
#include "gem_glue.h"
|
||||
#include "psb_drm.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "gtt.h"
|
||||
#include "power.h"
|
||||
#include "oaktrail.h"
|
||||
|
||||
/* Append new drm mode definition here, align with libdrm definition */
|
||||
#define DRM_MODE_SCALE_NO_SCALE 2
|
||||
|
||||
enum {
|
||||
CHIP_PSB_8108 = 0, /* Poulsbo */
|
||||
CHIP_PSB_8109 = 1, /* Poulsbo */
|
||||
CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
|
||||
CHIP_MFLD_0130 = 3, /* Medfield */
|
||||
};
|
||||
|
||||
#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
|
||||
#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
|
||||
|
||||
/*
|
||||
* Driver definitions
|
||||
*/
|
||||
|
||||
#define DRIVER_NAME "gma500"
|
||||
#define DRIVER_DESC "DRM driver for the Intel GMA500"
|
||||
|
||||
#define PSB_DRM_DRIVER_DATE "2011-06-06"
|
||||
#define PSB_DRM_DRIVER_MAJOR 1
|
||||
#define PSB_DRM_DRIVER_MINOR 0
|
||||
#define PSB_DRM_DRIVER_PATCHLEVEL 0
|
||||
|
||||
/*
|
||||
* Hardware offsets
|
||||
*/
|
||||
#define PSB_VDC_OFFSET 0x00000000
|
||||
#define PSB_VDC_SIZE 0x000080000
|
||||
#define MRST_MMIO_SIZE 0x0000C0000
|
||||
#define MDFLD_MMIO_SIZE 0x000100000
|
||||
#define PSB_SGX_SIZE 0x8000
|
||||
#define PSB_SGX_OFFSET 0x00040000
|
||||
#define MRST_SGX_OFFSET 0x00080000
|
||||
/*
|
||||
* PCI resource identifiers
|
||||
*/
|
||||
#define PSB_MMIO_RESOURCE 0
|
||||
#define PSB_GATT_RESOURCE 2
|
||||
#define PSB_GTT_RESOURCE 3
|
||||
/*
|
||||
* PCI configuration
|
||||
*/
|
||||
#define PSB_GMCH_CTRL 0x52
|
||||
#define PSB_BSM 0x5C
|
||||
#define _PSB_GMCH_ENABLED 0x4
|
||||
#define PSB_PGETBL_CTL 0x2020
|
||||
#define _PSB_PGETBL_ENABLED 0x00000001
|
||||
#define PSB_SGX_2D_SLAVE_PORT 0x4000
|
||||
|
||||
/* To get rid of */
|
||||
#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
|
||||
#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
|
||||
|
||||
/*
|
||||
* SGX side MMU definitions (these can probably go)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Flags for external memory type field.
|
||||
*/
|
||||
#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
|
||||
#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
|
||||
#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
|
||||
/*
|
||||
* PTE's and PDE's
|
||||
*/
|
||||
#define PSB_PDE_MASK 0x003FFFFF
|
||||
#define PSB_PDE_SHIFT 22
|
||||
#define PSB_PTE_SHIFT 12
|
||||
/*
|
||||
* Cache control
|
||||
*/
|
||||
#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
|
||||
#define PSB_PTE_WO 0x0002 /* Write only */
|
||||
#define PSB_PTE_RO 0x0004 /* Read only */
|
||||
#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
|
||||
|
||||
/*
|
||||
* VDC registers and bits
|
||||
*/
|
||||
#define PSB_MSVDX_CLOCKGATING 0x2064
|
||||
#define PSB_TOPAZ_CLOCKGATING 0x2068
|
||||
#define PSB_HWSTAM 0x2098
|
||||
#define PSB_INSTPM 0x20C0
|
||||
#define PSB_INT_IDENTITY_R 0x20A4
|
||||
#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
|
||||
#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
|
||||
#define _PSB_DPST_PIPEB_FLAG (1<<4)
|
||||
#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
|
||||
#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
|
||||
#define _PSB_DPST_PIPEA_FLAG (1<<6)
|
||||
#define _PSB_PIPEA_EVENT_FLAG (1<<6)
|
||||
#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
|
||||
#define _MDFLD_MIPIA_FLAG (1<<16)
|
||||
#define _MDFLD_MIPIC_FLAG (1<<17)
|
||||
#define _PSB_IRQ_SGX_FLAG (1<<18)
|
||||
#define _PSB_IRQ_MSVDX_FLAG (1<<19)
|
||||
#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
|
||||
|
||||
/* This flag includes all the display IRQ bits excepts the vblank irqs. */
|
||||
#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
|
||||
_MDFLD_PIPEB_EVENT_FLAG | \
|
||||
_PSB_PIPEA_EVENT_FLAG | \
|
||||
_PSB_VSYNC_PIPEA_FLAG | \
|
||||
_MDFLD_MIPIA_FLAG | \
|
||||
_MDFLD_MIPIC_FLAG)
|
||||
#define PSB_INT_IDENTITY_R 0x20A4
|
||||
#define PSB_INT_MASK_R 0x20A8
|
||||
#define PSB_INT_ENABLE_R 0x20A0
|
||||
|
||||
#define _PSB_MMU_ER_MASK 0x0001FF00
|
||||
#define _PSB_MMU_ER_HOST (1 << 16)
|
||||
#define GPIOA 0x5010
|
||||
#define GPIOB 0x5014
|
||||
#define GPIOC 0x5018
|
||||
#define GPIOD 0x501c
|
||||
#define GPIOE 0x5020
|
||||
#define GPIOF 0x5024
|
||||
#define GPIOG 0x5028
|
||||
#define GPIOH 0x502c
|
||||
#define GPIO_CLOCK_DIR_MASK (1 << 0)
|
||||
#define GPIO_CLOCK_DIR_IN (0 << 1)
|
||||
#define GPIO_CLOCK_DIR_OUT (1 << 1)
|
||||
#define GPIO_CLOCK_VAL_MASK (1 << 2)
|
||||
#define GPIO_CLOCK_VAL_OUT (1 << 3)
|
||||
#define GPIO_CLOCK_VAL_IN (1 << 4)
|
||||
#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
|
||||
#define GPIO_DATA_DIR_MASK (1 << 8)
|
||||
#define GPIO_DATA_DIR_IN (0 << 9)
|
||||
#define GPIO_DATA_DIR_OUT (1 << 9)
|
||||
#define GPIO_DATA_VAL_MASK (1 << 10)
|
||||
#define GPIO_DATA_VAL_OUT (1 << 11)
|
||||
#define GPIO_DATA_VAL_IN (1 << 12)
|
||||
#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
|
||||
|
||||
#define VCLK_DIVISOR_VGA0 0x6000
|
||||
#define VCLK_DIVISOR_VGA1 0x6004
|
||||
#define VCLK_POST_DIV 0x6010
|
||||
|
||||
#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
|
||||
#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
|
||||
#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
|
||||
#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
|
||||
#define PSB_COMM_USER_IRQ (1024 >> 2)
|
||||
#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
|
||||
#define PSB_COMM_FW (2048 >> 2)
|
||||
|
||||
#define PSB_UIRQ_VISTEST 1
|
||||
#define PSB_UIRQ_OOM_REPLY 2
|
||||
#define PSB_UIRQ_FIRE_TA_REPLY 3
|
||||
#define PSB_UIRQ_FIRE_RASTER_REPLY 4
|
||||
|
||||
#define PSB_2D_SIZE (256*1024*1024)
|
||||
#define PSB_MAX_RELOC_PAGES 1024
|
||||
|
||||
#define PSB_LOW_REG_OFFS 0x0204
|
||||
#define PSB_HIGH_REG_OFFS 0x0600
|
||||
|
||||
#define PSB_NUM_VBLANKS 2
|
||||
|
||||
|
||||
#define PSB_2D_SIZE (256*1024*1024)
|
||||
#define PSB_MAX_RELOC_PAGES 1024
|
||||
|
||||
#define PSB_LOW_REG_OFFS 0x0204
|
||||
#define PSB_HIGH_REG_OFFS 0x0600
|
||||
|
||||
#define PSB_NUM_VBLANKS 2
|
||||
#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
|
||||
#define PSB_LID_DELAY (DRM_HZ / 10)
|
||||
|
||||
#define MDFLD_PNW_B0 0x04
|
||||
#define MDFLD_PNW_C0 0x08
|
||||
|
||||
#define MDFLD_DSR_2D_3D_0 (1 << 0)
|
||||
#define MDFLD_DSR_2D_3D_2 (1 << 1)
|
||||
#define MDFLD_DSR_CURSOR_0 (1 << 2)
|
||||
#define MDFLD_DSR_CURSOR_2 (1 << 3)
|
||||
#define MDFLD_DSR_OVERLAY_0 (1 << 4)
|
||||
#define MDFLD_DSR_OVERLAY_2 (1 << 5)
|
||||
#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
|
||||
#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
|
||||
#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
|
||||
#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
|
||||
|
||||
#define MDFLD_DSR_RR 45
|
||||
#define MDFLD_DPU_ENABLE (1 << 31)
|
||||
#define MDFLD_DSR_FULLSCREEN (1 << 30)
|
||||
#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
|
||||
|
||||
#define PSB_PWR_STATE_ON 1
|
||||
#define PSB_PWR_STATE_OFF 2
|
||||
|
||||
#define PSB_PMPOLICY_NOPM 0
|
||||
#define PSB_PMPOLICY_CLOCKGATING 1
|
||||
#define PSB_PMPOLICY_POWERDOWN 2
|
||||
|
||||
#define PSB_PMSTATE_POWERUP 0
|
||||
#define PSB_PMSTATE_CLOCKGATED 1
|
||||
#define PSB_PMSTATE_POWERDOWN 2
|
||||
#define PSB_PCIx_MSI_ADDR_LOC 0x94
|
||||
#define PSB_PCIx_MSI_DATA_LOC 0x98
|
||||
|
||||
/* Medfield crystal settings */
|
||||
#define KSEL_CRYSTAL_19 1
|
||||
#define KSEL_BYPASS_19 5
|
||||
#define KSEL_BYPASS_25 6
|
||||
#define KSEL_BYPASS_83_100 7
|
||||
|
||||
struct opregion_header;
|
||||
struct opregion_acpi;
|
||||
struct opregion_swsci;
|
||||
struct opregion_asle;
|
||||
|
||||
struct psb_intel_opregion {
|
||||
struct opregion_header *header;
|
||||
struct opregion_acpi *acpi;
|
||||
struct opregion_swsci *swsci;
|
||||
struct opregion_asle *asle;
|
||||
int enabled;
|
||||
};
|
||||
|
||||
struct psb_ops;
|
||||
|
||||
struct drm_psb_private {
|
||||
struct drm_device *dev;
|
||||
const struct psb_ops *ops;
|
||||
|
||||
struct psb_gtt gtt;
|
||||
|
||||
/* GTT Memory manager */
|
||||
struct psb_gtt_mm *gtt_mm;
|
||||
struct page *scratch_page;
|
||||
u32 *gtt_map;
|
||||
uint32_t stolen_base;
|
||||
void *vram_addr;
|
||||
unsigned long vram_stolen_size;
|
||||
int gtt_initialized;
|
||||
u16 gmch_ctrl; /* Saved GTT setup */
|
||||
u32 pge_ctl;
|
||||
|
||||
struct mutex gtt_mutex;
|
||||
struct resource *gtt_mem; /* Our PCI resource */
|
||||
|
||||
struct psb_mmu_driver *mmu;
|
||||
struct psb_mmu_pd *pf_pd;
|
||||
|
||||
/*
|
||||
* Register base
|
||||
*/
|
||||
|
||||
uint8_t *sgx_reg;
|
||||
uint8_t *vdc_reg;
|
||||
uint32_t gatt_free_offset;
|
||||
|
||||
/*
|
||||
* Fencing / irq.
|
||||
*/
|
||||
|
||||
uint32_t vdc_irq_mask;
|
||||
uint32_t pipestat[PSB_NUM_PIPE];
|
||||
|
||||
spinlock_t irqmask_lock;
|
||||
|
||||
/*
|
||||
* Power
|
||||
*/
|
||||
|
||||
bool suspended;
|
||||
bool display_power;
|
||||
int display_count;
|
||||
|
||||
/*
|
||||
* Modesetting
|
||||
*/
|
||||
struct psb_intel_mode_device mode_dev;
|
||||
|
||||
struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
|
||||
struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
|
||||
uint32_t num_pipe;
|
||||
|
||||
/*
|
||||
* OSPM info (Power management base) (can go ?)
|
||||
*/
|
||||
uint32_t ospm_base;
|
||||
|
||||
/*
|
||||
* Sizes info
|
||||
*/
|
||||
|
||||
struct drm_psb_sizes_arg sizes;
|
||||
|
||||
u32 fuse_reg_value;
|
||||
u32 video_device_fuse;
|
||||
|
||||
/* PCI revision ID for B0:D2:F0 */
|
||||
uint8_t platform_rev_id;
|
||||
|
||||
/*
|
||||
* LVDS info
|
||||
*/
|
||||
int backlight_duty_cycle; /* restore backlight to this value */
|
||||
bool panel_wants_dither;
|
||||
struct drm_display_mode *panel_fixed_mode;
|
||||
struct drm_display_mode *lfp_lvds_vbt_mode;
|
||||
struct drm_display_mode *sdvo_lvds_vbt_mode;
|
||||
|
||||
struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
|
||||
struct psb_intel_i2c_chan *lvds_i2c_bus;
|
||||
|
||||
/* Feature bits from the VBIOS */
|
||||
unsigned int int_tv_support:1;
|
||||
unsigned int lvds_dither:1;
|
||||
unsigned int lvds_vbt:1;
|
||||
unsigned int int_crt_support:1;
|
||||
unsigned int lvds_use_ssc:1;
|
||||
int lvds_ssc_freq;
|
||||
bool is_lvds_on;
|
||||
bool is_mipi_on;
|
||||
u32 mipi_ctrl_display;
|
||||
|
||||
unsigned int core_freq;
|
||||
uint32_t iLVDS_enable;
|
||||
|
||||
/* Runtime PM state */
|
||||
int rpm_enabled;
|
||||
|
||||
/* MID specific */
|
||||
struct oaktrail_vbt vbt_data;
|
||||
struct oaktrail_gct_data gct_data;
|
||||
|
||||
/* MIPI Panel type etc */
|
||||
int panel_id;
|
||||
bool dual_mipi; /* dual display - DPI & DBI */
|
||||
bool dpi_panel_on; /* The DPI panel power is on */
|
||||
bool dpi_panel_on2; /* The DPI panel power is on */
|
||||
bool dbi_panel_on; /* The DBI panel power is on */
|
||||
bool dbi_panel_on2; /* The DBI panel power is on */
|
||||
u32 dsr_fb_update; /* DSR FB update counter */
|
||||
|
||||
/* Moorestown HDMI state */
|
||||
struct oaktrail_hdmi_dev *hdmi_priv;
|
||||
|
||||
/* Moorestown pipe config register value cache */
|
||||
uint32_t pipeconf;
|
||||
uint32_t pipeconf1;
|
||||
uint32_t pipeconf2;
|
||||
|
||||
/* Moorestown plane control register value cache */
|
||||
uint32_t dspcntr;
|
||||
uint32_t dspcntr1;
|
||||
uint32_t dspcntr2;
|
||||
|
||||
/* Moorestown MM backlight cache */
|
||||
uint8_t saveBKLTCNT;
|
||||
uint8_t saveBKLTREQ;
|
||||
uint8_t saveBKLTBRTL;
|
||||
|
||||
/*
|
||||
* Register state
|
||||
*/
|
||||
uint32_t saveDSPACNTR;
|
||||
uint32_t saveDSPBCNTR;
|
||||
uint32_t savePIPEACONF;
|
||||
uint32_t savePIPEBCONF;
|
||||
uint32_t savePIPEASRC;
|
||||
uint32_t savePIPEBSRC;
|
||||
uint32_t saveFPA0;
|
||||
uint32_t saveFPA1;
|
||||
uint32_t saveDPLL_A;
|
||||
uint32_t saveDPLL_A_MD;
|
||||
uint32_t saveHTOTAL_A;
|
||||
uint32_t saveHBLANK_A;
|
||||
uint32_t saveHSYNC_A;
|
||||
uint32_t saveVTOTAL_A;
|
||||
uint32_t saveVBLANK_A;
|
||||
uint32_t saveVSYNC_A;
|
||||
uint32_t saveDSPASTRIDE;
|
||||
uint32_t saveDSPASIZE;
|
||||
uint32_t saveDSPAPOS;
|
||||
uint32_t saveDSPABASE;
|
||||
uint32_t saveDSPASURF;
|
||||
uint32_t saveDSPASTATUS;
|
||||
uint32_t saveFPB0;
|
||||
uint32_t saveFPB1;
|
||||
uint32_t saveDPLL_B;
|
||||
uint32_t saveDPLL_B_MD;
|
||||
uint32_t saveHTOTAL_B;
|
||||
uint32_t saveHBLANK_B;
|
||||
uint32_t saveHSYNC_B;
|
||||
uint32_t saveVTOTAL_B;
|
||||
uint32_t saveVBLANK_B;
|
||||
uint32_t saveVSYNC_B;
|
||||
uint32_t saveDSPBSTRIDE;
|
||||
uint32_t saveDSPBSIZE;
|
||||
uint32_t saveDSPBPOS;
|
||||
uint32_t saveDSPBBASE;
|
||||
uint32_t saveDSPBSURF;
|
||||
uint32_t saveDSPBSTATUS;
|
||||
uint32_t saveVCLK_DIVISOR_VGA0;
|
||||
uint32_t saveVCLK_DIVISOR_VGA1;
|
||||
uint32_t saveVCLK_POST_DIV;
|
||||
uint32_t saveVGACNTRL;
|
||||
uint32_t saveADPA;
|
||||
uint32_t saveLVDS;
|
||||
uint32_t saveDVOA;
|
||||
uint32_t saveDVOB;
|
||||
uint32_t saveDVOC;
|
||||
uint32_t savePP_ON;
|
||||
uint32_t savePP_OFF;
|
||||
uint32_t savePP_CONTROL;
|
||||
uint32_t savePP_CYCLE;
|
||||
uint32_t savePFIT_CONTROL;
|
||||
uint32_t savePaletteA[256];
|
||||
uint32_t savePaletteB[256];
|
||||
uint32_t saveBLC_PWM_CTL2;
|
||||
uint32_t saveBLC_PWM_CTL;
|
||||
uint32_t saveCLOCKGATING;
|
||||
uint32_t saveDSPARB;
|
||||
uint32_t saveDSPATILEOFF;
|
||||
uint32_t saveDSPBTILEOFF;
|
||||
uint32_t saveDSPAADDR;
|
||||
uint32_t saveDSPBADDR;
|
||||
uint32_t savePFIT_AUTO_RATIOS;
|
||||
uint32_t savePFIT_PGM_RATIOS;
|
||||
uint32_t savePP_ON_DELAYS;
|
||||
uint32_t savePP_OFF_DELAYS;
|
||||
uint32_t savePP_DIVISOR;
|
||||
uint32_t saveBSM;
|
||||
uint32_t saveVBT;
|
||||
uint32_t saveBCLRPAT_A;
|
||||
uint32_t saveBCLRPAT_B;
|
||||
uint32_t saveDSPALINOFF;
|
||||
uint32_t saveDSPBLINOFF;
|
||||
uint32_t savePERF_MODE;
|
||||
uint32_t saveDSPFW1;
|
||||
uint32_t saveDSPFW2;
|
||||
uint32_t saveDSPFW3;
|
||||
uint32_t saveDSPFW4;
|
||||
uint32_t saveDSPFW5;
|
||||
uint32_t saveDSPFW6;
|
||||
uint32_t saveCHICKENBIT;
|
||||
uint32_t saveDSPACURSOR_CTRL;
|
||||
uint32_t saveDSPBCURSOR_CTRL;
|
||||
uint32_t saveDSPACURSOR_BASE;
|
||||
uint32_t saveDSPBCURSOR_BASE;
|
||||
uint32_t saveDSPACURSOR_POS;
|
||||
uint32_t saveDSPBCURSOR_POS;
|
||||
uint32_t save_palette_a[256];
|
||||
uint32_t save_palette_b[256];
|
||||
uint32_t saveOV_OVADD;
|
||||
uint32_t saveOV_OGAMC0;
|
||||
uint32_t saveOV_OGAMC1;
|
||||
uint32_t saveOV_OGAMC2;
|
||||
uint32_t saveOV_OGAMC3;
|
||||
uint32_t saveOV_OGAMC4;
|
||||
uint32_t saveOV_OGAMC5;
|
||||
uint32_t saveOVC_OVADD;
|
||||
uint32_t saveOVC_OGAMC0;
|
||||
uint32_t saveOVC_OGAMC1;
|
||||
uint32_t saveOVC_OGAMC2;
|
||||
uint32_t saveOVC_OGAMC3;
|
||||
uint32_t saveOVC_OGAMC4;
|
||||
uint32_t saveOVC_OGAMC5;
|
||||
|
||||
/* MSI reg save */
|
||||
uint32_t msi_addr;
|
||||
uint32_t msi_data;
|
||||
|
||||
/* Medfield specific register save state */
|
||||
uint32_t saveHDMIPHYMISCCTL;
|
||||
uint32_t saveHDMIB_CONTROL;
|
||||
uint32_t saveDSPCCNTR;
|
||||
uint32_t savePIPECCONF;
|
||||
uint32_t savePIPECSRC;
|
||||
uint32_t saveHTOTAL_C;
|
||||
uint32_t saveHBLANK_C;
|
||||
uint32_t saveHSYNC_C;
|
||||
uint32_t saveVTOTAL_C;
|
||||
uint32_t saveVBLANK_C;
|
||||
uint32_t saveVSYNC_C;
|
||||
uint32_t saveDSPCSTRIDE;
|
||||
uint32_t saveDSPCSIZE;
|
||||
uint32_t saveDSPCPOS;
|
||||
uint32_t saveDSPCSURF;
|
||||
uint32_t saveDSPCSTATUS;
|
||||
uint32_t saveDSPCLINOFF;
|
||||
uint32_t saveDSPCTILEOFF;
|
||||
uint32_t saveDSPCCURSOR_CTRL;
|
||||
uint32_t saveDSPCCURSOR_BASE;
|
||||
uint32_t saveDSPCCURSOR_POS;
|
||||
uint32_t save_palette_c[256];
|
||||
uint32_t saveOV_OVADD_C;
|
||||
uint32_t saveOV_OGAMC0_C;
|
||||
uint32_t saveOV_OGAMC1_C;
|
||||
uint32_t saveOV_OGAMC2_C;
|
||||
uint32_t saveOV_OGAMC3_C;
|
||||
uint32_t saveOV_OGAMC4_C;
|
||||
uint32_t saveOV_OGAMC5_C;
|
||||
|
||||
/* DSI register save */
|
||||
uint32_t saveDEVICE_READY_REG;
|
||||
uint32_t saveINTR_EN_REG;
|
||||
uint32_t saveDSI_FUNC_PRG_REG;
|
||||
uint32_t saveHS_TX_TIMEOUT_REG;
|
||||
uint32_t saveLP_RX_TIMEOUT_REG;
|
||||
uint32_t saveTURN_AROUND_TIMEOUT_REG;
|
||||
uint32_t saveDEVICE_RESET_REG;
|
||||
uint32_t saveDPI_RESOLUTION_REG;
|
||||
uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
|
||||
uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
|
||||
uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
|
||||
uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
|
||||
uint32_t saveVERT_SYNC_PAD_COUNT_REG;
|
||||
uint32_t saveVERT_BACK_PORCH_COUNT_REG;
|
||||
uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
|
||||
uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
|
||||
uint32_t saveINIT_COUNT_REG;
|
||||
uint32_t saveMAX_RET_PAK_REG;
|
||||
uint32_t saveVIDEO_FMT_REG;
|
||||
uint32_t saveEOT_DISABLE_REG;
|
||||
uint32_t saveLP_BYTECLK_REG;
|
||||
uint32_t saveHS_LS_DBI_ENABLE_REG;
|
||||
uint32_t saveTXCLKESC_REG;
|
||||
uint32_t saveDPHY_PARAM_REG;
|
||||
uint32_t saveMIPI_CONTROL_REG;
|
||||
uint32_t saveMIPI;
|
||||
uint32_t saveMIPI_C;
|
||||
|
||||
/* DPST register save */
|
||||
uint32_t saveHISTOGRAM_INT_CONTROL_REG;
|
||||
uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
|
||||
uint32_t savePWM_CONTROL_LOGIC;
|
||||
|
||||
/*
|
||||
* DSI info.
|
||||
*/
|
||||
void * dbi_dsr_info;
|
||||
void * dbi_dpu_info;
|
||||
void * dsi_configs[2];
|
||||
/*
|
||||
* LID-Switch
|
||||
*/
|
||||
spinlock_t lid_lock;
|
||||
struct timer_list lid_timer;
|
||||
struct psb_intel_opregion opregion;
|
||||
u32 *lid_state;
|
||||
u32 lid_last_state;
|
||||
|
||||
/*
|
||||
* Watchdog
|
||||
*/
|
||||
|
||||
uint32_t apm_reg;
|
||||
uint16_t apm_base;
|
||||
|
||||
/*
|
||||
* Used for modifying backlight from
|
||||
* xrandr -- consider removing and using HAL instead
|
||||
*/
|
||||
struct backlight_device *backlight_device;
|
||||
struct drm_property *backlight_property;
|
||||
uint32_t blc_adj1;
|
||||
uint32_t blc_adj2;
|
||||
|
||||
void *fbdev;
|
||||
|
||||
/* 2D acceleration */
|
||||
struct mutex mutex_2d;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Operations for each board type
|
||||
*/
|
||||
|
||||
struct psb_ops {
|
||||
const char *name;
|
||||
unsigned int accel_2d:1;
|
||||
int pipes; /* Number of output pipes */
|
||||
int crtcs; /* Number of CRTCs */
|
||||
int sgx_offset; /* Base offset of SGX device */
|
||||
|
||||
/* Sub functions */
|
||||
struct drm_crtc_helper_funcs const *crtc_helper;
|
||||
struct drm_crtc_funcs const *crtc_funcs;
|
||||
|
||||
/* Setup hooks */
|
||||
int (*chip_setup)(struct drm_device *dev);
|
||||
void (*chip_teardown)(struct drm_device *dev);
|
||||
|
||||
/* Display management hooks */
|
||||
int (*output_init)(struct drm_device *dev);
|
||||
/* Power management hooks */
|
||||
void (*init_pm)(struct drm_device *dev);
|
||||
int (*save_regs)(struct drm_device *dev);
|
||||
int (*restore_regs)(struct drm_device *dev);
|
||||
int (*power_up)(struct drm_device *dev);
|
||||
int (*power_down)(struct drm_device *dev);
|
||||
|
||||
void (*lvds_bl_power)(struct drm_device *dev, bool on);
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
/* Backlight */
|
||||
int (*backlight_init)(struct drm_device *dev);
|
||||
#endif
|
||||
int i2c_bus; /* I2C bus identifier for Moorestown */
|
||||
};
|
||||
|
||||
|
||||
|
||||
struct psb_mmu_driver;
|
||||
|
||||
extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
|
||||
extern int drm_pick_crtcs(struct drm_device *dev);
|
||||
|
||||
static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
|
||||
{
|
||||
return (struct drm_psb_private *) dev->dev_private;
|
||||
}
|
||||
|
||||
/*
|
||||
* MMU stuff.
|
||||
*/
|
||||
|
||||
extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
|
||||
int trap_pagefaults,
|
||||
int invalid_type,
|
||||
struct drm_psb_private *dev_priv);
|
||||
extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
|
||||
extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
|
||||
*driver);
|
||||
extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
|
||||
uint32_t gtt_start, uint32_t gtt_pages);
|
||||
extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
|
||||
int trap_pagefaults,
|
||||
int invalid_type);
|
||||
extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
|
||||
extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
|
||||
extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
|
||||
unsigned long address,
|
||||
uint32_t num_pages);
|
||||
extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
|
||||
uint32_t start_pfn,
|
||||
unsigned long address,
|
||||
uint32_t num_pages, int type);
|
||||
extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
|
||||
unsigned long *pfn);
|
||||
|
||||
/*
|
||||
* Enable / disable MMU for different requestors.
|
||||
*/
|
||||
|
||||
|
||||
extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
|
||||
extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride, int type);
|
||||
extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
|
||||
unsigned long address, uint32_t num_pages,
|
||||
uint32_t desired_tile_stride,
|
||||
uint32_t hw_tile_stride);
|
||||
/*
|
||||
*psb_irq.c
|
||||
*/
|
||||
|
||||
extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
|
||||
extern int psb_irq_enable_dpst(struct drm_device *dev);
|
||||
extern int psb_irq_disable_dpst(struct drm_device *dev);
|
||||
extern void psb_irq_preinstall(struct drm_device *dev);
|
||||
extern int psb_irq_postinstall(struct drm_device *dev);
|
||||
extern void psb_irq_uninstall(struct drm_device *dev);
|
||||
extern void psb_irq_turn_on_dpst(struct drm_device *dev);
|
||||
extern void psb_irq_turn_off_dpst(struct drm_device *dev);
|
||||
|
||||
extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
|
||||
extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
|
||||
extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
|
||||
extern int psb_enable_vblank(struct drm_device *dev, int crtc);
|
||||
extern void psb_disable_vblank(struct drm_device *dev, int crtc);
|
||||
void
|
||||
psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
|
||||
|
||||
void
|
||||
psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
|
||||
|
||||
extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
|
||||
|
||||
/*
|
||||
* intel_opregion.c
|
||||
*/
|
||||
extern int gma_intel_opregion_init(struct drm_device *dev);
|
||||
extern int gma_intel_opregion_exit(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* framebuffer.c
|
||||
*/
|
||||
extern int psbfb_probed(struct drm_device *dev);
|
||||
extern int psbfb_remove(struct drm_device *dev,
|
||||
struct drm_framebuffer *fb);
|
||||
/*
|
||||
* accel_2d.c
|
||||
*/
|
||||
extern void psbfb_copyarea(struct fb_info *info,
|
||||
const struct fb_copyarea *region);
|
||||
extern int psbfb_sync(struct fb_info *info);
|
||||
extern void psb_spank(struct drm_psb_private *dev_priv);
|
||||
|
||||
/*
|
||||
* psb_reset.c
|
||||
*/
|
||||
|
||||
extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
|
||||
extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
|
||||
extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
|
||||
|
||||
/* modesetting */
|
||||
extern void psb_modeset_init(struct drm_device *dev);
|
||||
extern void psb_modeset_cleanup(struct drm_device *dev);
|
||||
extern int psb_fbdev_init(struct drm_device *dev);
|
||||
|
||||
/* backlight.c */
|
||||
int gma_backlight_init(struct drm_device *dev);
|
||||
void gma_backlight_exit(struct drm_device *dev);
|
||||
|
||||
/* oaktrail_crtc.c */
|
||||
extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
|
||||
|
||||
/* oaktrail_lvds.c */
|
||||
extern void oaktrail_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
|
||||
/* psb_intel_display.c */
|
||||
extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
|
||||
extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
|
||||
|
||||
/* psb_intel_lvds.c */
|
||||
extern const struct drm_connector_helper_funcs
|
||||
psb_intel_lvds_connector_helper_funcs;
|
||||
extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
|
||||
|
||||
/* gem.c */
|
||||
extern int psb_gem_init_object(struct drm_gem_object *obj);
|
||||
extern void psb_gem_free_object(struct drm_gem_object *obj);
|
||||
extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
|
||||
struct drm_file *file);
|
||||
extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
|
||||
struct drm_mode_create_dumb *args);
|
||||
extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
|
||||
uint32_t handle);
|
||||
extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
|
||||
uint32_t handle, uint64_t *offset);
|
||||
extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
|
||||
extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file);
|
||||
extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *file);
|
||||
|
||||
/* psb_device.c */
|
||||
extern const struct psb_ops psb_chip_ops;
|
||||
|
||||
/* oaktrail_device.c */
|
||||
extern const struct psb_ops oaktrail_chip_ops;
|
||||
|
||||
/* cdv_device.c */
|
||||
extern const struct psb_ops cdv_chip_ops;
|
||||
|
||||
/*
|
||||
* Debug print bits setting
|
||||
*/
|
||||
#define PSB_D_GENERAL (1 << 0)
|
||||
#define PSB_D_INIT (1 << 1)
|
||||
#define PSB_D_IRQ (1 << 2)
|
||||
#define PSB_D_ENTRY (1 << 3)
|
||||
/* debug the get H/V BP/FP count */
|
||||
#define PSB_D_HV (1 << 4)
|
||||
#define PSB_D_DBI_BF (1 << 5)
|
||||
#define PSB_D_PM (1 << 6)
|
||||
#define PSB_D_RENDER (1 << 7)
|
||||
#define PSB_D_REG (1 << 8)
|
||||
#define PSB_D_MSVDX (1 << 9)
|
||||
#define PSB_D_TOPAZ (1 << 10)
|
||||
|
||||
extern int drm_psb_no_fb;
|
||||
extern int drm_idle_check_interval;
|
||||
|
||||
/*
|
||||
* Utilities
|
||||
*/
|
||||
|
||||
static inline u32 MRST_MSG_READ32(uint port, uint offset)
|
||||
{
|
||||
int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
|
||||
uint32_t ret_val = 0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
||||
pci_dev_put(pci_root);
|
||||
return ret_val;
|
||||
}
|
||||
static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
|
||||
{
|
||||
int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD4, value);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
|
||||
{
|
||||
int mcr = (0x10<<24) | (port << 16) | (offset << 8);
|
||||
uint32_t ret_val = 0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_read_config_dword(pci_root, 0xD4, &ret_val);
|
||||
pci_dev_put(pci_root);
|
||||
return ret_val;
|
||||
}
|
||||
static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
|
||||
{
|
||||
int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
pci_write_config_dword(pci_root, 0xD4, value);
|
||||
pci_write_config_dword(pci_root, 0xD0, mcr);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
|
||||
static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
return ioread32(dev_priv->vdc_reg + reg);
|
||||
}
|
||||
|
||||
#define REG_READ(reg) REGISTER_READ(dev, (reg))
|
||||
|
||||
static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
|
||||
uint32_t val)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
iowrite32((val), dev_priv->vdc_reg + (reg));
|
||||
}
|
||||
|
||||
#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
|
||||
|
||||
static inline void REGISTER_WRITE16(struct drm_device *dev,
|
||||
uint32_t reg, uint32_t val)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
iowrite16((val), dev_priv->vdc_reg + (reg));
|
||||
}
|
||||
|
||||
#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
|
||||
|
||||
static inline void REGISTER_WRITE8(struct drm_device *dev,
|
||||
uint32_t reg, uint32_t val)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
iowrite8((val), dev_priv->vdc_reg + (reg));
|
||||
}
|
||||
|
||||
#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
|
||||
|
||||
#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
|
||||
#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
|
||||
|
||||
/* #define TRAP_SGX_PM_FAULT 1 */
|
||||
#ifdef TRAP_SGX_PM_FAULT
|
||||
#define PSB_RSGX32(_offs) \
|
||||
({ \
|
||||
if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
|
||||
printk(KERN_ERR \
|
||||
"access sgx when it's off!! (READ) %s, %d\n", \
|
||||
__FILE__, __LINE__); \
|
||||
melay(1000); \
|
||||
} \
|
||||
ioread32(dev_priv->sgx_reg + (_offs)); \
|
||||
})
|
||||
#else
|
||||
#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
|
||||
#endif
|
||||
#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
|
||||
|
||||
#define MSVDX_REG_DUMP 0
|
||||
|
||||
#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
|
||||
#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
|
||||
|
||||
#endif
|
51
drivers/gpu/drm/gma500/psb_gfx.mod.c
Normal file
51
drivers/gpu/drm/gma500/psb_gfx.mod.c
Normal file
@ -0,0 +1,51 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/vermagic.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
MODULE_INFO(vermagic, VERMAGIC_STRING);
|
||||
|
||||
struct module __this_module
|
||||
__attribute__((section(".gnu.linkonce.this_module"))) = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.init = init_module,
|
||||
#ifdef CONFIG_MODULE_UNLOAD
|
||||
.exit = cleanup_module,
|
||||
#endif
|
||||
.arch = MODULE_ARCH_INIT,
|
||||
};
|
||||
|
||||
MODULE_INFO(staging, "Y");
|
||||
|
||||
static const char __module_depends[]
|
||||
__used
|
||||
__attribute__((section(".modinfo"))) =
|
||||
"depends=drm,drm_kms_helper,video,i2c-algo-bit";
|
||||
|
||||
MODULE_ALIAS("pci:v00008086d00008108sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00008109sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004100sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004101sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004102sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004103sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004104sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004105sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004106sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00004107sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000130sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000131sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000132sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000133sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000134sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000135sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000136sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000137sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE0sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE1sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE2sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE3sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE4sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE5sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE6sv*sd*bc*sc*i*");
|
||||
MODULE_ALIAS("pci:v00008086d00000BE7sv*sd*bc*sc*i*");
|
||||
|
||||
MODULE_INFO(srcversion, "51B3334F342F5EEAC93AF22");
|
1431
drivers/gpu/drm/gma500/psb_intel_display.c
Normal file
1431
drivers/gpu/drm/gma500/psb_intel_display.c
Normal file
File diff suppressed because it is too large
Load Diff
28
drivers/gpu/drm/gma500/psb_intel_display.h
Normal file
28
drivers/gpu/drm/gma500/psb_intel_display.h
Normal file
@ -0,0 +1,28 @@
|
||||
/* copyright (c) 2008, Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*/
|
||||
|
||||
#ifndef _INTEL_DISPLAY_H_
|
||||
#define _INTEL_DISPLAY_H_
|
||||
|
||||
bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type);
|
||||
void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
|
||||
u16 *green, u16 *blue, uint32_t type, uint32_t size);
|
||||
void psb_intel_crtc_destroy(struct drm_crtc *crtc);
|
||||
|
||||
#endif
|
228
drivers/gpu/drm/gma500/psb_intel_drv.h
Normal file
228
drivers/gpu/drm/gma500/psb_intel_drv.h
Normal file
@ -0,0 +1,228 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __INTEL_DRV_H__
|
||||
#define __INTEL_DRV_H__
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-algo-bit.h>
|
||||
#include <drm/drm_crtc.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
/*
|
||||
* Display related stuff
|
||||
*/
|
||||
|
||||
/* store information about an Ixxx DVO */
|
||||
/* The i830->i865 use multiple DVOs with multiple i2cs */
|
||||
/* the i915, i945 have a single sDVO i2c bus - which is different */
|
||||
#define MAX_OUTPUTS 6
|
||||
/* maximum connectors per crtcs in the mode set */
|
||||
#define INTELFB_CONN_LIMIT 4
|
||||
|
||||
#define INTEL_I2C_BUS_DVO 1
|
||||
#define INTEL_I2C_BUS_SDVO 2
|
||||
|
||||
/* these are outputs from the chip - integrated only
|
||||
* external chips are via DVO or SDVO output */
|
||||
#define INTEL_OUTPUT_UNUSED 0
|
||||
#define INTEL_OUTPUT_ANALOG 1
|
||||
#define INTEL_OUTPUT_DVO 2
|
||||
#define INTEL_OUTPUT_SDVO 3
|
||||
#define INTEL_OUTPUT_LVDS 4
|
||||
#define INTEL_OUTPUT_TVOUT 5
|
||||
#define INTEL_OUTPUT_HDMI 6
|
||||
#define INTEL_OUTPUT_MIPI 7
|
||||
#define INTEL_OUTPUT_MIPI2 8
|
||||
|
||||
#define INTEL_DVO_CHIP_NONE 0
|
||||
#define INTEL_DVO_CHIP_LVDS 1
|
||||
#define INTEL_DVO_CHIP_TMDS 2
|
||||
#define INTEL_DVO_CHIP_TVOUT 4
|
||||
|
||||
/*
|
||||
* Hold information useally put on the device driver privates here,
|
||||
* since it needs to be shared across multiple of devices drivers privates.
|
||||
*/
|
||||
struct psb_intel_mode_device {
|
||||
|
||||
/*
|
||||
* Abstracted memory manager operations
|
||||
*/
|
||||
size_t(*bo_offset) (struct drm_device *dev, void *bo);
|
||||
|
||||
/*
|
||||
* Cursor (Can go ?)
|
||||
*/
|
||||
int cursor_needs_physical;
|
||||
|
||||
/*
|
||||
* LVDS info
|
||||
*/
|
||||
int backlight_duty_cycle; /* restore backlight to this value */
|
||||
bool panel_wants_dither;
|
||||
struct drm_display_mode *panel_fixed_mode;
|
||||
struct drm_display_mode *panel_fixed_mode2;
|
||||
struct drm_display_mode *vbt_mode; /* if any */
|
||||
|
||||
uint32_t saveBLC_PWM_CTL;
|
||||
};
|
||||
|
||||
struct psb_intel_i2c_chan {
|
||||
/* for getting at dev. private (mmio etc.) */
|
||||
struct drm_device *drm_dev;
|
||||
u32 reg; /* GPIO reg */
|
||||
struct i2c_adapter adapter;
|
||||
struct i2c_algo_bit_data algo;
|
||||
u8 slave_addr;
|
||||
};
|
||||
|
||||
struct psb_intel_output {
|
||||
struct drm_connector base;
|
||||
|
||||
struct drm_encoder enc;
|
||||
int type;
|
||||
|
||||
struct psb_intel_i2c_chan *i2c_bus; /* for control functions */
|
||||
struct psb_intel_i2c_chan *ddc_bus; /* for DDC only stuff */
|
||||
bool load_detect_temp;
|
||||
void *dev_priv;
|
||||
|
||||
struct psb_intel_mode_device *mode_dev;
|
||||
struct i2c_adapter *hdmi_i2c_adapter; /* for control functions */
|
||||
};
|
||||
|
||||
struct psb_intel_crtc_state {
|
||||
uint32_t saveDSPCNTR;
|
||||
uint32_t savePIPECONF;
|
||||
uint32_t savePIPESRC;
|
||||
uint32_t saveDPLL;
|
||||
uint32_t saveFP0;
|
||||
uint32_t saveFP1;
|
||||
uint32_t saveHTOTAL;
|
||||
uint32_t saveHBLANK;
|
||||
uint32_t saveHSYNC;
|
||||
uint32_t saveVTOTAL;
|
||||
uint32_t saveVBLANK;
|
||||
uint32_t saveVSYNC;
|
||||
uint32_t saveDSPSTRIDE;
|
||||
uint32_t saveDSPSIZE;
|
||||
uint32_t saveDSPPOS;
|
||||
uint32_t saveDSPBASE;
|
||||
uint32_t savePalette[256];
|
||||
};
|
||||
|
||||
struct psb_intel_crtc {
|
||||
struct drm_crtc base;
|
||||
int pipe;
|
||||
int plane;
|
||||
uint32_t cursor_addr;
|
||||
u8 lut_r[256], lut_g[256], lut_b[256];
|
||||
u8 lut_adj[256];
|
||||
struct psb_intel_framebuffer *fbdev_fb;
|
||||
/* a mode_set for fbdev users on this crtc */
|
||||
struct drm_mode_set mode_set;
|
||||
|
||||
/* GEM object that holds our cursor */
|
||||
struct drm_gem_object *cursor_obj;
|
||||
|
||||
struct drm_display_mode saved_mode;
|
||||
struct drm_display_mode saved_adjusted_mode;
|
||||
|
||||
struct psb_intel_mode_device *mode_dev;
|
||||
|
||||
/*crtc mode setting flags*/
|
||||
u32 mode_flags;
|
||||
|
||||
/* Saved Crtc HW states */
|
||||
struct psb_intel_crtc_state *crtc_state;
|
||||
};
|
||||
|
||||
#define to_psb_intel_crtc(x) \
|
||||
container_of(x, struct psb_intel_crtc, base)
|
||||
#define to_psb_intel_output(x) \
|
||||
container_of(x, struct psb_intel_output, base)
|
||||
#define enc_to_psb_intel_output(x) \
|
||||
container_of(x, struct psb_intel_output, enc)
|
||||
#define to_psb_intel_framebuffer(x) \
|
||||
container_of(x, struct psb_intel_framebuffer, base)
|
||||
|
||||
struct psb_intel_i2c_chan *psb_intel_i2c_create(struct drm_device *dev,
|
||||
const u32 reg, const char *name);
|
||||
void psb_intel_i2c_destroy(struct psb_intel_i2c_chan *chan);
|
||||
int psb_intel_ddc_get_modes(struct psb_intel_output *psb_intel_output);
|
||||
extern bool psb_intel_ddc_probe(struct psb_intel_output *psb_intel_output);
|
||||
|
||||
extern void psb_intel_crtc_init(struct drm_device *dev, int pipe,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
extern void psb_intel_crt_init(struct drm_device *dev);
|
||||
extern void psb_intel_sdvo_init(struct drm_device *dev, int output_device);
|
||||
extern void psb_intel_dvo_init(struct drm_device *dev);
|
||||
extern void psb_intel_tv_init(struct drm_device *dev);
|
||||
extern void psb_intel_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
extern void psb_intel_lvds_set_brightness(struct drm_device *dev, int level);
|
||||
extern void oaktrail_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
extern void oaktrail_wait_for_INTR_PKT_SENT(struct drm_device *dev);
|
||||
extern void oaktrail_dsi_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev);
|
||||
extern void mid_dsi_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev, int dsi_num);
|
||||
|
||||
extern void psb_intel_crtc_load_lut(struct drm_crtc *crtc);
|
||||
extern void psb_intel_encoder_prepare(struct drm_encoder *encoder);
|
||||
extern void psb_intel_encoder_commit(struct drm_encoder *encoder);
|
||||
|
||||
extern struct drm_encoder *psb_intel_best_encoder(struct drm_connector
|
||||
*connector);
|
||||
|
||||
extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
|
||||
struct drm_crtc *crtc);
|
||||
extern void psb_intel_wait_for_vblank(struct drm_device *dev);
|
||||
extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv);
|
||||
extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev,
|
||||
int pipe);
|
||||
extern struct drm_connector *psb_intel_sdvo_find(struct drm_device *dev,
|
||||
int sdvoB);
|
||||
extern int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector);
|
||||
extern void psb_intel_sdvo_set_hotplug(struct drm_connector *connector,
|
||||
int enable);
|
||||
extern int intelfb_probe(struct drm_device *dev);
|
||||
extern int intelfb_remove(struct drm_device *dev,
|
||||
struct drm_framebuffer *fb);
|
||||
extern struct drm_framebuffer *psb_intel_framebuffer_create(struct drm_device
|
||||
*dev, struct
|
||||
drm_mode_fb_cmd
|
||||
*mode_cmd,
|
||||
void *mm_private);
|
||||
extern bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode);
|
||||
extern int psb_intel_lvds_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode);
|
||||
extern int psb_intel_lvds_set_property(struct drm_connector *connector,
|
||||
struct drm_property *property,
|
||||
uint64_t value);
|
||||
extern void psb_intel_lvds_destroy(struct drm_connector *connector);
|
||||
extern const struct drm_encoder_funcs psb_intel_lvds_enc_funcs;
|
||||
|
||||
|
||||
#endif /* __INTEL_DRV_H__ */
|
849
drivers/gpu/drm/gma500/psb_intel_lvds.c
Normal file
849
drivers/gpu/drm/gma500/psb_intel_lvds.c
Normal file
@ -0,0 +1,849 @@
|
||||
/*
|
||||
* Copyright © 2006-2007 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
* Dave Airlie <airlied@linux.ie>
|
||||
* Jesse Barnes <jesse.barnes@intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <drm/drmP.h>
|
||||
|
||||
#include "intel_bios.h"
|
||||
#include "psb_drv.h"
|
||||
#include "psb_intel_drv.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "power.h"
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
/*
|
||||
* LVDS I2C backlight control macros
|
||||
*/
|
||||
#define BRIGHTNESS_MAX_LEVEL 100
|
||||
#define BRIGHTNESS_MASK 0xFF
|
||||
#define BLC_I2C_TYPE 0x01
|
||||
#define BLC_PWM_TYPT 0x02
|
||||
|
||||
#define BLC_POLARITY_NORMAL 0
|
||||
#define BLC_POLARITY_INVERSE 1
|
||||
|
||||
#define PSB_BLC_MAX_PWM_REG_FREQ (0xFFFE)
|
||||
#define PSB_BLC_MIN_PWM_REG_FREQ (0x2)
|
||||
#define PSB_BLC_PWM_PRECISION_FACTOR (10)
|
||||
#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
|
||||
#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
|
||||
|
||||
struct psb_intel_lvds_priv {
|
||||
/*
|
||||
* Saved LVDO output states
|
||||
*/
|
||||
uint32_t savePP_ON;
|
||||
uint32_t savePP_OFF;
|
||||
uint32_t saveLVDS;
|
||||
uint32_t savePP_CONTROL;
|
||||
uint32_t savePP_CYCLE;
|
||||
uint32_t savePFIT_CONTROL;
|
||||
uint32_t savePFIT_PGM_RATIOS;
|
||||
uint32_t saveBLC_PWM_CTL;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Returns the maximum level of the backlight duty cycle field.
|
||||
*/
|
||||
static u32 psb_intel_lvds_get_max_backlight(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 retVal;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
retVal = ((REG_READ(BLC_PWM_CTL) &
|
||||
BACKLIGHT_MODULATION_FREQ_MASK) >>
|
||||
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
|
||||
|
||||
gma_power_end(dev);
|
||||
} else
|
||||
retVal = ((dev_priv->saveBLC_PWM_CTL &
|
||||
BACKLIGHT_MODULATION_FREQ_MASK) >>
|
||||
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set LVDS backlight level by I2C command
|
||||
*
|
||||
* FIXME: at some point we need to both track this for PM and also
|
||||
* disable runtime pm on MRST if the brightness is nil (ie blanked)
|
||||
*/
|
||||
static int psb_lvds_i2c_set_brightness(struct drm_device *dev,
|
||||
unsigned int level)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private;
|
||||
|
||||
struct psb_intel_i2c_chan *lvds_i2c_bus = dev_priv->lvds_i2c_bus;
|
||||
u8 out_buf[2];
|
||||
unsigned int blc_i2c_brightness;
|
||||
|
||||
struct i2c_msg msgs[] = {
|
||||
{
|
||||
.addr = lvds_i2c_bus->slave_addr,
|
||||
.flags = 0,
|
||||
.len = 2,
|
||||
.buf = out_buf,
|
||||
}
|
||||
};
|
||||
|
||||
blc_i2c_brightness = BRIGHTNESS_MASK & ((unsigned int)level *
|
||||
BRIGHTNESS_MASK /
|
||||
BRIGHTNESS_MAX_LEVEL);
|
||||
|
||||
if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)
|
||||
blc_i2c_brightness = BRIGHTNESS_MASK - blc_i2c_brightness;
|
||||
|
||||
out_buf[0] = dev_priv->lvds_bl->brightnesscmd;
|
||||
out_buf[1] = (u8)blc_i2c_brightness;
|
||||
|
||||
if (i2c_transfer(&lvds_i2c_bus->adapter, msgs, 1) == 1) {
|
||||
dev_dbg(dev->dev, "I2C set brightness.(command, value) (%d, %d)\n",
|
||||
dev_priv->lvds_bl->brightnesscmd,
|
||||
blc_i2c_brightness);
|
||||
return 0;
|
||||
}
|
||||
|
||||
dev_err(dev->dev, "I2C transfer error\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static int psb_lvds_pwm_set_brightness(struct drm_device *dev, int level)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private;
|
||||
|
||||
u32 max_pwm_blc;
|
||||
u32 blc_pwm_duty_cycle;
|
||||
|
||||
max_pwm_blc = psb_intel_lvds_get_max_backlight(dev);
|
||||
|
||||
/*BLC_PWM_CTL Should be initiated while backlight device init*/
|
||||
BUG_ON((max_pwm_blc & PSB_BLC_MAX_PWM_REG_FREQ) == 0);
|
||||
|
||||
blc_pwm_duty_cycle = level * max_pwm_blc / BRIGHTNESS_MAX_LEVEL;
|
||||
|
||||
if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)
|
||||
blc_pwm_duty_cycle = max_pwm_blc - blc_pwm_duty_cycle;
|
||||
|
||||
blc_pwm_duty_cycle &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
|
||||
REG_WRITE(BLC_PWM_CTL,
|
||||
(max_pwm_blc << PSB_BACKLIGHT_PWM_CTL_SHIFT) |
|
||||
(blc_pwm_duty_cycle));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set LVDS backlight level either by I2C or PWM
|
||||
*/
|
||||
void psb_intel_lvds_set_brightness(struct drm_device *dev, int level)
|
||||
{
|
||||
/*u32 blc_pwm_ctl;*/
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private;
|
||||
|
||||
dev_dbg(dev->dev, "backlight level is %d\n", level);
|
||||
|
||||
if (!dev_priv->lvds_bl) {
|
||||
dev_err(dev->dev, "NO LVDS Backlight Info\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (dev_priv->lvds_bl->type == BLC_I2C_TYPE)
|
||||
psb_lvds_i2c_set_brightness(dev, level);
|
||||
else
|
||||
psb_lvds_pwm_set_brightness(dev, level);
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the backlight level.
|
||||
*
|
||||
* level: backlight level, from 0 to psb_intel_lvds_get_max_backlight().
|
||||
*/
|
||||
static void psb_intel_lvds_set_backlight(struct drm_device *dev, int level)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 blc_pwm_ctl;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
blc_pwm_ctl =
|
||||
REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
|
||||
REG_WRITE(BLC_PWM_CTL,
|
||||
(blc_pwm_ctl |
|
||||
(level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
|
||||
gma_power_end(dev);
|
||||
} else {
|
||||
blc_pwm_ctl = dev_priv->saveBLC_PWM_CTL &
|
||||
~BACKLIGHT_DUTY_CYCLE_MASK;
|
||||
dev_priv->saveBLC_PWM_CTL = (blc_pwm_ctl |
|
||||
(level << BACKLIGHT_DUTY_CYCLE_SHIFT));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the power state for the panel.
|
||||
*/
|
||||
static void psb_intel_lvds_set_power(struct drm_device *dev,
|
||||
struct psb_intel_output *output, bool on)
|
||||
{
|
||||
u32 pp_status;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
if (on) {
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
|
||||
POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while ((pp_status & PP_ON) == 0);
|
||||
|
||||
psb_intel_lvds_set_backlight(dev,
|
||||
output->
|
||||
mode_dev->backlight_duty_cycle);
|
||||
} else {
|
||||
psb_intel_lvds_set_backlight(dev, 0);
|
||||
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
|
||||
~POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while (pp_status & PP_ON);
|
||||
}
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
static void psb_intel_lvds_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
|
||||
if (mode == DRM_MODE_DPMS_ON)
|
||||
psb_intel_lvds_set_power(dev, output, true);
|
||||
else
|
||||
psb_intel_lvds_set_power(dev, output, false);
|
||||
|
||||
/* XXX: We never power down the LVDS pairs. */
|
||||
}
|
||||
|
||||
static void psb_intel_lvds_save(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private;
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct psb_intel_lvds_priv *lvds_priv =
|
||||
(struct psb_intel_lvds_priv *)psb_intel_output->dev_priv;
|
||||
|
||||
lvds_priv->savePP_ON = REG_READ(LVDSPP_ON);
|
||||
lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF);
|
||||
lvds_priv->saveLVDS = REG_READ(LVDS);
|
||||
lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL);
|
||||
lvds_priv->savePP_CYCLE = REG_READ(PP_CYCLE);
|
||||
/*lvds_priv->savePP_DIVISOR = REG_READ(PP_DIVISOR);*/
|
||||
lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
|
||||
lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
|
||||
lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
|
||||
|
||||
/*TODO: move backlight_duty_cycle to psb_intel_lvds_priv*/
|
||||
dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
|
||||
BACKLIGHT_DUTY_CYCLE_MASK);
|
||||
|
||||
/*
|
||||
* If the light is off at server startup,
|
||||
* just make it full brightness
|
||||
*/
|
||||
if (dev_priv->backlight_duty_cycle == 0)
|
||||
dev_priv->backlight_duty_cycle =
|
||||
psb_intel_lvds_get_max_backlight(dev);
|
||||
|
||||
dev_dbg(dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n",
|
||||
lvds_priv->savePP_ON,
|
||||
lvds_priv->savePP_OFF,
|
||||
lvds_priv->saveLVDS,
|
||||
lvds_priv->savePP_CONTROL,
|
||||
lvds_priv->savePP_CYCLE,
|
||||
lvds_priv->saveBLC_PWM_CTL);
|
||||
}
|
||||
|
||||
static void psb_intel_lvds_restore(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
u32 pp_status;
|
||||
|
||||
/*struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private;*/
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct psb_intel_lvds_priv *lvds_priv =
|
||||
(struct psb_intel_lvds_priv *)psb_intel_output->dev_priv;
|
||||
|
||||
dev_dbg(dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n",
|
||||
lvds_priv->savePP_ON,
|
||||
lvds_priv->savePP_OFF,
|
||||
lvds_priv->saveLVDS,
|
||||
lvds_priv->savePP_CONTROL,
|
||||
lvds_priv->savePP_CYCLE,
|
||||
lvds_priv->saveBLC_PWM_CTL);
|
||||
|
||||
REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL);
|
||||
REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL);
|
||||
REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS);
|
||||
REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON);
|
||||
REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF);
|
||||
/*REG_WRITE(PP_DIVISOR, lvds_priv->savePP_DIVISOR);*/
|
||||
REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE);
|
||||
REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL);
|
||||
REG_WRITE(LVDS, lvds_priv->saveLVDS);
|
||||
|
||||
if (lvds_priv->savePP_CONTROL & POWER_TARGET_ON) {
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
|
||||
POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while ((pp_status & PP_ON) == 0);
|
||||
} else {
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
|
||||
~POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while (pp_status & PP_ON);
|
||||
}
|
||||
}
|
||||
|
||||
int psb_intel_lvds_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct drm_display_mode *fixed_mode =
|
||||
psb_intel_output->mode_dev->panel_fixed_mode;
|
||||
|
||||
if (psb_intel_output->type == INTEL_OUTPUT_MIPI2)
|
||||
fixed_mode = psb_intel_output->mode_dev->panel_fixed_mode2;
|
||||
|
||||
/* just in case */
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
||||
return MODE_NO_DBLESCAN;
|
||||
|
||||
/* just in case */
|
||||
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
||||
return MODE_NO_INTERLACE;
|
||||
|
||||
if (fixed_mode) {
|
||||
if (mode->hdisplay > fixed_mode->hdisplay)
|
||||
return MODE_PANEL;
|
||||
if (mode->vdisplay > fixed_mode->vdisplay)
|
||||
return MODE_PANEL;
|
||||
}
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct psb_intel_mode_device *mode_dev =
|
||||
enc_to_psb_intel_output(encoder)->mode_dev;
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_crtc *psb_intel_crtc =
|
||||
to_psb_intel_crtc(encoder->crtc);
|
||||
struct drm_encoder *tmp_encoder;
|
||||
struct drm_display_mode *panel_fixed_mode = mode_dev->panel_fixed_mode;
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
enc_to_psb_intel_output(encoder);
|
||||
|
||||
if (psb_intel_output->type == INTEL_OUTPUT_MIPI2)
|
||||
panel_fixed_mode = mode_dev->panel_fixed_mode2;
|
||||
|
||||
/* FIXME: review for Medfield */
|
||||
/* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */
|
||||
if (!IS_MRST(dev) && psb_intel_crtc->pipe == 0) {
|
||||
printk(KERN_ERR "Can't support LVDS on pipe A\n");
|
||||
return false;
|
||||
}
|
||||
if (IS_MRST(dev) && psb_intel_crtc->pipe != 0) {
|
||||
printk(KERN_ERR "Must use PIPE A\n");
|
||||
return false;
|
||||
}
|
||||
/* Should never happen!! */
|
||||
list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list,
|
||||
head) {
|
||||
if (tmp_encoder != encoder
|
||||
&& tmp_encoder->crtc == encoder->crtc) {
|
||||
printk(KERN_ERR "Can't enable LVDS and another "
|
||||
"encoder on the same pipe\n");
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If we have timings from the BIOS for the panel, put them in
|
||||
* to the adjusted mode. The CRTC will be set up for this mode,
|
||||
* with the panel scaling set up to source from the H/VDisplay
|
||||
* of the original mode.
|
||||
*/
|
||||
if (panel_fixed_mode != NULL) {
|
||||
adjusted_mode->hdisplay = panel_fixed_mode->hdisplay;
|
||||
adjusted_mode->hsync_start = panel_fixed_mode->hsync_start;
|
||||
adjusted_mode->hsync_end = panel_fixed_mode->hsync_end;
|
||||
adjusted_mode->htotal = panel_fixed_mode->htotal;
|
||||
adjusted_mode->vdisplay = panel_fixed_mode->vdisplay;
|
||||
adjusted_mode->vsync_start = panel_fixed_mode->vsync_start;
|
||||
adjusted_mode->vsync_end = panel_fixed_mode->vsync_end;
|
||||
adjusted_mode->vtotal = panel_fixed_mode->vtotal;
|
||||
adjusted_mode->clock = panel_fixed_mode->clock;
|
||||
drm_mode_set_crtcinfo(adjusted_mode,
|
||||
CRTC_INTERLACE_HALVE_V);
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX: It would be nice to support lower refresh rates on the
|
||||
* panels to reduce power consumption, and perhaps match the
|
||||
* user's requested refresh rate.
|
||||
*/
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void psb_intel_lvds_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct psb_intel_mode_device *mode_dev = output->mode_dev;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
||||
mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
|
||||
mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
|
||||
BACKLIGHT_DUTY_CYCLE_MASK);
|
||||
|
||||
psb_intel_lvds_set_power(dev, output, false);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
static void psb_intel_lvds_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
|
||||
struct psb_intel_mode_device *mode_dev = output->mode_dev;
|
||||
|
||||
if (mode_dev->backlight_duty_cycle == 0)
|
||||
mode_dev->backlight_duty_cycle =
|
||||
psb_intel_lvds_get_max_backlight(dev);
|
||||
|
||||
psb_intel_lvds_set_power(dev, output, true);
|
||||
}
|
||||
|
||||
static void psb_intel_lvds_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 pfit_control;
|
||||
|
||||
/*
|
||||
* The LVDS pin pair will already have been turned on in the
|
||||
* psb_intel_crtc_mode_set since it has a large impact on the DPLL
|
||||
* settings.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Enable automatic panel scaling so that non-native modes fill the
|
||||
* screen. Should be enabled before the pipe is enabled, according to
|
||||
* register description and PRM.
|
||||
*/
|
||||
if (mode->hdisplay != adjusted_mode->hdisplay ||
|
||||
mode->vdisplay != adjusted_mode->vdisplay)
|
||||
pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
|
||||
HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR |
|
||||
HORIZ_INTERP_BILINEAR);
|
||||
else
|
||||
pfit_control = 0;
|
||||
|
||||
if (dev_priv->lvds_dither)
|
||||
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
|
||||
|
||||
REG_WRITE(PFIT_CONTROL, pfit_control);
|
||||
}
|
||||
|
||||
/*
|
||||
* Detect the LVDS connection.
|
||||
*
|
||||
* This always returns CONNECTOR_STATUS_CONNECTED.
|
||||
* This connector should only have
|
||||
* been set up if the LVDS was actually connected anyway.
|
||||
*/
|
||||
static enum drm_connector_status psb_intel_lvds_detect(struct drm_connector
|
||||
*connector, bool force)
|
||||
{
|
||||
return connector_status_connected;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
|
||||
*/
|
||||
static int psb_intel_lvds_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
struct psb_intel_mode_device *mode_dev =
|
||||
psb_intel_output->mode_dev;
|
||||
int ret = 0;
|
||||
|
||||
if (!IS_MRST(dev))
|
||||
ret = psb_intel_ddc_get_modes(psb_intel_output);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Didn't get an EDID, so
|
||||
* Set wide sync ranges so we get all modes
|
||||
* handed to valid_mode for checking
|
||||
*/
|
||||
connector->display_info.min_vfreq = 0;
|
||||
connector->display_info.max_vfreq = 200;
|
||||
connector->display_info.min_hfreq = 0;
|
||||
connector->display_info.max_hfreq = 200;
|
||||
|
||||
if (mode_dev->panel_fixed_mode != NULL) {
|
||||
struct drm_display_mode *mode =
|
||||
drm_mode_duplicate(dev, mode_dev->panel_fixed_mode);
|
||||
drm_mode_probed_add(connector, mode);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_intel_lvds_destroy - unregister and free LVDS structures
|
||||
* @connector: connector to free
|
||||
*
|
||||
* Unregister the DDC bus for this connector then free the driver private
|
||||
* structure.
|
||||
*/
|
||||
void psb_intel_lvds_destroy(struct drm_connector *connector)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output =
|
||||
to_psb_intel_output(connector);
|
||||
|
||||
if (psb_intel_output->ddc_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->ddc_bus);
|
||||
drm_sysfs_connector_remove(connector);
|
||||
drm_connector_cleanup(connector);
|
||||
kfree(connector);
|
||||
}
|
||||
|
||||
int psb_intel_lvds_set_property(struct drm_connector *connector,
|
||||
struct drm_property *property,
|
||||
uint64_t value)
|
||||
{
|
||||
struct drm_encoder *encoder = connector->encoder;
|
||||
|
||||
if (!encoder)
|
||||
return -1;
|
||||
|
||||
if (!strcmp(property->name, "scaling mode")) {
|
||||
struct psb_intel_crtc *crtc =
|
||||
to_psb_intel_crtc(encoder->crtc);
|
||||
uint64_t curval;
|
||||
|
||||
if (!crtc)
|
||||
goto set_prop_error;
|
||||
|
||||
switch (value) {
|
||||
case DRM_MODE_SCALE_FULLSCREEN:
|
||||
break;
|
||||
case DRM_MODE_SCALE_NO_SCALE:
|
||||
break;
|
||||
case DRM_MODE_SCALE_ASPECT:
|
||||
break;
|
||||
default:
|
||||
goto set_prop_error;
|
||||
}
|
||||
|
||||
if (drm_connector_property_get_value(connector,
|
||||
property,
|
||||
&curval))
|
||||
goto set_prop_error;
|
||||
|
||||
if (curval == value)
|
||||
goto set_prop_done;
|
||||
|
||||
if (drm_connector_property_set_value(connector,
|
||||
property,
|
||||
value))
|
||||
goto set_prop_error;
|
||||
|
||||
if (crtc->saved_mode.hdisplay != 0 &&
|
||||
crtc->saved_mode.vdisplay != 0) {
|
||||
if (!drm_crtc_helper_set_mode(encoder->crtc,
|
||||
&crtc->saved_mode,
|
||||
encoder->crtc->x,
|
||||
encoder->crtc->y,
|
||||
encoder->crtc->fb))
|
||||
goto set_prop_error;
|
||||
}
|
||||
} else if (!strcmp(property->name, "backlight")) {
|
||||
if (drm_connector_property_set_value(connector,
|
||||
property,
|
||||
value))
|
||||
goto set_prop_error;
|
||||
else {
|
||||
#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
|
||||
struct drm_psb_private *devp = encoder->dev->dev_private;
|
||||
struct backlight_device *bd = devp->backlight_device;
|
||||
if (bd) {
|
||||
bd->props.brightness = value;
|
||||
backlight_update_status(bd);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
} else if (!strcmp(property->name, "DPMS")) {
|
||||
struct drm_encoder_helper_funcs *hfuncs
|
||||
= encoder->helper_private;
|
||||
hfuncs->dpms(encoder, value);
|
||||
}
|
||||
|
||||
set_prop_done:
|
||||
return 0;
|
||||
set_prop_error:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs psb_intel_lvds_helper_funcs = {
|
||||
.dpms = psb_intel_lvds_encoder_dpms,
|
||||
.mode_fixup = psb_intel_lvds_mode_fixup,
|
||||
.prepare = psb_intel_lvds_prepare,
|
||||
.mode_set = psb_intel_lvds_mode_set,
|
||||
.commit = psb_intel_lvds_commit,
|
||||
};
|
||||
|
||||
const struct drm_connector_helper_funcs
|
||||
psb_intel_lvds_connector_helper_funcs = {
|
||||
.get_modes = psb_intel_lvds_get_modes,
|
||||
.mode_valid = psb_intel_lvds_mode_valid,
|
||||
.best_encoder = psb_intel_best_encoder,
|
||||
};
|
||||
|
||||
const struct drm_connector_funcs psb_intel_lvds_connector_funcs = {
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.save = psb_intel_lvds_save,
|
||||
.restore = psb_intel_lvds_restore,
|
||||
.detect = psb_intel_lvds_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.set_property = psb_intel_lvds_set_property,
|
||||
.destroy = psb_intel_lvds_destroy,
|
||||
};
|
||||
|
||||
|
||||
static void psb_intel_lvds_enc_destroy(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_encoder_cleanup(encoder);
|
||||
}
|
||||
|
||||
const struct drm_encoder_funcs psb_intel_lvds_enc_funcs = {
|
||||
.destroy = psb_intel_lvds_enc_destroy,
|
||||
};
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* psb_intel_lvds_init - setup LVDS connectors on this device
|
||||
* @dev: drm device
|
||||
*
|
||||
* Create the connector, register the LVDS DDC bus, and try to figure out what
|
||||
* modes we can display on the LVDS panel (if present).
|
||||
*/
|
||||
void psb_intel_lvds_init(struct drm_device *dev,
|
||||
struct psb_intel_mode_device *mode_dev)
|
||||
{
|
||||
struct psb_intel_output *psb_intel_output;
|
||||
struct psb_intel_lvds_priv *lvds_priv;
|
||||
struct drm_connector *connector;
|
||||
struct drm_encoder *encoder;
|
||||
struct drm_display_mode *scan; /* *modes, *bios_mode; */
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private;
|
||||
u32 lvds;
|
||||
int pipe;
|
||||
|
||||
psb_intel_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
|
||||
if (!psb_intel_output)
|
||||
return;
|
||||
|
||||
lvds_priv = kzalloc(sizeof(struct psb_intel_lvds_priv), GFP_KERNEL);
|
||||
if (!lvds_priv) {
|
||||
kfree(psb_intel_output);
|
||||
dev_err(dev->dev, "LVDS private allocation error\n");
|
||||
return;
|
||||
}
|
||||
|
||||
psb_intel_output->dev_priv = lvds_priv;
|
||||
|
||||
psb_intel_output->mode_dev = mode_dev;
|
||||
connector = &psb_intel_output->base;
|
||||
encoder = &psb_intel_output->enc;
|
||||
drm_connector_init(dev, &psb_intel_output->base,
|
||||
&psb_intel_lvds_connector_funcs,
|
||||
DRM_MODE_CONNECTOR_LVDS);
|
||||
|
||||
drm_encoder_init(dev, &psb_intel_output->enc,
|
||||
&psb_intel_lvds_enc_funcs,
|
||||
DRM_MODE_ENCODER_LVDS);
|
||||
|
||||
drm_mode_connector_attach_encoder(&psb_intel_output->base,
|
||||
&psb_intel_output->enc);
|
||||
psb_intel_output->type = INTEL_OUTPUT_LVDS;
|
||||
|
||||
drm_encoder_helper_add(encoder, &psb_intel_lvds_helper_funcs);
|
||||
drm_connector_helper_add(connector,
|
||||
&psb_intel_lvds_connector_helper_funcs);
|
||||
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = false;
|
||||
connector->doublescan_allowed = false;
|
||||
|
||||
/*Attach connector properties*/
|
||||
drm_connector_attach_property(connector,
|
||||
dev->mode_config.scaling_mode_property,
|
||||
DRM_MODE_SCALE_FULLSCREEN);
|
||||
drm_connector_attach_property(connector,
|
||||
dev_priv->backlight_property,
|
||||
BRIGHTNESS_MAX_LEVEL);
|
||||
|
||||
/*
|
||||
* Set up I2C bus
|
||||
* FIXME: distroy i2c_bus when exit
|
||||
*/
|
||||
psb_intel_output->i2c_bus = psb_intel_i2c_create(dev,
|
||||
GPIOB,
|
||||
"LVDSBLC_B");
|
||||
if (!psb_intel_output->i2c_bus) {
|
||||
dev_printk(KERN_ERR,
|
||||
&dev->pdev->dev, "I2C bus registration failed.\n");
|
||||
goto failed_blc_i2c;
|
||||
}
|
||||
psb_intel_output->i2c_bus->slave_addr = 0x2C;
|
||||
dev_priv->lvds_i2c_bus = psb_intel_output->i2c_bus;
|
||||
|
||||
/*
|
||||
* LVDS discovery:
|
||||
* 1) check for EDID on DDC
|
||||
* 2) check for VBT data
|
||||
* 3) check to see if LVDS is already on
|
||||
* if none of the above, no panel
|
||||
* 4) make sure lid is open
|
||||
* if closed, act like it's not there for now
|
||||
*/
|
||||
|
||||
/* Set up the DDC bus. */
|
||||
psb_intel_output->ddc_bus = psb_intel_i2c_create(dev,
|
||||
GPIOC,
|
||||
"LVDSDDC_C");
|
||||
if (!psb_intel_output->ddc_bus) {
|
||||
dev_printk(KERN_ERR, &dev->pdev->dev,
|
||||
"DDC bus registration " "failed.\n");
|
||||
goto failed_ddc;
|
||||
}
|
||||
|
||||
/*
|
||||
* Attempt to get the fixed panel mode from DDC. Assume that the
|
||||
* preferred mode is the right one.
|
||||
*/
|
||||
psb_intel_ddc_get_modes(psb_intel_output);
|
||||
list_for_each_entry(scan, &connector->probed_modes, head) {
|
||||
if (scan->type & DRM_MODE_TYPE_PREFERRED) {
|
||||
mode_dev->panel_fixed_mode =
|
||||
drm_mode_duplicate(dev, scan);
|
||||
goto out; /* FIXME: check for quirks */
|
||||
}
|
||||
}
|
||||
|
||||
/* Failed to get EDID, what about VBT? do we need this? */
|
||||
if (mode_dev->vbt_mode)
|
||||
mode_dev->panel_fixed_mode =
|
||||
drm_mode_duplicate(dev, mode_dev->vbt_mode);
|
||||
|
||||
if (!mode_dev->panel_fixed_mode)
|
||||
if (dev_priv->lfp_lvds_vbt_mode)
|
||||
mode_dev->panel_fixed_mode =
|
||||
drm_mode_duplicate(dev,
|
||||
dev_priv->lfp_lvds_vbt_mode);
|
||||
|
||||
/*
|
||||
* If we didn't get EDID, try checking if the panel is already turned
|
||||
* on. If so, assume that whatever is currently programmed is the
|
||||
* correct mode.
|
||||
*/
|
||||
lvds = REG_READ(LVDS);
|
||||
pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
|
||||
crtc = psb_intel_get_crtc_from_pipe(dev, pipe);
|
||||
|
||||
if (crtc && (lvds & LVDS_PORT_EN)) {
|
||||
mode_dev->panel_fixed_mode =
|
||||
psb_intel_crtc_mode_get(dev, crtc);
|
||||
if (mode_dev->panel_fixed_mode) {
|
||||
mode_dev->panel_fixed_mode->type |=
|
||||
DRM_MODE_TYPE_PREFERRED;
|
||||
goto out; /* FIXME: check for quirks */
|
||||
}
|
||||
}
|
||||
|
||||
/* If we still don't have a mode after all that, give up. */
|
||||
if (!mode_dev->panel_fixed_mode) {
|
||||
dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
|
||||
goto failed_find;
|
||||
}
|
||||
|
||||
/*
|
||||
* Blacklist machines with BIOSes that list an LVDS panel without
|
||||
* actually having one.
|
||||
*/
|
||||
out:
|
||||
drm_sysfs_connector_add(connector);
|
||||
return;
|
||||
|
||||
failed_find:
|
||||
if (psb_intel_output->ddc_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->ddc_bus);
|
||||
failed_ddc:
|
||||
if (psb_intel_output->i2c_bus)
|
||||
psb_intel_i2c_destroy(psb_intel_output->i2c_bus);
|
||||
failed_blc_i2c:
|
||||
drm_encoder_cleanup(encoder);
|
||||
drm_connector_cleanup(connector);
|
||||
kfree(connector);
|
||||
}
|
||||
|
77
drivers/gpu/drm/gma500/psb_intel_modes.c
Normal file
77
drivers/gpu/drm/gma500/psb_intel_modes.c
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2007 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authers: Jesse Barnes <jesse.barnes@intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/fb.h>
|
||||
#include <drm/drmP.h>
|
||||
#include "psb_intel_drv.h"
|
||||
|
||||
/**
|
||||
* psb_intel_ddc_probe
|
||||
*
|
||||
*/
|
||||
bool psb_intel_ddc_probe(struct psb_intel_output *psb_intel_output)
|
||||
{
|
||||
u8 out_buf[] = { 0x0, 0x0 };
|
||||
u8 buf[2];
|
||||
int ret;
|
||||
struct i2c_msg msgs[] = {
|
||||
{
|
||||
.addr = 0x50,
|
||||
.flags = 0,
|
||||
.len = 1,
|
||||
.buf = out_buf,
|
||||
},
|
||||
{
|
||||
.addr = 0x50,
|
||||
.flags = I2C_M_RD,
|
||||
.len = 1,
|
||||
.buf = buf,
|
||||
}
|
||||
};
|
||||
|
||||
ret = i2c_transfer(&psb_intel_output->ddc_bus->adapter, msgs, 2);
|
||||
if (ret == 2)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* psb_intel_ddc_get_modes - get modelist from monitor
|
||||
* @connector: DRM connector device to use
|
||||
*
|
||||
* Fetch the EDID information from @connector using the DDC bus.
|
||||
*/
|
||||
int psb_intel_ddc_get_modes(struct psb_intel_output *psb_intel_output)
|
||||
{
|
||||
struct edid *edid;
|
||||
int ret = 0;
|
||||
|
||||
edid =
|
||||
drm_get_edid(&psb_intel_output->base,
|
||||
&psb_intel_output->ddc_bus->adapter);
|
||||
if (edid) {
|
||||
drm_mode_connector_update_edid_property(&psb_intel_output->
|
||||
base, edid);
|
||||
ret = drm_add_edid_modes(&psb_intel_output->base, edid);
|
||||
kfree(edid);
|
||||
}
|
||||
return ret;
|
||||
}
|
1235
drivers/gpu/drm/gma500/psb_intel_reg.h
Normal file
1235
drivers/gpu/drm/gma500/psb_intel_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
1293
drivers/gpu/drm/gma500/psb_intel_sdvo.c
Normal file
1293
drivers/gpu/drm/gma500/psb_intel_sdvo.c
Normal file
File diff suppressed because it is too large
Load Diff
338
drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
Normal file
338
drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h
Normal file
@ -0,0 +1,338 @@
|
||||
/*
|
||||
* SDVO command definitions and structures.
|
||||
*
|
||||
* Copyright (c) 2008, Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*/
|
||||
|
||||
#define SDVO_OUTPUT_FIRST (0)
|
||||
#define SDVO_OUTPUT_TMDS0 (1 << 0)
|
||||
#define SDVO_OUTPUT_RGB0 (1 << 1)
|
||||
#define SDVO_OUTPUT_CVBS0 (1 << 2)
|
||||
#define SDVO_OUTPUT_SVID0 (1 << 3)
|
||||
#define SDVO_OUTPUT_YPRPB0 (1 << 4)
|
||||
#define SDVO_OUTPUT_SCART0 (1 << 5)
|
||||
#define SDVO_OUTPUT_LVDS0 (1 << 6)
|
||||
#define SDVO_OUTPUT_TMDS1 (1 << 8)
|
||||
#define SDVO_OUTPUT_RGB1 (1 << 9)
|
||||
#define SDVO_OUTPUT_CVBS1 (1 << 10)
|
||||
#define SDVO_OUTPUT_SVID1 (1 << 11)
|
||||
#define SDVO_OUTPUT_YPRPB1 (1 << 12)
|
||||
#define SDVO_OUTPUT_SCART1 (1 << 13)
|
||||
#define SDVO_OUTPUT_LVDS1 (1 << 14)
|
||||
#define SDVO_OUTPUT_LAST (14)
|
||||
|
||||
struct psb_intel_sdvo_caps {
|
||||
u8 vendor_id;
|
||||
u8 device_id;
|
||||
u8 device_rev_id;
|
||||
u8 sdvo_version_major;
|
||||
u8 sdvo_version_minor;
|
||||
unsigned int sdvo_inputs_mask:2;
|
||||
unsigned int smooth_scaling:1;
|
||||
unsigned int sharp_scaling:1;
|
||||
unsigned int up_scaling:1;
|
||||
unsigned int down_scaling:1;
|
||||
unsigned int stall_support:1;
|
||||
unsigned int pad:1;
|
||||
u16 output_flags;
|
||||
} __packed;
|
||||
|
||||
/** This matches the EDID DTD structure, more or less */
|
||||
struct psb_intel_sdvo_dtd {
|
||||
struct {
|
||||
u16 clock; /**< pixel clock, in 10kHz units */
|
||||
u8 h_active; /**< lower 8 bits (pixels) */
|
||||
u8 h_blank; /**< lower 8 bits (pixels) */
|
||||
u8 h_high; /**< upper 4 bits each h_active, h_blank */
|
||||
u8 v_active; /**< lower 8 bits (lines) */
|
||||
u8 v_blank; /**< lower 8 bits (lines) */
|
||||
u8 v_high; /**< upper 4 bits each v_active, v_blank */
|
||||
} part1;
|
||||
|
||||
struct {
|
||||
u8 h_sync_off;
|
||||
/**< lower 8 bits, from hblank start */
|
||||
u8 h_sync_width;/**< lower 8 bits (pixels) */
|
||||
/** lower 4 bits each vsync offset, vsync width */
|
||||
u8 v_sync_off_width;
|
||||
/**
|
||||
* 2 high bits of hsync offset, 2 high bits of hsync width,
|
||||
* bits 4-5 of vsync offset, and 2 high bits of vsync width.
|
||||
*/
|
||||
u8 sync_off_width_high;
|
||||
u8 dtd_flags;
|
||||
u8 sdvo_flags;
|
||||
/** bits 6-7 of vsync offset at bits 6-7 */
|
||||
u8 v_sync_off_high;
|
||||
u8 reserved;
|
||||
} part2;
|
||||
} __packed;
|
||||
|
||||
struct psb_intel_sdvo_pixel_clock_range {
|
||||
u16 min; /**< pixel clock, in 10kHz units */
|
||||
u16 max; /**< pixel clock, in 10kHz units */
|
||||
} __packed;
|
||||
|
||||
struct psb_intel_sdvo_preferred_input_timing_args {
|
||||
u16 clock;
|
||||
u16 width;
|
||||
u16 height;
|
||||
} __packed;
|
||||
|
||||
/* I2C registers for SDVO */
|
||||
#define SDVO_I2C_ARG_0 0x07
|
||||
#define SDVO_I2C_ARG_1 0x06
|
||||
#define SDVO_I2C_ARG_2 0x05
|
||||
#define SDVO_I2C_ARG_3 0x04
|
||||
#define SDVO_I2C_ARG_4 0x03
|
||||
#define SDVO_I2C_ARG_5 0x02
|
||||
#define SDVO_I2C_ARG_6 0x01
|
||||
#define SDVO_I2C_ARG_7 0x00
|
||||
#define SDVO_I2C_OPCODE 0x08
|
||||
#define SDVO_I2C_CMD_STATUS 0x09
|
||||
#define SDVO_I2C_RETURN_0 0x0a
|
||||
#define SDVO_I2C_RETURN_1 0x0b
|
||||
#define SDVO_I2C_RETURN_2 0x0c
|
||||
#define SDVO_I2C_RETURN_3 0x0d
|
||||
#define SDVO_I2C_RETURN_4 0x0e
|
||||
#define SDVO_I2C_RETURN_5 0x0f
|
||||
#define SDVO_I2C_RETURN_6 0x10
|
||||
#define SDVO_I2C_RETURN_7 0x11
|
||||
#define SDVO_I2C_VENDOR_BEGIN 0x20
|
||||
|
||||
/* Status results */
|
||||
#define SDVO_CMD_STATUS_POWER_ON 0x0
|
||||
#define SDVO_CMD_STATUS_SUCCESS 0x1
|
||||
#define SDVO_CMD_STATUS_NOTSUPP 0x2
|
||||
#define SDVO_CMD_STATUS_INVALID_ARG 0x3
|
||||
#define SDVO_CMD_STATUS_PENDING 0x4
|
||||
#define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5
|
||||
#define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6
|
||||
|
||||
/* SDVO commands, argument/result registers */
|
||||
|
||||
#define SDVO_CMD_RESET 0x01
|
||||
|
||||
/** Returns a struct psb_intel_sdvo_caps */
|
||||
#define SDVO_CMD_GET_DEVICE_CAPS 0x02
|
||||
|
||||
#define SDVO_CMD_GET_FIRMWARE_REV 0x86
|
||||
# define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0
|
||||
# define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1
|
||||
# define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2
|
||||
|
||||
/**
|
||||
* Reports which inputs are trained (managed to sync).
|
||||
*
|
||||
* Devices must have trained within 2 vsyncs of a mode change.
|
||||
*/
|
||||
#define SDVO_CMD_GET_TRAINED_INPUTS 0x03
|
||||
struct psb_intel_sdvo_get_trained_inputs_response {
|
||||
unsigned int input0_trained:1;
|
||||
unsigned int input1_trained:1;
|
||||
unsigned int pad:6;
|
||||
} __packed;
|
||||
|
||||
/** Returns a struct psb_intel_sdvo_output_flags of active outputs. */
|
||||
#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
|
||||
|
||||
/**
|
||||
* Sets the current set of active outputs.
|
||||
*
|
||||
* Takes a struct psb_intel_sdvo_output_flags.
|
||||
* Must be preceded by a SET_IN_OUT_MAP
|
||||
* on multi-output devices.
|
||||
*/
|
||||
#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
|
||||
|
||||
/**
|
||||
* Returns the current mapping of SDVO inputs to outputs on the device.
|
||||
*
|
||||
* Returns two struct psb_intel_sdvo_output_flags structures.
|
||||
*/
|
||||
#define SDVO_CMD_GET_IN_OUT_MAP 0x06
|
||||
|
||||
/**
|
||||
* Sets the current mapping of SDVO inputs to outputs on the device.
|
||||
*
|
||||
* Takes two struct i380_sdvo_output_flags structures.
|
||||
*/
|
||||
#define SDVO_CMD_SET_IN_OUT_MAP 0x07
|
||||
|
||||
/**
|
||||
* Returns a struct psb_intel_sdvo_output_flags of attached displays.
|
||||
*/
|
||||
#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
|
||||
|
||||
/**
|
||||
* Returns a struct psb_intel_sdvo_ouptut_flags of displays supporting hot plugging.
|
||||
*/
|
||||
#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
|
||||
|
||||
/**
|
||||
* Takes a struct psb_intel_sdvo_output_flags.
|
||||
*/
|
||||
#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
|
||||
|
||||
/**
|
||||
* Returns a struct psb_intel_sdvo_output_flags of displays with hot plug
|
||||
* interrupts enabled.
|
||||
*/
|
||||
#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
|
||||
|
||||
#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
|
||||
struct psb_intel_sdvo_get_interrupt_event_source_response {
|
||||
u16 interrupt_status;
|
||||
unsigned int ambient_light_interrupt:1;
|
||||
unsigned int pad:7;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Selects which input is affected by future input commands.
|
||||
*
|
||||
* Commands affected include SET_INPUT_TIMINGS_PART[12],
|
||||
* GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
|
||||
* GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
|
||||
*/
|
||||
#define SDVO_CMD_SET_TARGET_INPUT 0x10
|
||||
struct psb_intel_sdvo_set_target_input_args {
|
||||
unsigned int target_1:1;
|
||||
unsigned int pad:7;
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by
|
||||
* future output commands.
|
||||
*
|
||||
* Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
|
||||
* GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
|
||||
*/
|
||||
#define SDVO_CMD_SET_TARGET_OUTPUT 0x11
|
||||
|
||||
#define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12
|
||||
#define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13
|
||||
#define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14
|
||||
#define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15
|
||||
#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16
|
||||
#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17
|
||||
#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18
|
||||
#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19
|
||||
/* Part 1 */
|
||||
# define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0
|
||||
# define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1
|
||||
# define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2
|
||||
# define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3
|
||||
# define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4
|
||||
# define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5
|
||||
# define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6
|
||||
# define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7
|
||||
/* Part 2 */
|
||||
# define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0
|
||||
# define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1
|
||||
# define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2
|
||||
# define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3
|
||||
# define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4
|
||||
# define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
|
||||
# define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)
|
||||
# define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)
|
||||
# define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)
|
||||
# define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5
|
||||
# define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)
|
||||
# define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)
|
||||
# define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)
|
||||
# define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)
|
||||
# define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)
|
||||
# define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)
|
||||
# define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)
|
||||
# define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6
|
||||
|
||||
/**
|
||||
* Generates a DTD based on the given width, height, and flags.
|
||||
*
|
||||
* This will be supported by any device supporting scaling or interlaced
|
||||
* modes.
|
||||
*/
|
||||
#define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
|
||||
# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)
|
||||
|
||||
#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
|
||||
#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
|
||||
|
||||
/** Returns a struct psb_intel_sdvo_pixel_clock_range */
|
||||
#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
|
||||
/** Returns a struct psb_intel_sdvo_pixel_clock_range */
|
||||
#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
|
||||
|
||||
/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
|
||||
#define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f
|
||||
|
||||
/** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
|
||||
#define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20
|
||||
/** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
|
||||
#define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21
|
||||
# define SDVO_CLOCK_RATE_MULT_1X (1 << 0)
|
||||
# define SDVO_CLOCK_RATE_MULT_2X (1 << 1)
|
||||
# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
|
||||
|
||||
#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
|
||||
|
||||
#define SDVO_CMD_GET_TV_FORMAT 0x28
|
||||
|
||||
#define SDVO_CMD_SET_TV_FORMAT 0x29
|
||||
|
||||
#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
|
||||
#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
|
||||
#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
|
||||
# define SDVO_ENCODER_STATE_ON (1 << 0)
|
||||
# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
|
||||
# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
|
||||
# define SDVO_ENCODER_STATE_OFF (1 << 3)
|
||||
|
||||
#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93
|
||||
|
||||
#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
|
||||
# define SDVO_CONTROL_BUS_PROM 0x0
|
||||
# define SDVO_CONTROL_BUS_DDC1 0x1
|
||||
# define SDVO_CONTROL_BUS_DDC2 0x2
|
||||
# define SDVO_CONTROL_BUS_DDC3 0x3
|
||||
|
||||
/* SDVO Bus & SDVO Inputs wiring details*/
|
||||
/* Bit 0: Is SDVOB connected to In0 (1 = yes, 0 = no*/
|
||||
/* Bit 1: Is SDVOB connected to In1 (1 = yes, 0 = no*/
|
||||
/* Bit 2: Is SDVOC connected to In0 (1 = yes, 0 = no*/
|
||||
/* Bit 3: Is SDVOC connected to In1 (1 = yes, 0 = no*/
|
||||
#define SDVOB_IN0 0x01
|
||||
#define SDVOB_IN1 0x02
|
||||
#define SDVOC_IN0 0x04
|
||||
#define SDVOC_IN1 0x08
|
||||
|
||||
#define SDVO_DEVICE_NONE 0x00
|
||||
#define SDVO_DEVICE_CRT 0x01
|
||||
#define SDVO_DEVICE_TV 0x02
|
||||
#define SDVO_DEVICE_LVDS 0x04
|
||||
#define SDVO_DEVICE_TMDS 0x08
|
||||
|
553
drivers/gpu/drm/gma500/psb_irq.c
Normal file
553
drivers/gpu/drm/gma500/psb_irq.c
Normal file
@ -0,0 +1,553 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
|
||||
* develop this driver.
|
||||
*
|
||||
**************************************************************************/
|
||||
/*
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include "power.h"
|
||||
|
||||
/*
|
||||
* inline functions
|
||||
*/
|
||||
|
||||
static inline u32
|
||||
psb_pipestat(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return PIPEASTAT;
|
||||
if (pipe == 1)
|
||||
return PIPEBSTAT;
|
||||
if (pipe == 2)
|
||||
return PIPECSTAT;
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mid_pipe_event(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return _PSB_PIPEA_EVENT_FLAG;
|
||||
if (pipe == 1)
|
||||
return _MDFLD_PIPEB_EVENT_FLAG;
|
||||
if (pipe == 2)
|
||||
return _MDFLD_PIPEC_EVENT_FLAG;
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mid_pipe_vsync(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return _PSB_VSYNC_PIPEA_FLAG;
|
||||
if (pipe == 1)
|
||||
return _PSB_VSYNC_PIPEB_FLAG;
|
||||
if (pipe == 2)
|
||||
return _MDFLD_PIPEC_VBLANK_FLAG;
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline u32
|
||||
mid_pipeconf(int pipe)
|
||||
{
|
||||
if (pipe == 0)
|
||||
return PIPEACONF;
|
||||
if (pipe == 1)
|
||||
return PIPEBCONF;
|
||||
if (pipe == 2)
|
||||
return PIPECCONF;
|
||||
BUG();
|
||||
}
|
||||
|
||||
void
|
||||
psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
|
||||
{
|
||||
if ((dev_priv->pipestat[pipe] & mask) != mask) {
|
||||
u32 reg = psb_pipestat(pipe);
|
||||
dev_priv->pipestat[pipe] |= mask;
|
||||
/* Enable the interrupt, clear any pending status */
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 writeVal = PSB_RVDC32(reg);
|
||||
writeVal |= (mask | (mask >> 16));
|
||||
PSB_WVDC32(writeVal, reg);
|
||||
(void) PSB_RVDC32(reg);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
|
||||
{
|
||||
if ((dev_priv->pipestat[pipe] & mask) != 0) {
|
||||
u32 reg = psb_pipestat(pipe);
|
||||
dev_priv->pipestat[pipe] &= ~mask;
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 writeVal = PSB_RVDC32(reg);
|
||||
writeVal &= ~mask;
|
||||
PSB_WVDC32(writeVal, reg);
|
||||
(void) PSB_RVDC32(reg);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
|
||||
{
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 pipe_event = mid_pipe_event(pipe);
|
||||
dev_priv->vdc_irq_mask |= pipe_event;
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
|
||||
void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
|
||||
{
|
||||
if (dev_priv->pipestat[pipe] == 0) {
|
||||
if (gma_power_begin(dev_priv->dev, false)) {
|
||||
u32 pipe_event = mid_pipe_event(pipe);
|
||||
dev_priv->vdc_irq_mask &= ~pipe_event;
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
gma_power_end(dev_priv->dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Display controller interrupt handler for vsync/vblank.
|
||||
*
|
||||
*/
|
||||
static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe)
|
||||
{
|
||||
drm_handle_vblank(dev, pipe);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Display controller interrupt handler for pipe event.
|
||||
*
|
||||
*/
|
||||
#define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
|
||||
static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
|
||||
uint32_t pipe_stat_val = 0;
|
||||
uint32_t pipe_stat_reg = psb_pipestat(pipe);
|
||||
uint32_t pipe_enable = dev_priv->pipestat[pipe];
|
||||
uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
|
||||
uint32_t i = 0;
|
||||
|
||||
spin_lock(&dev_priv->irqmask_lock);
|
||||
|
||||
pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
|
||||
pipe_stat_val &= pipe_enable | pipe_status;
|
||||
pipe_stat_val &= pipe_stat_val >> 16;
|
||||
|
||||
spin_unlock(&dev_priv->irqmask_lock);
|
||||
|
||||
/* clear the 2nd level interrupt status bits */
|
||||
/**
|
||||
* FIXME: shouldn't use while loop here. However, the interrupt
|
||||
* status 'sticky' bits cannot be cleared by setting '1' to that
|
||||
* bit once...
|
||||
*/
|
||||
for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) {
|
||||
PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
|
||||
(void) PSB_RVDC32(pipe_stat_reg);
|
||||
|
||||
if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == WAIT_STATUS_CLEAR_LOOP_COUNT)
|
||||
dev_err(dev->dev,
|
||||
"%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
|
||||
__func__, PSB_RVDC32(pipe_stat_reg));
|
||||
|
||||
if (pipe_stat_val & PIPE_VBLANK_STATUS)
|
||||
mid_vblank_handler(dev, pipe);
|
||||
|
||||
if (pipe_stat_val & PIPE_TE_STATUS)
|
||||
drm_handle_vblank(dev, pipe);
|
||||
}
|
||||
|
||||
/*
|
||||
* Display controller interrupt handler.
|
||||
*/
|
||||
static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
|
||||
{
|
||||
if (vdc_stat & _PSB_PIPEA_EVENT_FLAG)
|
||||
mid_pipe_event_handler(dev, 0);
|
||||
}
|
||||
|
||||
irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
|
||||
{
|
||||
struct drm_device *dev = (struct drm_device *) arg;
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
|
||||
uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
|
||||
int handled = 0;
|
||||
|
||||
spin_lock(&dev_priv->irqmask_lock);
|
||||
|
||||
vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
|
||||
|
||||
if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
|
||||
dsp_int = 1;
|
||||
|
||||
if (vdc_stat & _PSB_IRQ_SGX_FLAG)
|
||||
sgx_int = 1;
|
||||
|
||||
vdc_stat &= dev_priv->vdc_irq_mask;
|
||||
spin_unlock(&dev_priv->irqmask_lock);
|
||||
|
||||
if (dsp_int && gma_power_is_on(dev)) {
|
||||
psb_vdc_interrupt(dev, vdc_stat);
|
||||
handled = 1;
|
||||
}
|
||||
|
||||
if (sgx_int) {
|
||||
/* Not expected - we have it masked, shut it up */
|
||||
u32 s, s2;
|
||||
s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
|
||||
s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
|
||||
PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
|
||||
PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
|
||||
/* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
|
||||
we may as well poll even if we add that ! */
|
||||
handled = 1;
|
||||
}
|
||||
|
||||
PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
|
||||
(void) PSB_RVDC32(PSB_INT_IDENTITY_R);
|
||||
DRM_READMEMORYBARRIER();
|
||||
|
||||
if (!handled)
|
||||
return IRQ_NONE;
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void psb_irq_preinstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
if (gma_power_is_on(dev))
|
||||
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
||||
if (dev->vblank_enabled[0])
|
||||
dev_priv->vdc_irq_mask |= _PSB_PIPEA_EVENT_FLAG;
|
||||
if (dev->vblank_enabled[1])
|
||||
dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
|
||||
if (dev->vblank_enabled[2])
|
||||
dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
|
||||
|
||||
/*This register is safe even if display island is off*/
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
int psb_irq_postinstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
/* This register is safe even if display island is off */
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
||||
|
||||
if (dev->vblank_enabled[0])
|
||||
psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
else
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[1])
|
||||
psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
else
|
||||
psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[2])
|
||||
psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
else
|
||||
psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psb_irq_uninstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
|
||||
|
||||
if (dev->vblank_enabled[0])
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[1])
|
||||
psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
if (dev->vblank_enabled[2])
|
||||
psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
|
||||
_PSB_IRQ_MSVDX_FLAG |
|
||||
_LNC_IRQ_TOPAZ_FLAG;
|
||||
|
||||
/* These two registers are safe even if display island is off */
|
||||
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
|
||||
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
|
||||
|
||||
wmb();
|
||||
|
||||
/* This register is safe even if display island is off */
|
||||
PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
void psb_irq_turn_on_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
u32 hist_reg;
|
||||
u32 pwm_reg;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
|
||||
PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
|
||||
PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
|
||||
| PWM_PHASEIN_INT_ENABLE,
|
||||
PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
|
||||
psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
|
||||
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
|
||||
HISTOGRAM_INT_CONTROL);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
|
||||
PWM_CONTROL_LOGIC);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
}
|
||||
|
||||
int psb_irq_enable_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
/* enable DPST */
|
||||
mid_enable_pipe_event(dev_priv, 0);
|
||||
psb_irq_turn_on_dpst(dev);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void psb_irq_turn_off_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
u32 hist_reg;
|
||||
u32 pwm_reg;
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
|
||||
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
||||
|
||||
psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
|
||||
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
|
||||
PWM_CONTROL_LOGIC);
|
||||
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
||||
|
||||
gma_power_end(dev);
|
||||
}
|
||||
}
|
||||
|
||||
int psb_irq_disable_dpst(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *) dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_disable_pipe_event(dev_priv, 0);
|
||||
psb_irq_turn_off_dpst(dev);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef PSB_FIXME
|
||||
static int psb_vblank_do_wait(struct drm_device *dev,
|
||||
unsigned int *sequence, atomic_t *counter)
|
||||
{
|
||||
unsigned int cur_vblank;
|
||||
int ret = 0;
|
||||
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
|
||||
(((cur_vblank = atomic_read(counter))
|
||||
- *sequence) <= (1 << 23)));
|
||||
*sequence = cur_vblank;
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* It is used to enable VBLANK interrupt
|
||||
*/
|
||||
int psb_enable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t pipeconf_reg = mid_pipeconf(pipe);
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
reg_val = REG_READ(pipeconf_reg);
|
||||
gma_power_end(dev);
|
||||
}
|
||||
|
||||
if (!(reg_val & PIPEACONF_ENABLE))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_enable_pipe_event(dev_priv, pipe);
|
||||
psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* It is used to disable VBLANK interrupt
|
||||
*/
|
||||
void psb_disable_vblank(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
||||
|
||||
mid_disable_pipe_event(dev_priv, pipe);
|
||||
psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
||||
|
||||
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
||||
}
|
||||
|
||||
/* Called from drm generic code, passed a 'crtc', which
|
||||
* we use as a pipe index
|
||||
*/
|
||||
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
|
||||
{
|
||||
uint32_t high_frame = PIPEAFRAMEHIGH;
|
||||
uint32_t low_frame = PIPEAFRAMEPIXEL;
|
||||
uint32_t pipeconf_reg = PIPEACONF;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
high_frame = PIPEBFRAMEHIGH;
|
||||
low_frame = PIPEBFRAMEPIXEL;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
break;
|
||||
case 2:
|
||||
high_frame = PIPECFRAMEHIGH;
|
||||
low_frame = PIPECFRAMEPIXEL;
|
||||
pipeconf_reg = PIPECCONF;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!gma_power_begin(dev, false))
|
||||
return 0;
|
||||
|
||||
reg_val = REG_READ(pipeconf_reg);
|
||||
|
||||
if (!(reg_val & PIPEACONF_ENABLE)) {
|
||||
dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
|
||||
pipe);
|
||||
goto psb_get_vblank_counter_exit;
|
||||
}
|
||||
|
||||
/*
|
||||
* High & low register fields aren't synchronized, so make sure
|
||||
* we get a low value that's stable across two reads of the high
|
||||
* register.
|
||||
*/
|
||||
do {
|
||||
high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
|
||||
PIPE_FRAME_LOW_SHIFT);
|
||||
high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
} while (high1 != high2);
|
||||
|
||||
count = (high1 << 8) | low;
|
||||
|
||||
psb_get_vblank_counter_exit:
|
||||
|
||||
gma_power_end(dev);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
45
drivers/gpu/drm/gma500/psb_irq.h
Normal file
45
drivers/gpu/drm/gma500/psb_irq.h
Normal file
@ -0,0 +1,45 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2009-2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Benjamin Defnet <benjamin.r.defnet@intel.com>
|
||||
* Rajesh Poornachandran <rajesh.poornachandran@intel.com>
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef _SYSIRQ_H_
|
||||
#define _SYSIRQ_H_
|
||||
|
||||
#include <drm/drmP.h>
|
||||
|
||||
bool sysirq_init(struct drm_device *dev);
|
||||
void sysirq_uninit(struct drm_device *dev);
|
||||
|
||||
void psb_irq_preinstall(struct drm_device *dev);
|
||||
int psb_irq_postinstall(struct drm_device *dev);
|
||||
void psb_irq_uninstall(struct drm_device *dev);
|
||||
irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
|
||||
|
||||
int psb_irq_enable_dpst(struct drm_device *dev);
|
||||
int psb_irq_disable_dpst(struct drm_device *dev);
|
||||
void psb_irq_turn_on_dpst(struct drm_device *dev);
|
||||
void psb_irq_turn_off_dpst(struct drm_device *dev);
|
||||
int psb_enable_vblank(struct drm_device *dev, int pipe);
|
||||
void psb_disable_vblank(struct drm_device *dev, int pipe);
|
||||
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe);
|
||||
|
||||
#endif /* _SYSIRQ_H_ */
|
90
drivers/gpu/drm/gma500/psb_lid.c
Normal file
90
drivers/gpu/drm/gma500/psb_lid.c
Normal file
@ -0,0 +1,90 @@
|
||||
/**************************************************************************
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
|
||||
**************************************************************************/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include "psb_drv.h"
|
||||
#include "psb_reg.h"
|
||||
#include "psb_intel_reg.h"
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
static void psb_lid_timer_func(unsigned long data)
|
||||
{
|
||||
struct drm_psb_private * dev_priv = (struct drm_psb_private *)data;
|
||||
struct drm_device *dev = (struct drm_device *)dev_priv->dev;
|
||||
struct timer_list *lid_timer = &dev_priv->lid_timer;
|
||||
unsigned long irq_flags;
|
||||
u32 *lid_state = dev_priv->lid_state;
|
||||
u32 pp_status;
|
||||
|
||||
if (readl(lid_state) == dev_priv->lid_last_state)
|
||||
goto lid_timer_schedule;
|
||||
|
||||
if ((readl(lid_state)) & 0x01) {
|
||||
/*lid state is open*/
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while ((pp_status & PP_ON) == 0);
|
||||
|
||||
/*FIXME: should be backlight level before*/
|
||||
psb_intel_lvds_set_brightness(dev, 100);
|
||||
} else {
|
||||
psb_intel_lvds_set_brightness(dev, 0);
|
||||
|
||||
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON);
|
||||
do {
|
||||
pp_status = REG_READ(PP_STATUS);
|
||||
} while ((pp_status & PP_ON) == 0);
|
||||
}
|
||||
/* printk(KERN_INFO"%s: lid: closed\n", __FUNCTION__); */
|
||||
|
||||
dev_priv->lid_last_state = readl(lid_state);
|
||||
|
||||
lid_timer_schedule:
|
||||
spin_lock_irqsave(&dev_priv->lid_lock, irq_flags);
|
||||
if (!timer_pending(lid_timer)) {
|
||||
lid_timer->expires = jiffies + PSB_LID_DELAY;
|
||||
add_timer(lid_timer);
|
||||
}
|
||||
spin_unlock_irqrestore(&dev_priv->lid_lock, irq_flags);
|
||||
}
|
||||
|
||||
void psb_lid_timer_init(struct drm_psb_private *dev_priv)
|
||||
{
|
||||
struct timer_list *lid_timer = &dev_priv->lid_timer;
|
||||
unsigned long irq_flags;
|
||||
|
||||
spin_lock_init(&dev_priv->lid_lock);
|
||||
spin_lock_irqsave(&dev_priv->lid_lock, irq_flags);
|
||||
|
||||
init_timer(lid_timer);
|
||||
|
||||
lid_timer->data = (unsigned long)dev_priv;
|
||||
lid_timer->function = psb_lid_timer_func;
|
||||
lid_timer->expires = jiffies + PSB_LID_DELAY;
|
||||
|
||||
add_timer(lid_timer);
|
||||
spin_unlock_irqrestore(&dev_priv->lid_lock, irq_flags);
|
||||
}
|
||||
|
||||
void psb_lid_timer_takedown(struct drm_psb_private *dev_priv)
|
||||
{
|
||||
del_timer_sync(&dev_priv->lid_timer);
|
||||
}
|
||||
|
582
drivers/gpu/drm/gma500/psb_reg.h
Normal file
582
drivers/gpu/drm/gma500/psb_reg.h
Normal file
@ -0,0 +1,582 @@
|
||||
/**************************************************************************
|
||||
*
|
||||
* Copyright (c) (2005-2007) Imagination Technologies Limited.
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA..
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef _PSB_REG_H_
|
||||
#define _PSB_REG_H_
|
||||
|
||||
#define PSB_CR_CLKGATECTL 0x0000
|
||||
#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
|
||||
#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
|
||||
#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
|
||||
#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
|
||||
#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
|
||||
#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
|
||||
#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
|
||||
#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
|
||||
|
||||
#define PSB_CR_CORE_ID 0x0010
|
||||
#define _PSB_CC_ID_ID_SHIFT (16)
|
||||
#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
|
||||
#define _PSB_CC_ID_CONFIG_SHIFT (0)
|
||||
#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
|
||||
|
||||
#define PSB_CR_CORE_REVISION 0x0014
|
||||
#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
|
||||
#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
|
||||
#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
|
||||
#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
|
||||
#define _PSB_CC_REVISION_MINOR_SHIFT (8)
|
||||
#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
|
||||
#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
|
||||
|
||||
#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
|
||||
|
||||
#define PSB_CR_SOFT_RESET 0x0080
|
||||
#define _PSB_CS_RESET_TSP_RESET (1 << 6)
|
||||
#define _PSB_CS_RESET_ISP_RESET (1 << 5)
|
||||
#define _PSB_CS_RESET_USE_RESET (1 << 4)
|
||||
#define _PSB_CS_RESET_TA_RESET (1 << 3)
|
||||
#define _PSB_CS_RESET_DPM_RESET (1 << 2)
|
||||
#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
|
||||
#define _PSB_CS_RESET_BIF_RESET (1 << 0)
|
||||
|
||||
#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
|
||||
|
||||
#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
|
||||
|
||||
#define PSB_CR_EVENT_STATUS2 0x0118
|
||||
|
||||
#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
|
||||
#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4)
|
||||
|
||||
#define PSB_CR_EVENT_STATUS 0x012C
|
||||
|
||||
#define PSB_CR_EVENT_HOST_ENABLE 0x0130
|
||||
|
||||
#define PSB_CR_EVENT_HOST_CLEAR 0x0134
|
||||
#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
|
||||
#define _PSB_CE_TA_DPM_FAULT (1 << 28)
|
||||
#define _PSB_CE_TWOD_COMPLETE (1 << 27)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
|
||||
#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
|
||||
#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
|
||||
#define _PSB_CE_SW_EVENT (1 << 14)
|
||||
#define _PSB_CE_TA_FINISHED (1 << 13)
|
||||
#define _PSB_CE_TA_TERMINATE (1 << 12)
|
||||
#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
|
||||
#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
|
||||
#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
|
||||
|
||||
|
||||
#define PSB_USE_OFFSET_MASK 0x0007FFFF
|
||||
#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
|
||||
#define PSB_CR_USE_CODE_BASE0 0x0A0C
|
||||
#define PSB_CR_USE_CODE_BASE1 0x0A10
|
||||
#define PSB_CR_USE_CODE_BASE2 0x0A14
|
||||
#define PSB_CR_USE_CODE_BASE3 0x0A18
|
||||
#define PSB_CR_USE_CODE_BASE4 0x0A1C
|
||||
#define PSB_CR_USE_CODE_BASE5 0x0A20
|
||||
#define PSB_CR_USE_CODE_BASE6 0x0A24
|
||||
#define PSB_CR_USE_CODE_BASE7 0x0A28
|
||||
#define PSB_CR_USE_CODE_BASE8 0x0A2C
|
||||
#define PSB_CR_USE_CODE_BASE9 0x0A30
|
||||
#define PSB_CR_USE_CODE_BASE10 0x0A34
|
||||
#define PSB_CR_USE_CODE_BASE11 0x0A38
|
||||
#define PSB_CR_USE_CODE_BASE12 0x0A3C
|
||||
#define PSB_CR_USE_CODE_BASE13 0x0A40
|
||||
#define PSB_CR_USE_CODE_BASE14 0x0A44
|
||||
#define PSB_CR_USE_CODE_BASE15 0x0A48
|
||||
#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
|
||||
#define _PSB_CUC_BASE_DM_SHIFT (25)
|
||||
#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
|
||||
#define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */
|
||||
#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
|
||||
#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
|
||||
#define _PSB_CUC_DM_VERTEX (0)
|
||||
#define _PSB_CUC_DM_PIXEL (1)
|
||||
#define _PSB_CUC_DM_RESERVED (2)
|
||||
#define _PSB_CUC_DM_EDM (3)
|
||||
|
||||
#define PSB_CR_PDS_EXEC_BASE 0x0AB8
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) /* 1MB aligned address */
|
||||
#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
|
||||
|
||||
#define PSB_CR_EVENT_KICKER 0x0AC4
|
||||
#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) /* 128-bit aligned address */
|
||||
|
||||
#define PSB_CR_EVENT_KICK 0x0AC8
|
||||
#define _PSB_CE_KICK_NOW (1 << 0)
|
||||
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
|
||||
|
||||
#define PSB_CR_BIF_CTRL 0x0C00
|
||||
#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
|
||||
#define _PSB_CB_CTRL_INVALDC (1 << 3)
|
||||
#define _PSB_CB_CTRL_FLUSH (1 << 2)
|
||||
|
||||
#define PSB_CR_BIF_INT_STAT 0x0C04
|
||||
|
||||
#define PSB_CR_BIF_FAULT 0x0C08
|
||||
#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
|
||||
#define _PSB_CBI_STAT_FAULT_SHIFT (0)
|
||||
#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
|
||||
#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
|
||||
#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
|
||||
#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
|
||||
#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
|
||||
#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
|
||||
#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
|
||||
#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
|
||||
#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
|
||||
#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
|
||||
|
||||
#define PSB_CR_BIF_BANK0 0x0C78
|
||||
#define PSB_CR_BIF_BANK1 0x0C7C
|
||||
#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
|
||||
#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
|
||||
#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
|
||||
|
||||
#define PSB_CR_2D_SOCIF 0x0E18
|
||||
#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
|
||||
#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
|
||||
#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
|
||||
|
||||
#define PSB_CR_2D_BLIT_STATUS 0x0E04
|
||||
#define _PSB_C2B_STATUS_BUSY (1 << 24)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
|
||||
#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
|
||||
|
||||
/*
|
||||
* 2D defs.
|
||||
*/
|
||||
|
||||
/*
|
||||
* 2D Slave Port Data : Block Header's Object Type
|
||||
*/
|
||||
|
||||
#define PSB_2D_CLIP_BH (0x00000000)
|
||||
#define PSB_2D_PAT_BH (0x10000000)
|
||||
#define PSB_2D_CTRL_BH (0x20000000)
|
||||
#define PSB_2D_SRC_OFF_BH (0x30000000)
|
||||
#define PSB_2D_MASK_OFF_BH (0x40000000)
|
||||
#define PSB_2D_RESERVED1_BH (0x50000000)
|
||||
#define PSB_2D_RESERVED2_BH (0x60000000)
|
||||
#define PSB_2D_FENCE_BH (0x70000000)
|
||||
#define PSB_2D_BLIT_BH (0x80000000)
|
||||
#define PSB_2D_SRC_SURF_BH (0x90000000)
|
||||
#define PSB_2D_DST_SURF_BH (0xA0000000)
|
||||
#define PSB_2D_PAT_SURF_BH (0xB0000000)
|
||||
#define PSB_2D_SRC_PAL_BH (0xC0000000)
|
||||
#define PSB_2D_PAT_PAL_BH (0xD0000000)
|
||||
#define PSB_2D_MASK_SURF_BH (0xE0000000)
|
||||
#define PSB_2D_FLUSH_BH (0xF0000000)
|
||||
|
||||
/*
|
||||
* Clip Definition block (PSB_2D_CLIP_BH)
|
||||
*/
|
||||
#define PSB_2D_CLIPCOUNT_MAX (1)
|
||||
#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
|
||||
#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CLIPCOUNT_SHIFT (0)
|
||||
/* clip rectangle min & max */
|
||||
#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_XMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_XMIN_SHIFT (0)
|
||||
/* clip rectangle offset */
|
||||
#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_CLIP_YMAX_SHIFT (12)
|
||||
#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
|
||||
#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
|
||||
#define PSB_2D_CLIP_YMIN_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Pattern Control (PSB_2D_PAT_BH)
|
||||
*/
|
||||
#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
|
||||
#define PSB_2D_PAT_HEIGHT_SHIFT (0)
|
||||
#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
|
||||
#define PSB_2D_PAT_WIDTH_SHIFT (5)
|
||||
#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
|
||||
#define PSB_2D_PAT_YSTART_SHIFT (10)
|
||||
#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
|
||||
#define PSB_2D_PAT_XSTART_SHIFT (15)
|
||||
|
||||
/*
|
||||
* 2D Control block (PSB_2D_CTRL_BH)
|
||||
*/
|
||||
/* Present Flags */
|
||||
#define PSB_2D_SRCCK_CTRL (0x00000001)
|
||||
#define PSB_2D_DSTCK_CTRL (0x00000002)
|
||||
#define PSB_2D_ALPHA_CTRL (0x00000004)
|
||||
/* Colour Key Colour (SRC/DST)*/
|
||||
#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_COL_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_COL_SHIFT (0)
|
||||
/* Colour Key Mask (SRC/DST)*/
|
||||
#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
|
||||
#define PSB_2D_CK_MASK_SHIFT (0)
|
||||
/* Alpha Control (Alpha/RGB)*/
|
||||
#define PSB_2D_GBLALPHA_MASK (0x000FF000)
|
||||
#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
|
||||
#define PSB_2D_GBLALPHA_SHIFT (12)
|
||||
#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
|
||||
#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
|
||||
#define PSB_2D_SRCALPHA_OP_SHIFT (20)
|
||||
#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
|
||||
#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
|
||||
#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
|
||||
#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
|
||||
#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
|
||||
#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
|
||||
#define PSB_2D_SRCALPHA_INVERT (0x00800000)
|
||||
#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
|
||||
#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
|
||||
#define PSB_2D_DSTALPHA_OP_SHIFT (24)
|
||||
#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
|
||||
#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
|
||||
#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
|
||||
#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
|
||||
#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT (0x08000000)
|
||||
#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
|
||||
|
||||
#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
|
||||
#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
|
||||
#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
|
||||
|
||||
/*
|
||||
*Source Offset (PSB_2D_SRC_OFF_BH)
|
||||
*/
|
||||
#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Mask Offset (PSB_2D_MASK_OFF_BH)
|
||||
*/
|
||||
#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
|
||||
#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
|
||||
#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
|
||||
|
||||
/*
|
||||
* 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
|
||||
*/
|
||||
|
||||
/*
|
||||
*Blit Rectangle (PSB_2D_BLIT_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROT_MASK (3 << 25)
|
||||
#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
|
||||
#define PSB_2D_ROT_NONE (0 << 25)
|
||||
#define PSB_2D_ROT_90DEGS (1 << 25)
|
||||
#define PSB_2D_ROT_180DEGS (2 << 25)
|
||||
#define PSB_2D_ROT_270DEGS (3 << 25)
|
||||
|
||||
#define PSB_2D_COPYORDER_MASK (3 << 23)
|
||||
#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
|
||||
#define PSB_2D_COPYORDER_TL2BR (0 << 23)
|
||||
#define PSB_2D_COPYORDER_BR2TL (1 << 23)
|
||||
#define PSB_2D_COPYORDER_TR2BL (2 << 23)
|
||||
#define PSB_2D_COPYORDER_BL2TR (3 << 23)
|
||||
|
||||
#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
|
||||
#define PSB_2D_DSTCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_DSTCK_PASS (0x00200000)
|
||||
#define PSB_2D_DSTCK_REJECT (0x00400000)
|
||||
|
||||
#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
|
||||
#define PSB_2D_SRCCK_DISABLE (0x00000000)
|
||||
#define PSB_2D_SRCCK_PASS (0x00080000)
|
||||
#define PSB_2D_SRCCK_REJECT (0x00100000)
|
||||
|
||||
#define PSB_2D_CLIP_ENABLE (0x00040000)
|
||||
|
||||
#define PSB_2D_ALPHA_ENABLE (0x00020000)
|
||||
|
||||
#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
|
||||
#define PSB_2D_PAT_MASK (0x00010000)
|
||||
#define PSB_2D_USE_PAT (0x00010000)
|
||||
#define PSB_2D_USE_FILL (0x00000000)
|
||||
/*
|
||||
* Tungsten Graphics note on rop codes: If rop A and rop B are
|
||||
* identical, the mask surface will not be read and need not be
|
||||
* set up.
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROP3B_MASK (0x0000FF00)
|
||||
#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
|
||||
#define PSB_2D_ROP3B_SHIFT (8)
|
||||
/* rop code A */
|
||||
#define PSB_2D_ROP3A_MASK (0x000000FF)
|
||||
#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
|
||||
#define PSB_2D_ROP3A_SHIFT (0)
|
||||
|
||||
#define PSB_2D_ROP4_MASK (0x0000FFFF)
|
||||
/*
|
||||
* DWORD0: (Only pass if Pattern control == Use Fill Colour)
|
||||
* Fill Colour RGBA8888
|
||||
*/
|
||||
#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
|
||||
#define PSB_2D_FILLCOLOUR_SHIFT (0)
|
||||
/*
|
||||
* DWORD1: (Always Present)
|
||||
* X Start (Dest)
|
||||
* Y Start (Dest)
|
||||
*/
|
||||
#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSTART_SHIFT (12)
|
||||
#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSTART_SHIFT (0)
|
||||
/*
|
||||
* DWORD2: (Always Present)
|
||||
* X Size (Dest)
|
||||
* Y Size (Dest)
|
||||
*/
|
||||
#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
|
||||
#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
|
||||
#define PSB_2D_DST_XSIZE_SHIFT (12)
|
||||
#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
|
||||
#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
|
||||
#define PSB_2D_DST_YSIZE_SHIFT (0)
|
||||
|
||||
/*
|
||||
* Source Surface (PSB_2D_SRC_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_SRC_1_PAL (0x00000000)
|
||||
#define PSB_2D_SRC_2_PAL (0x00008000)
|
||||
#define PSB_2D_SRC_4_PAL (0x00010000)
|
||||
#define PSB_2D_SRC_8_PAL (0x00018000)
|
||||
#define PSB_2D_SRC_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_SRC_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_SRC_332RGB (0x00030000)
|
||||
#define PSB_2D_SRC_4444ARGB (0x00038000)
|
||||
#define PSB_2D_SRC_555RGB (0x00040000)
|
||||
#define PSB_2D_SRC_1555ARGB (0x00048000)
|
||||
#define PSB_2D_SRC_565RGB (0x00050000)
|
||||
#define PSB_2D_SRC_0888ARGB (0x00058000)
|
||||
#define PSB_2D_SRC_8888ARGB (0x00060000)
|
||||
#define PSB_2D_SRC_8888UYVY (0x00068000)
|
||||
#define PSB_2D_SRC_RESERVED (0x00070000)
|
||||
#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
|
||||
|
||||
|
||||
#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_SRC_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_SRC_ADDR_SHIFT (2)
|
||||
#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Pattern Surface (PSB_2D_PAT_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_PAT_1_PAL (0x00000000)
|
||||
#define PSB_2D_PAT_2_PAL (0x00008000)
|
||||
#define PSB_2D_PAT_4_PAL (0x00010000)
|
||||
#define PSB_2D_PAT_8_PAL (0x00018000)
|
||||
#define PSB_2D_PAT_8_ALPHA (0x00020000)
|
||||
#define PSB_2D_PAT_4_ALPHA (0x00028000)
|
||||
#define PSB_2D_PAT_332RGB (0x00030000)
|
||||
#define PSB_2D_PAT_4444ARGB (0x00038000)
|
||||
#define PSB_2D_PAT_555RGB (0x00040000)
|
||||
#define PSB_2D_PAT_1555ARGB (0x00048000)
|
||||
#define PSB_2D_PAT_565RGB (0x00050000)
|
||||
#define PSB_2D_PAT_0888ARGB (0x00058000)
|
||||
#define PSB_2D_PAT_8888ARGB (0x00060000)
|
||||
|
||||
#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_PAT_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_PAT_ADDR_SHIFT (2)
|
||||
#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Destination Surface (PSB_2D_DST_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
|
||||
#define PSB_2D_DST_FORMAT_MASK (0x00078000)
|
||||
#define PSB_2D_DST_332RGB (0x00030000)
|
||||
#define PSB_2D_DST_4444ARGB (0x00038000)
|
||||
#define PSB_2D_DST_555RGB (0x00040000)
|
||||
#define PSB_2D_DST_1555ARGB (0x00048000)
|
||||
#define PSB_2D_DST_565RGB (0x00050000)
|
||||
#define PSB_2D_DST_0888ARGB (0x00058000)
|
||||
#define PSB_2D_DST_8888ARGB (0x00060000)
|
||||
#define PSB_2D_DST_8888AYUV (0x00070000)
|
||||
|
||||
#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_DST_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_DST_ADDR_SHIFT (2)
|
||||
#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Mask Surface (PSB_2D_MASK_SURF_BH)
|
||||
*/
|
||||
/*
|
||||
* WORD 0
|
||||
*/
|
||||
#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
|
||||
#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
|
||||
#define PSB_2D_MASK_STRIDE_SHIFT (0)
|
||||
/*
|
||||
* WORD 1 - Base Address
|
||||
*/
|
||||
#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
|
||||
#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
|
||||
#define PSB_2D_MASK_ADDR_SHIFT (2)
|
||||
#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
|
||||
|
||||
/*
|
||||
* Source Palette (PSB_2D_SRC_PAL_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_SRCPAL_BYTEALIGN (1024)
|
||||
|
||||
/*
|
||||
* Pattern Palette (PSB_2D_PAT_PAL_BH)
|
||||
*/
|
||||
|
||||
#define PSB_2D_PATPAL_ADDR_SHIFT (0)
|
||||
#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
|
||||
#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
|
||||
#define PSB_2D_PATPAL_BYTEALIGN (1024)
|
||||
|
||||
/*
|
||||
* Rop3 Codes (2 LS bytes)
|
||||
*/
|
||||
|
||||
#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
|
||||
#define PSB_2D_ROP3_PATCOPY (0xF0F0)
|
||||
#define PSB_2D_ROP3_WHITENESS (0xFFFF)
|
||||
#define PSB_2D_ROP3_BLACKNESS (0x0000)
|
||||
#define PSB_2D_ROP3_SRC (0xCC)
|
||||
#define PSB_2D_ROP3_PAT (0xF0)
|
||||
#define PSB_2D_ROP3_DST (0xAA)
|
||||
|
||||
/*
|
||||
* Sizes.
|
||||
*/
|
||||
|
||||
#define PSB_SCENE_HW_COOKIE_SIZE 16
|
||||
#define PSB_TA_MEM_HW_COOKIE_SIZE 16
|
||||
|
||||
/*
|
||||
* Scene stuff.
|
||||
*/
|
||||
|
||||
#define PSB_NUM_HW_SCENES 2
|
||||
|
||||
/*
|
||||
* Scheduler completion actions.
|
||||
*/
|
||||
|
||||
#define PSB_RASTER_BLOCK 0
|
||||
#define PSB_RASTER 1
|
||||
#define PSB_RETURN 2
|
||||
#define PSB_TA 3
|
||||
|
||||
/* Power management */
|
||||
#define PSB_PUNIT_PORT 0x04
|
||||
#define PSB_OSPMBA 0x78
|
||||
#define PSB_APMBA 0x7a
|
||||
#define PSB_APM_CMD 0x0
|
||||
#define PSB_APM_STS 0x04
|
||||
#define PSB_PWRGT_VID_ENC_MASK 0x30
|
||||
#define PSB_PWRGT_VID_DEC_MASK 0xc
|
||||
#define PSB_PWRGT_GL3_MASK 0xc0
|
||||
|
||||
#define PSB_PM_SSC 0x20
|
||||
#define PSB_PM_SSS 0x30
|
||||
#define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/
|
||||
#define MDFLD_PWRGT_DISPLAY_A_CNTR 0x0000000c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR) /* 0x000fc00c */
|
||||
/* Display SSS register bits are different in A0 vs. B0 */
|
||||
#define PSB_PWRGT_GFX_MASK 0x3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS 0x00000300
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS 0x00000c00
|
||||
#define PSB_PWRGT_GFX_MASK_B0 0xc3
|
||||
#define MDFLD_PWRGT_DISPLAY_A_STS_B0 0x0000000c
|
||||
#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000
|
||||
#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000
|
||||
#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
|
||||
#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */
|
||||
#endif
|
Loading…
Reference in New Issue
Block a user