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video: exynos_dp: check DP PLL Lock status

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DP PLL Lock status should be checked in order to  prevent unlocked PLL.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
This commit is contained in:
Jingoo Han 2012-04-04 15:59:24 +09:00 committed by Florian Tobias Schandinat
parent 4e0dd49d2c
commit b5cfeed6cf
1 changed files with 12 additions and 1 deletions
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13
drivers/video/exynos/exynos_dp_reg.c
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@ -271,6 +271,7 @@ void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
{
u32 reg;
int timeout_loop = 0;
exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
@ -282,9 +283,19 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
/* Power up PLL */
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED)
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
exynos_dp_set_pll_power_down(dp, 0);
while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "failed to get pll lock status\n");
return;
}
usleep_range(10, 20);
}
}
/* Enable Serdes FIFO function and Link symbol clock domain module */
reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N