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ARM: dts: imx6sx: document SION necessity of ENET1_REF_CLK1

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Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Christoph Fritz 2016-08-17 11:25:31 +02:00 committed by Shawn Guo
parent a7311c0c9a
commit b5ca028fe9
1 changed files with 14 additions and 0 deletions
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14
arch/arm/boot/dts/imx6sx-pinfunc.h
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@ -308,6 +308,20 @@
#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
/*
* SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is
* used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a
* PHY in RMII mode. This configuration is valid if:
* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set
* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset
* It seems to be a silicon bug that in this configuration ENET1_TX reference
* clock isn't provided automatically. According to i.MX6SX reference manual
* (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it
* should be the case.
* So this might have unwanted side effects for other hardware units that are
* also connected to that pin and using respective function as input (e.g.
* UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B).
*/
#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0