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drm/i915: Pass modifier instead of tiling_mode to gen4_compute_page_offset()

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In preparation for handling more than X tiling, pass the fb modifier to
gen4_compute_page_offset() instead of the obj->tiling_mode.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1452625717-9713-2-git-send-email-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2016-01-12 21:08:31 +02:00
parent 657fb5fbad
commit b5c653384f
3 changed files with 18 additions and 19 deletions
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12
drivers/gpu/drm/i915/intel_display.c
View File

@ -2449,11 +2449,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
* is assumed to be a power-of-two. */
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
unsigned int tiling_mode,
uint64_t fb_modifier,
unsigned int cpp,
unsigned int pitch)
{
if (tiling_mode != I915_TILING_NONE) {
if (fb_modifier != DRM_FORMAT_MOD_NONE) {
unsigned int tile_rows, tiles;
tile_rows = *y / 8;
@ -2769,8 +2769,8 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (INTEL_INFO(dev)->gen >= 4) {
intel_crtc->dspaddr_offset =
intel_gen4_compute_page_offset(dev_priv,
&x, &y, obj->tiling_mode,
intel_gen4_compute_page_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;
@ -2877,8 +2877,8 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
linear_offset = y * fb->pitches[0] + x * pixel_size;
intel_crtc->dspaddr_offset =
intel_gen4_compute_page_offset(dev_priv,
&x, &y, obj->tiling_mode,
intel_gen4_compute_page_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;

4
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1198,8 +1198,8 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
unsigned int tiling_mode,
unsigned int bpp,
uint64_t fb_modifier,
unsigned int cpp,
unsigned int pitch);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);

21
drivers/gpu/drm/i915/intel_sprite.c
View File

@ -422,9 +422,8 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_h--;
linear_offset = y * fb->pitches[0] + x * pixel_size;
sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
&x, &y,
obj->tiling_mode,
sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= sprsurf_offset;
@ -557,10 +556,10 @@ ivb_update_plane(struct drm_plane *plane,
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
sprsurf_offset =
intel_gen4_compute_page_offset(dev_priv,
&x, &y, obj->tiling_mode,
pixel_size, fb->pitches[0]);
sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= sprsurf_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@ -696,10 +695,10 @@ ilk_update_plane(struct drm_plane *plane,
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
dvssurf_offset =
intel_gen4_compute_page_offset(dev_priv,
&x, &y, obj->tiling_mode,
pixel_size, fb->pitches[0]);
dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= dvssurf_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {