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net: ipa: define more IPA register fields

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Define the fields for the LOCAL_PKT_PROC_CNTXT, COUNTER_CFG, and
IPA_TX_CFG IPA registers for all supported IPA versions.

Create enumerated types to identify fields for these IPA registers.
Use IPA_REG_FIELDS() to specify the field mask values defined for
these registers, for each supported version of IPA.

Use ipa_reg_bit() and ipa_reg_encode() to build up the values to be
written to these registers.  Remove the definition of the *_FMASK
symbols as well as proc_cntxt_base_addr_encoded(), because they are
no longer needed.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder 2022-09-26 17:09:26 -05:00 committed by Jakub Kicinski
parent 62b9c009a8
commit b5c35fa470
9 changed files with 146 additions and 48 deletions
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7
drivers/net/ipa/ipa_main.c
View File

@ -214,7 +214,7 @@ static void ipa_hardware_config_tx(struct ipa *ipa)
val = ioread32(ipa->reg_virt + offset);
val &= ~PA_MASK_EN_FMASK;
val &= ~ipa_reg_bit(reg, PA_MASK_EN);
iowrite32(val, ipa->reg_virt + offset);
}
@ -398,7 +398,8 @@ static void ipa_hardware_config_counter(struct ipa *ipa)
u32 val;
reg = ipa_reg(ipa, COUNTER_CFG);
val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK);
/* If defined, EOT_COAL_GRANULARITY is 0 */
val = ipa_reg_encode(reg, AGGR_GRANULARITY, granularity);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
}
@ -690,8 +691,6 @@ static void ipa_validate_build(void)
/* Aggregation granularity value can't be 0, and must fit */
BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY));
BUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) >
field_max(AGGR_GRANULARITY_FMASK));
}
/**

2
drivers/net/ipa/ipa_mem.c
View File

@ -115,7 +115,7 @@ int ipa_mem_setup(struct ipa *ipa)
offset = ipa->mem_offset + mem->offset;
reg = ipa_reg(ipa, LOCAL_PKT_PROC_CNTXT);
val = proc_cntxt_base_addr_encoded(ipa->version, offset);
val = ipa_reg_encode(reg, IPA_BASE_ADDR, offset);
iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));
return 0;

50
drivers/net/ipa/ipa_reg.h
View File

@ -289,39 +289,31 @@ enum ipa_bcr_compat {
};
/* LOCAL_PKT_PROC_CNTXT register */
/* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */
static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version,
u32 addr)
{
if (version < IPA_VERSION_4_5)
return u32_encode_bits(addr, GENMASK(16, 0));
return u32_encode_bits(addr, GENMASK(17, 0));
}
enum ipa_reg_local_pkt_proc_cntxt_field_id {
IPA_BASE_ADDR,
};
/* COUNTER_CFG register */
/* The next field is not present for IPA v3.5+ */
#define EOT_COAL_GRANULARITY_FMASK GENMASK(3, 0)
#define AGGR_GRANULARITY_FMASK GENMASK(8, 4)
enum ipa_reg_counter_cfg_field_id {
EOT_COAL_GRANULARITY, /* Not v3.5+ */
AGGR_GRANULARITY,
};
/* IPA_TX_CFG register */
/* The next three fields are not present for IPA v4.0+ */
#define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0)
#define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1)
#define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2)
/* The next six fields are present for IPA v4.0+ */
#define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2)
#define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6)
#define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10)
#define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11)
#define PA_MASK_EN_FMASK GENMASK(12, 12)
#define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13)
/* The next field is present for IPA v4.5+ */
#define DUAL_TX_ENABLE_FMASK GENMASK(17, 17)
/* The next field is present for IPA v4.2+, but not IPA v4.5 */
#define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18)
/* The next field is present for IPA v4.2 only */
#define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19)
enum ipa_reg_ipa_tx_cfg_field_id {
TX0_PREFETCH_DISABLE, /* Not v4.0+ */
TX1_PREFETCH_DISABLE, /* Not v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */
DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */
DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */
DMAW_MAX_BEATS_256_DIS, /* v4.0+ */
PA_MASK_EN, /* v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */
DUAL_TX_ENABLE, /* v4.5+ */
SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */
SSPND_PA_NO_BQ_STATE, /* v4.2 only */
};
/* FLAVOR_0 register */
#define IPA_MAX_PIPES_FMASK GENMASK(3, 0)

15
drivers/net/ipa/reg/ipa_reg-v3.1.c
View File

@ -107,13 +107,24 @@ IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c);
IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
IPA_REG(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_counter_cfg_fmask[] = {
[EOT_COAL_GRANULARITY] = GENMASK(3, 0),
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
IPA_REG_STRIDE(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020);

24
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
View File

@ -112,15 +112,33 @@ IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c);
IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
IPA_REG(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_counter_cfg_fmask[] = {
/* Bits 0-3 reserved */
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 5-31 reserved */
};
IPA_REG(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
[TX0_PREFETCH_DISABLE] = BIT(0),
[TX1_PREFETCH_DISABLE] = BIT(1),
[PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
IPA_REG(FLAVOR_0, flavor_0, 0x00000210);

22
drivers/net/ipa/reg/ipa_reg-v4.11.c
View File

@ -142,13 +142,31 @@ IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
IPA_REG(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bits 19-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
IPA_REG(FLAVOR_0, flavor_0, 0x00000210);

31
drivers/net/ipa/reg/ipa_reg-v4.2.c
View File

@ -136,15 +136,40 @@ IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
IPA_REG(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_counter_cfg_fmask[] = {
/* Bits 0-3 reserved */
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 9-31 reserved */
};
IPA_REG(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
/* Bit 17 reserved */
[SSPND_PA_NO_START_STATE] = BIT(18),
[SSPND_PA_NO_BQ_STATE] = BIT(19),
/* Bits 20-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
IPA_REG(FLAVOR_0, flavor_0, 0x00000210);

21
drivers/net/ipa/reg/ipa_reg-v4.5.c
View File

@ -136,13 +136,30 @@ IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
IPA_REG(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
/* Bits 18-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
IPA_REG(FLAVOR_0, flavor_0, 0x00000210);

22
drivers/net/ipa/reg/ipa_reg-v4.9.c
View File

@ -141,13 +141,31 @@ IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
/* Valid bits defined by ipa->available */
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
[IPA_BASE_ADDR] = GENMASK(17, 0),
/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 */
IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* Valid bits defined by ipa->available */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
IPA_REG(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
/* Bits 0-1 reserved */
[PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
[DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
[DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
[DMAW_MAX_BEATS_256_DIS] = BIT(11),
[PA_MASK_EN] = BIT(12),
[PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
[DUAL_TX_ENABLE] = BIT(17),
[SSPND_PA_NO_START_STATE] = BIT(18),
/* Bits 19-31 reserved */
};
IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
IPA_REG(FLAVOR_0, flavor_0, 0x00000210);