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usb: dwc3: add P3 in U2 SS inactive quirk

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This patch adds P3 in U2 SS inactive quirk, and some special platforms can
configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Huang Rui
2014-10-28 19:54:28 +08:00
committed by Felipe Balbi
parent 9a5b2f3167
commit b5a65c4063
4 changed files with 28 additions and 0 deletions
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3
drivers/usb/dwc3/core.h
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@@ -176,6 +176,7 @@
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
/* Global TX Fifo Size Register */
@@ -681,6 +682,7 @@ struct dwc3_scratchpad_array {
* @three_stage_setup: set if we perform a three phase setup
* @disable_scramble_quirk: set if we enable the disable scramble quirk
* @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
* @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -790,6 +792,7 @@ struct dwc3 {
unsigned disable_scramble_quirk:1;
unsigned u2exit_lfps_quirk:1;
unsigned u2ss_inp3_quirk:1;
};
/* -------------------------------------------------------------------------- */