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MIPS: pci: Make use of the BIT() macro inside the mt7620 driver

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There are a few defines that manully shift a bit. Change these to using
the BIT() macro.

Signed-off-by: John Crispin <john@phrozen.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15322/
Signed-off-by: James Hogan <jhogan@kernel.org>
This commit is contained in:
John Crispin 2017-02-20 10:29:44 +01:00 committed by James Hogan
parent 8593b18ad3
commit b54fcf6ae1
1 changed files with 6 additions and 6 deletions
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12
arch/mips/pci/pci-mt7620.c
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@ -35,11 +35,11 @@
#define PPLL_CFG1 0x9c #define PPLL_CFG1 0x9c
#define PPLL_DRV 0xa0 #define PPLL_DRV 0xa0
#define PDRV_SW_SET (1<<31) #define PDRV_SW_SET BIT(31)
#define LC_CKDRVPD (1<<19) #define LC_CKDRVPD BIT(19)
#define LC_CKDRVOHZ (1<<18) #define LC_CKDRVOHZ BIT(18)
#define LC_CKDRVHZ (1<<17) #define LC_CKDRVHZ BIT(17)
#define LC_CKTEST (1<<16) #define LC_CKTEST BIT(16)
/* PCI Bridge registers */ /* PCI Bridge registers */
#define RALINK_PCI_PCICFG_ADDR 0x00 #define RALINK_PCI_PCICFG_ADDR 0x00
@ -65,7 +65,7 @@
#define PCIEPHY0_CFG 0x90 #define PCIEPHY0_CFG 0x90
#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
#define RALINK_PCIE0_CLK_EN (1 << 26) #define RALINK_PCIE0_CLK_EN BIT(26)
#define BUSY 0x80000000 #define BUSY 0x80000000
#define WAITRETRY_MAX 10 #define WAITRETRY_MAX 10