dt-bindings: phy-mtk-tphy: make the ref clock optional
Make the ref clock optional, then we no need refer to a fixed-clock in DTS anymore when the clock of USB3 PHY comes from oscillator directly Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -34,12 +34,6 @@ Optional properties (controller (parent) node):
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Required properties (port (child) node):
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- reg : address and length of the register set for the port.
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : must contain
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"ref": 48M reference clock for HighSpeed analog phy; and 26M
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reference clock for SuperSpeed analog phy, sometimes is
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24M, 25M or 27M, depended on platform.
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- #phy-cells : should be 1 (See second example)
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- #phy-cells : should be 1 (See second example)
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cell after port phandle is phy type from:
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cell after port phandle is phy type from:
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- PHY_TYPE_USB2
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- PHY_TYPE_USB2
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@ -48,6 +42,13 @@ Required properties (port (child) node):
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- PHY_TYPE_SATA
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- PHY_TYPE_SATA
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Optional properties (PHY_TYPE_USB2 port (child) node):
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Optional properties (PHY_TYPE_USB2 port (child) node):
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : may contain
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"ref": 48M reference clock for HighSpeed anolog phy; and 26M
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reference clock for SuperSpeed anolog phy, sometimes is
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24M, 25M or 27M, depended on platform.
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- mediatek,eye-src : u32, the value of slew rate calibrate
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- mediatek,eye-src : u32, the value of slew rate calibrate
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- mediatek,eye-vrt : u32, the selection of VRT reference voltage
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- mediatek,eye-vrt : u32, the selection of VRT reference voltage
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- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
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- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
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