leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

tg3: Revise 5719 internal FIFO overflow solution

Browse Source 
Commit cf79003d59, entitled
"tg3: Fix 5719 internal FIFO overflow problem", proposed a way to solve
an internal FIFO overflow problem.  We have since discovered a slightly
better way to solve the problem.  This patch changes the code so that
the problem is contained closer to the problem source.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson 2011-01-25 15:58:47 +00:00 committed by David S. Miller
parent 26ad787962
commit b4495ed88b
2 changed files with 12 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
drivers/net/tg3.c
View File

@ -8227,8 +8227,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
val = tr32(TG3_RDMA_RSRVCTRL_REG); val = tr32(TG3_RDMA_RSRVCTRL_REG);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK; val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B; TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
} }
tw32(TG3_RDMA_RSRVCTRL_REG, tw32(TG3_RDMA_RSRVCTRL_REG,
val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
@ -13394,42 +13398,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
tp->pcie_readrq = 4096; tp->pcie_readrq = 4096;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
u16 word; tp->pcie_readrq = 2048;
pci_read_config_word(tp->pdev,
tp->pcie_cap + PCI_EXP_LNKSTA,
&word);
switch (word & PCI_EXP_LNKSTA_CLS) {
case PCI_EXP_LNKSTA_CLS_2_5GB:
word &= PCI_EXP_LNKSTA_NLW;
word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
switch (word) {
case 2:
tp->pcie_readrq = 2048;
break;
case 4:
tp->pcie_readrq = 1024;
break;
}
break;
case PCI_EXP_LNKSTA_CLS_5_0GB:
word &= PCI_EXP_LNKSTA_NLW;
word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
switch (word) {
case 1:
tp->pcie_readrq = 2048;
break;
case 2:
tp->pcie_readrq = 1024;
break;
case 4:
tp->pcie_readrq = 512;
break;
}
}
}
pcie_set_readrq(tp->pdev, tp->pcie_readrq); pcie_set_readrq(tp->pdev, tp->pcie_readrq);

4
drivers/net/tg3.h
View File

@ -1333,6 +1333,10 @@
#define TG3_RDMA_RSRVCTRL_REG 0x00004900 #define TG3_RDMA_RSRVCTRL_REG 0x00004900
#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
/* 0x4904 --> 0x4910 unused */ /* 0x4904 --> 0x4910 unused */