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ARM: mvebu: ll_set_cpu_coherent always uses the current CPU

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ll_set_cpu_coherent is always used on the current CPU, so instead of
passing the CPU id as argument, ll_set_cpu_coherent() can find it by
itself.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.com
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Gregory CLEMENT 2014-04-14 17:10:06 +02:00 committed by Jason Cooper
parent ccd6a13180
commit b41375f71a
5 changed files with 12 additions and 18 deletions
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12
arch/arm/mach-mvebu/coherency.c
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@ -61,17 +61,17 @@ static struct of_device_id of_coherency_table[] = {
}; };
/* Function defined in coherency_ll.S */ /* Function defined in coherency_ll.S */
int ll_set_cpu_coherent(unsigned int hw_cpu_id); int ll_set_cpu_coherent(void);
int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id) int set_cpu_coherent(int smp_group_id)
{ {
if (!coherency_base) { if (!coherency_base) {
pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id); pr_warn("Can't make current CPU cache coherent.\n");
pr_warn("Coherency fabric is not initialized\n"); pr_warn("Coherency fabric is not initialized\n");
return 1; return 1;
} }
return ll_set_cpu_coherent(hw_cpu_id); return ll_set_cpu_coherent();
} }
/* /*
@ -302,7 +302,7 @@ static void __init armada_370_coherency_init(struct device_node *np)
sync_cache_w(&coherency_phys_base); sync_cache_w(&coherency_phys_base);
coherency_base = of_iomap(np, 0); coherency_base = of_iomap(np, 0);
coherency_cpu_base = of_iomap(np, 1); coherency_cpu_base = of_iomap(np, 1);
set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); set_cpu_coherent(0);
} }
static void __init armada_375_380_coherency_init(struct device_node *np) static void __init armada_375_380_coherency_init(struct device_node *np)
@ -330,8 +330,6 @@ static int coherency_type(void)
/* Armada 380 coherency works only on SMP */ /* Armada 380 coherency works only on SMP */
else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp()) else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())
return type; return type;
of_node_put(np);
} }
return COHERENCY_FABRIC_TYPE_NONE; return COHERENCY_FABRIC_TYPE_NONE;

2
arch/arm/mach-mvebu/coherency.h
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@ -16,7 +16,7 @@
extern unsigned long coherency_phys_base; extern unsigned long coherency_phys_base;
int set_cpu_coherent(unsigned int cpu_id, int smp_group_id); int set_cpu_coherent(int smp_group_id);
int coherency_init(void); int coherency_init(void);
int coherency_available(void); int coherency_available(void);

10
arch/arm/mach-mvebu/coherency_ll.S
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@ -24,9 +24,7 @@
#include <asm/cp15.h> #include <asm/cp15.h>
.text .text
/*
* r0: HW CPU id
*/
ENTRY(ll_set_cpu_coherent) ENTRY(ll_set_cpu_coherent)
mrc p15, 0, r1, c1, c0, 0 mrc p15, 0, r1, c1, c0, 0
tst r1, #CR_M @ Check MMU bit enabled tst r1, #CR_M @ Check MMU bit enabled
@ -43,8 +41,10 @@ ENTRY(ll_set_cpu_coherent)
ldr r0, [r0] ldr r0, [r0]
2: 2:
/* Create bit by cpu index */ /* Create bit by cpu index */
mov r3, #(1 << 24) mrc 15, 0, r1, cr0, cr0, 5
lsl r1, r3, r1 and r1, r1, #15
mov r2, #(1 << 24)
lsl r1, r2, r1
ARM_BE8(rev r1, r1) ARM_BE8(rev r1, r1)
/* Add CPU to SMP group - Atomic */ /* Add CPU to SMP group - Atomic */

4
arch/arm/mach-mvebu/headsmp.S
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@ -31,10 +31,6 @@
ENTRY(armada_xp_secondary_startup) ENTRY(armada_xp_secondary_startup)
ARM_BE8(setend be ) @ go BE8 if entered LE ARM_BE8(setend be ) @ go BE8 if entered LE
/* Read CPU id */
mrc p15, 0, r1, c0, c0, 5
and r1, r1, #0xF
/* Add CPU to coherency fabric */ /* Add CPU to coherency fabric */
bl ll_set_cpu_coherent bl ll_set_cpu_coherent
b secondary_startup b secondary_startup

2
arch/arm/mach-mvebu/platsmp.c
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@ -103,7 +103,7 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
set_secondary_cpus_clock(); set_secondary_cpus_clock();
flush_cache_all(); flush_cache_all();
set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); set_cpu_coherent(0);
/* /*
* In order to boot the secondary CPUs we need to ensure * In order to boot the secondary CPUs we need to ensure