drm/amdgpu: lookup vbios table to check ecc capability
Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -26,6 +26,7 @@
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#include <linux/module.h>
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_atomfirmware.h"
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struct ras_ih_data {
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/* interrupt bottom half */
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@ -1327,36 +1328,21 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
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}
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/* recovery end */
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struct ras_DID_capability {
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u16 did;
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u8 rid;
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u32 capability;
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};
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static const struct ras_DID_capability supported_DID_array[] = {
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{0x66a0, 0x00, AMDGPU_RAS_BLOCK_MASK},
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{0x66a0, 0x02, AMDGPU_RAS_BLOCK_MASK},
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{0x66a1, 0x00, AMDGPU_RAS_BLOCK_MASK},
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{0x66a1, 0x01, AMDGPU_RAS_BLOCK_MASK},
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{0x66a1, 0x04, AMDGPU_RAS_BLOCK_MASK},
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{0x66a3, 0x00, AMDGPU_RAS_BLOCK_MASK},
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{0x66a7, 0x00, AMDGPU_RAS_BLOCK_MASK},
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};
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static uint32_t amdgpu_ras_check_supported(struct amdgpu_device *adev)
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{
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/* TODO need check vbios table */
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int i;
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int did = adev->pdev->device;
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int rid = adev->pdev->revision;
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uint32_t supported = 0;
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for (i = 0; i < ARRAY_SIZE(supported_DID_array); i++) {
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if (did == supported_DID_array[i].did &&
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rid == supported_DID_array[i].rid) {
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return supported_DID_array[i].capability;
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}
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if (amdgpu_ras_enable == 0 ||
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amdgpu_sriov_vf(adev) ||
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adev->asic_type != CHIP_VEGA20)
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return 0;
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if (amdgpu_atomfirmware_mem_ecc_supported(adev) ||
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amdgpu_atomfirmware_sram_ecc_supported(adev)) {
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supported = AMDGPU_RAS_BLOCK_MASK;
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}
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return 0;
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return supported & amdgpu_ras_mask;
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}
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int amdgpu_ras_init(struct amdgpu_device *adev)
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@ -1364,7 +1350,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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uint32_t supported = amdgpu_ras_check_supported(adev);
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if (con || supported == 0)
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if (con)
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return 0;
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con = kmalloc(sizeof(struct amdgpu_ras) +
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