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arm64: dts: imx8mm-nitrogen-r2: add PWMs

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Add description for the four PWMs.

Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Adrien Grassein 2021-02-23 20:16:49 +01:00 committed by Shawn Guo
parent 2b6e7da251
commit b399c13f0b
1 changed files with 51 additions and 0 deletions
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51
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
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@ -198,6 +198,33 @@
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
assigned-clocks = <&clk IMX8MM_CLK_PWM2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
/* BT */
&uart1 {
pinctrl-names = "default";
@ -354,6 +381,30 @@
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
>;
};
pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16