forked from Minki/linux
drm/amdgpu: unify VM size handling of Vega10 with older generation
One function to rule them all. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2573,21 +2573,6 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
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return ((bits + 3) / 2);
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}
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/**
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* amdgpu_vm_set_fragment_size - adjust fragment size in PTE
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*
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* @adev: amdgpu_device pointer
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* @fragment_size_default: the default fragment size if it's set auto
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*/
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void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
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uint32_t fragment_size_default)
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{
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if (amdgpu_vm_fragment_size == -1)
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adev->vm_manager.fragment_size = fragment_size_default;
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else
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adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
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}
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/**
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* amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
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*
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@ -2595,22 +2580,29 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
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* @vm_size: the default vm size if it's set auto
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*/
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
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uint32_t fragment_size_default)
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uint32_t fragment_size_default, unsigned max_level)
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{
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/* adjust vm size firstly */
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if (amdgpu_vm_size != -1)
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/* adjust vm size first, but only for two level setups for now */
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if (amdgpu_vm_size != -1 && max_level == 1)
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vm_size = amdgpu_vm_size;
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adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
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adev->vm_manager.num_level = max_level;
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/* block size depends on vm size */
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if (amdgpu_vm_block_size == -1)
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/* block size depends on vm size and hw setup*/
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if (adev->vm_manager.num_level > 1)
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/* Use fixed block_size for multi level page tables */
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adev->vm_manager.block_size = 9;
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else if (amdgpu_vm_block_size == -1)
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adev->vm_manager.block_size =
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amdgpu_vm_get_block_size(vm_size);
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else
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adev->vm_manager.block_size = amdgpu_vm_block_size;
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amdgpu_vm_set_fragment_size(adev, fragment_size_default);
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if (amdgpu_vm_fragment_size == -1)
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adev->vm_manager.fragment_size = fragment_size_default;
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else
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adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
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DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",
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vm_size, adev->vm_manager.block_size,
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@ -324,10 +324,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
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uint64_t addr);
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void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va);
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void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
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uint32_t fragment_size_default);
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
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uint32_t fragment_size_default);
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uint32_t fragment_size_default, unsigned max_level);
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int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
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bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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struct amdgpu_job *job);
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@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle)
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if (r)
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return r;
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amdgpu_vm_adjust_size(adev, 64, 9);
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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adev->mc.mc_mask = 0xffffffffffULL;
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@ -877,7 +877,6 @@ static int gmc_v6_0_sw_init(void *handle)
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle)
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* Currently set to 4GB ((1 << 20) 4k pages).
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* Max GPUVM size for cayman and SI is 40 bits.
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*/
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amdgpu_vm_adjust_size(adev, 64, 9);
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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/* Set the internal MC address mask
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* This is the max address of the GPU's
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@ -1026,7 +1026,6 @@ static int gmc_v7_0_sw_init(void *handle)
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle)
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* Currently set to 4GB ((1 << 20) 4k pages).
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* Max GPUVM size for cayman and SI is 40 bits.
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*/
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amdgpu_vm_adjust_size(adev, 64, 9);
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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/* Set the internal MC address mask
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* This is the max address of the GPU's
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@ -1123,7 +1123,6 @@ static int gmc_v8_0_sw_init(void *handle)
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* amdkfd will use VMIDs 8-15
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*/
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adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
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adev->vm_manager.num_level = 1;
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amdgpu_vm_manager_init(adev);
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/* base offset of vram pages */
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@ -769,16 +769,11 @@ static int gmc_v9_0_sw_init(void *handle)
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
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if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
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adev->vm_manager.max_pfn = 1ULL << 36;
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adev->vm_manager.block_size = 9;
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adev->vm_manager.num_level = 3;
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amdgpu_vm_set_fragment_size(adev, 9);
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} else {
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if (adev->rev_id == 0x0 || adev->rev_id == 0x1)
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amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3);
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else
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/* vm_size is 64GB for legacy 2-level page support */
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amdgpu_vm_adjust_size(adev, 64, 9);
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adev->vm_manager.num_level = 1;
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}
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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break;
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case CHIP_VEGA10:
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/* XXX Don't know how to get VRAM type yet. */
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@ -788,19 +783,12 @@ static int gmc_v9_0_sw_init(void *handle)
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* vm size is 256TB (48bit), maximum size of Vega10,
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* block size 512 (9bit)
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*/
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adev->vm_manager.max_pfn = 1ULL << 36;
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adev->vm_manager.block_size = 9;
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adev->vm_manager.num_level = 3;
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amdgpu_vm_set_fragment_size(adev, 9);
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amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3);
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break;
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default:
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break;
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}
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DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
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adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size,
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adev->vm_manager.fragment_size);
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/* This interrupt is VMC page fault.*/
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r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
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&adev->mc.vm_fault);
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