forked from Minki/linux
firewire: core: combine some repeated code
All of these CSRs have the same read/ write/ aynthing-else handling, except for CSR_PRIORITY_BUDGET which might not be implemented. The CSR_CYCLE_TIME read handler implementation accepted 4-byte-sized block write requests before this change but this is just silly; the register is only required to support quadlet read and write requests like the other r/w CSR core and Serial-Bus-dependent registers. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
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c8a94ded57
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b384cf1887
@ -1006,38 +1006,30 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
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unsigned long flags;
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switch (reg) {
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case CSR_STATE_CLEAR:
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if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_STATE_CLEAR));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_STATE_CLEAR,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_STATE_SET:
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if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_STATE_SET));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_STATE_SET,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_PRIORITY_BUDGET:
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if (!card->priority_budget_implemented) {
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rcode = RCODE_ADDRESS_ERROR;
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break;
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}
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/* else fall through */
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case CSR_NODE_IDS:
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/*
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* per IEEE 1394-2008 8.3.22.3, not IEEE 1394.1-2004 3.2.8
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* and 9.6, but interoperable with IEEE 1394.1-2004 bridges
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*/
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/* fall through */
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case CSR_STATE_CLEAR:
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case CSR_STATE_SET:
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case CSR_CYCLE_TIME:
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case CSR_BUS_TIME:
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case CSR_BUSY_TIMEOUT:
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if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_NODE_IDS));
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read_csr_reg(card, reg));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_NODE_IDS,
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card->driver->write_csr_reg(card, reg,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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@ -1078,52 +1070,6 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
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}
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break;
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case CSR_CYCLE_TIME:
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if (TCODE_IS_READ_REQUEST(tcode) && length == 4)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_CYCLE_TIME));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_CYCLE_TIME,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_BUS_TIME:
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if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_BUS_TIME));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_BUS_TIME,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_BUSY_TIMEOUT:
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if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_BUSY_TIMEOUT));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_BUSY_TIMEOUT,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_PRIORITY_BUDGET:
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if (!card->priority_budget_implemented)
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rcode = RCODE_ADDRESS_ERROR;
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else if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_PRIORITY_BUDGET));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_PRIORITY_BUDGET,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_MAINT_UTILITY:
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if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = card->maint_utility_register;
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