forked from Minki/linux
drm/amdgpu: set sched_hw_submission higher for KIQ (v3)
KIQ doesn't really use the GPU scheduler. The base drivers generally use the KIQ ring directly rather than submitting IBs. However, amdgpu_sched_hw_submission (which defaults to 2) limits the number of outstanding fences to 2. KFD uses the KIQ for TLB flushes and the 2 fence limit hurts performance when there are several KFD processes running. v2: move some expressions to one line change KIQ sched_hw_submission to at least 16 v3: bump to 256 Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -170,6 +170,16 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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unsigned irq_type)
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{
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int r;
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int sched_hw_submission = amdgpu_sched_hw_submission;
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/* Set the hw submission limit higher for KIQ because
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* it's used for a number of gfx/compute tasks by both
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* KFD and KGD which may have outstanding fences and
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* it doesn't really use the gpu scheduler anyway;
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* KIQ tasks get submitted directly to the ring.
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*/
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if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
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sched_hw_submission = max(sched_hw_submission, 256);
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if (ring->adev == NULL) {
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if (adev->num_rings >= AMDGPU_MAX_RINGS)
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@ -178,8 +188,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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ring->adev = adev;
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ring->idx = adev->num_rings++;
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adev->rings[ring->idx] = ring;
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r = amdgpu_fence_driver_init_ring(ring,
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amdgpu_sched_hw_submission);
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r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
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if (r)
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return r;
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}
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@ -218,8 +227,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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return r;
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}
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ring->ring_size = roundup_pow_of_two(max_dw * 4 *
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amdgpu_sched_hw_submission);
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ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
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ring->buf_mask = (ring->ring_size / 4) - 1;
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ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
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