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staging: brcm80211: cleanup code in source file aiutils.c

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The aiutils functions that were taken from siutils have been renamed
with proper ai_ prefix. Calling functions have been updated accordingly.

Cc: devel@linuxdriverproject.org
Cc: linux-wireless@vger.kernel.org
Cc: Brett Rudley <brudley@broadcom.com>
Cc: Henry Ptasinski <henryp@broadcom.com>
Cc: Roland Vossen <rvossen@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Arend van Spriel 2011-05-03 11:35:45 +02:00 committed by Greg Kroah-Hartman
parent 803d226ea2
commit b21c892d78
10 changed files with 418 additions and 568 deletions
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6
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c
View File

@ -14558,7 +14558,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
CHSPEC_IS40(pi->radio_chanspec)) {
regs = (d11regs_t *) si_switch_core(pi->sh->sih, D11_CORE_ID,
regs = (d11regs_t *) ai_switch_core(pi->sh->sih, D11_CORE_ID,
&origidx, &intr_val);
d11_clk_ctl_st = R_REG(&regs->clk_ctl_st);
AND_REG(&regs->clk_ctl_st,
@ -14566,7 +14566,7 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
W_REG(&regs->clk_ctl_st, d11_clk_ctl_st);
si_restore_core(pi->sh->sih, origidx, intr_val);
ai_restore_core(pi->sh->sih, origidx, intr_val);
}
pi->use_int_tx_iqlo_cal_nphy =
@ -19580,7 +19580,7 @@ void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init)
write_phy_reg(pi, 0xc8, 0x0);
write_phy_reg(pi, 0xc9, 0x0);
si_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
mc = R_REG(&pi->regs->maccontrol);
mc &= ~MCTL_GPOUT_SEL_MASK;

48
drivers/staging/brcm80211/brcmsmac/wlc_bmac.c
View File

@ -647,7 +647,7 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
* Also initialize software state that depends on the particular hardware
* we are running.
*/
wlc_hw->sih = si_attach((uint) device, regsva, bustype, btparam,
wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
&wlc_hw->vars, &wlc_hw->vars_size);
if (wlc_hw->sih == NULL) {
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
@ -698,7 +698,7 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
wlc_hw->deviceid = device;
/* set bar0 window to point at D11 core */
wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
wlc_hw->corerev = ai_corerev(wlc_hw->sih);
regs = wlc_hw->regs;
@ -712,7 +712,7 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
}
/* initialize power control registers */
si_clkctl_init(wlc_hw->sih);
ai_clkctl_init(wlc_hw->sih);
/* request fastclock and force fastclock for the rest of attach
* bring the d11 core out of reset.
@ -750,7 +750,7 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
if ((wlc_hw->sih->bustype == PCI_BUS)
&& (si_pci_war16165(wlc_hw->sih)))
&& (ai_pci_war16165(wlc_hw->sih)))
wlc->war16165 = true;
/* check device id(srom, nvram etc.) to set bands */
@ -909,10 +909,10 @@ int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
/* Match driver "down" state */
if (wlc_hw->sih->bustype == PCI_BUS)
si_pci_down(wlc_hw->sih);
ai_pci_down(wlc_hw->sih);
/* register sb interrupt callback functions */
si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
(void *)wlc_wlintrsrestore, NULL, wlc);
/* turn off pll and xtal to match driver "down" state */
@ -997,10 +997,10 @@ int wlc_bmac_detach(struct wlc_info *wlc)
/* detach interrupt sync mechanism since interrupt is disabled and per-port
* interrupt object may has been freed. this must be done before sb core switch
*/
si_deregister_intr_callback(wlc_hw->sih);
ai_deregister_intr_callback(wlc_hw->sih);
if (wlc_hw->sih->bustype == PCI_BUS)
si_pci_sleep(wlc_hw->sih);
ai_pci_sleep(wlc_hw->sih);
}
wlc_bmac_detach_dmapio(wlc_hw);
@ -1025,7 +1025,7 @@ int wlc_bmac_detach(struct wlc_info *wlc)
wlc_hw->vars = NULL;
if (wlc_hw->sih) {
si_detach(wlc_hw->sih);
ai_detach(wlc_hw->sih);
wlc_hw->sih = NULL;
}
@ -1112,7 +1112,7 @@ int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
* and force fastclock for the remainder of wlc_up().
*/
wlc_bmac_xtal(wlc_hw, ON);
si_clkctl_init(wlc_hw->sih);
ai_clkctl_init(wlc_hw->sih);
wlc_clkctl_clk(wlc_hw, CLK_FAST);
/*
@ -1122,7 +1122,7 @@ int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
coremask = (1 << wlc_hw->wlc->core->coreidx);
if (wlc_hw->sih->bustype == PCI_BUS)
si_pci_setup(wlc_hw->sih, coremask);
ai_pci_setup(wlc_hw->sih, coremask);
/*
* Need to read the hwradio status here to cover the case where the system
@ -1131,13 +1131,13 @@ int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
/* put SB PCI in down state again */
if (wlc_hw->sih->bustype == PCI_BUS)
si_pci_down(wlc_hw->sih);
ai_pci_down(wlc_hw->sih);
wlc_bmac_xtal(wlc_hw, OFF);
return -ENOMEDIUM;
}
if (wlc_hw->sih->bustype == PCI_BUS)
si_pci_up(wlc_hw->sih);
ai_pci_up(wlc_hw->sih);
/* reset the d11 core */
wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
@ -1222,7 +1222,7 @@ int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
/* turn off primary xtal and pll */
if (!wlc_hw->noreset) {
if (wlc_hw->sih->bustype == PCI_BUS)
si_pci_down(wlc_hw->sih);
ai_pci_down(wlc_hw->sih);
wlc_bmac_xtal(wlc_hw, OFF);
}
}
@ -1295,7 +1295,7 @@ static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
* then use FCA to verify mac is running fast clock
*/
wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
/* check fast clock is available (if core is not in reset) */
if (wlc_hw->forcefastclk && wlc_hw->clk)
@ -2042,7 +2042,7 @@ bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
(wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43421_CHIP_ID))
wlc_hw->regs =
(d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
(d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
0);
ai_core_reset(wlc_hw->sih, flags, resetbits);
wlc_mctrl_reset(wlc_hw);
@ -2073,18 +2073,18 @@ void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
* and force fastclock for the remainder of wlc_up().
*/
wlc_bmac_xtal(wlc_hw, ON);
si_clkctl_init(wlc_hw->sih);
ai_clkctl_init(wlc_hw->sih);
wlc_clkctl_clk(wlc_hw, CLK_FAST);
if (wlc_hw->sih->bustype == PCI_BUS) {
si_pci_fixcfg(wlc_hw->sih);
ai_pci_fixcfg(wlc_hw->sih);
/* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43421_CHIP_ID))
wlc_hw->regs =
(d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
(d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
0);
}
@ -2099,7 +2099,7 @@ void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
if (!
(wlc_hw->boardrev >= 0x1250
&& (wlc_hw->boardflags & BFL_FEM_BT)))
si_epa_4313war(wlc_hw->sih);
ai_epa_4313war(wlc_hw->sih);
}
}
@ -2390,7 +2390,7 @@ static void wlc_coreinit(struct wlc_info *wlc)
wlc_bmac_macphyclk_set(wlc_hw, ON);
/* program dynamic clock control fast powerup delay register */
wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
/* tell the ucode the corerev */
@ -2533,7 +2533,7 @@ static void wlc_gpio_init(struct wlc_info *wlc)
gm |= gc |= BOARD_GPIO_PACTRL;
/* apply to gpiocontrol register */
si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
}
static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
@ -3426,7 +3426,7 @@ void wlc_coredisable(struct wlc_hw_info *wlc_hw)
/* remove gpio controls */
if (wlc_hw->ucode_dbgsel)
si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
wlc_hw->clk = false;
ai_core_disable(wlc_hw->sih, 0);
@ -3443,7 +3443,7 @@ static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
return;
if (wlc_hw->sih)
si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
wlc_hw->sbclk = want;
if (!wlc_hw->sbclk) {

2
drivers/staging/brcm80211/brcmsmac/wlc_main.h
View File

@ -193,7 +193,7 @@ extern const u8 prio2fifo[];
((wlc->hw->clk) ? \
((R_REG(&wlc->hw->regs->maccontrol) & \
(MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN) : \
(si_deviceremoved(wlc->hw->sih)))
(ai_deviceremoved(wlc->hw->sih)))
#define WLCWLUNIT(wlc) ((wlc)->pub->unit)

74
drivers/staging/brcm80211/brcmsmac/wlc_pmu.c
View File

@ -1213,20 +1213,20 @@ u32 si_pmu_ilp_clock(si_t *sih)
{
static u32 ilpcycles_per_sec;
if (ISSIM_ENAB(sih))
if (ISSIM_ENAB(sih) || !PMUCTL_ENAB(sih))
return ILP_CLOCK;
if (ilpcycles_per_sec == 0) {
u32 start, end, delta;
u32 origidx = ai_coreidx(sih);
chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
chipcregs_t *cc = ai_setcoreidx(sih, SI_CC_IDX);
ASSERT(cc != NULL);
start = R_REG(&cc->pmutimer);
mdelay(ILP_CALC_DUR);
end = R_REG(&cc->pmutimer);
delta = end - start;
ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
}
return ilpcycles_per_sec;
@ -1276,9 +1276,9 @@ void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage)
shift = sr_cntl_shift + rc_shift;
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
~0, addr);
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
mask << shift, (voltage & mask) << shift);
}
@ -1294,7 +1294,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih)
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
switch (sih->chip) {
case BCM43224_CHIP_ID:
@ -1312,7 +1312,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih)
if (ISSIM_ENAB(sih))
delay = 70;
else {
u32 ilp = si_ilp_clock(sih);
u32 ilp = si_pmu_ilp_clock(sih);
delay =
(si_pmu_res_uptime(sih, cc, RES4329_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@ -1327,7 +1327,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih)
if (ISSIM_ENAB(sih))
delay = 70;
else {
u32 ilp = si_ilp_clock(sih);
u32 ilp = si_pmu_ilp_clock(sih);
delay =
(si_pmu_res_uptime(sih, cc, RES4336_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@ -1339,7 +1339,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih)
if (ISSIM_ENAB(sih))
delay = 70;
else {
u32 ilp = si_ilp_clock(sih);
u32 ilp = si_pmu_ilp_clock(sih);
delay =
(si_pmu_res_uptime(sih, cc, RES4330_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
@ -1351,7 +1351,7 @@ u16 si_pmu_fast_pwrup_delay(si_t *sih)
break;
}
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
return (u16) delay;
}
@ -1363,43 +1363,43 @@ void si_pmu_sprom_enable(si_t *sih, bool enable)
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
}
/* Read/write a chipcontrol reg */
u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
{
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
reg);
return si_corereg(sih, SI_CC_IDX,
return ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_data), mask, val);
}
/* Read/write a regcontrol reg */
u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
{
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
reg);
return si_corereg(sih, SI_CC_IDX,
return ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, regcontrol_data), mask, val);
}
/* Read/write a pllcontrol reg */
u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
{
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
reg);
return si_corereg(sih, SI_CC_IDX,
return ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, pllcontrol_data), mask, val);
}
/* PMU PLL update */
void si_pmu_pllupd(si_t *sih)
{
si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
}
@ -1416,7 +1416,7 @@ u32 si_pmu_alp_clock(si_t *sih)
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
switch (sih->chip) {
case BCM43224_CHIP_ID:
@ -1451,7 +1451,7 @@ u32 si_pmu_alp_clock(si_t *sih)
}
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
return clock;
}
@ -1462,7 +1462,7 @@ void si_pmu_spuravoid(si_t *sih, u8 spuravoid)
u32 tmp = 0;
/* Remember original core before switch to chipc */
cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
cc = (chipcregs_t *) ai_switch_core(sih, CC_CORE_ID, &origidx,
&intr_val);
/* force the HT off */
@ -1487,7 +1487,7 @@ void si_pmu_spuravoid(si_t *sih, u8 spuravoid)
}
/* Return to original core */
si_restore_core(sih, origidx, intr_val);
ai_restore_core(sih, origidx, intr_val);
}
/* initialize PMU */
@ -1498,7 +1498,7 @@ void si_pmu_init(si_t *sih)
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
if (sih->pmurev == 1)
AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
@ -1515,7 +1515,7 @@ void si_pmu_init(si_t *sih)
}
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
}
/* initialize PMU chip controls and other chip level stuff */
@ -1531,7 +1531,7 @@ void si_pmu_chip_init(si_t *sih)
origidx = ai_coreidx(sih);
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
}
/* initialize PMU switch/regulators */
@ -1569,7 +1569,7 @@ void si_pmu_pll_init(si_t *sih, uint xtalfreq)
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -1598,7 +1598,7 @@ void si_pmu_pll_init(si_t *sih, uint xtalfreq)
}
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
}
/* initialize PMU resources */
@ -1616,7 +1616,7 @@ void si_pmu_res_init(si_t *sih)
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -1771,7 +1771,7 @@ void si_pmu_res_init(si_t *sih)
mdelay(2);
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
}
u32 si_pmu_measure_alpclk(si_t *sih)
@ -1786,7 +1786,7 @@ u32 si_pmu_measure_alpclk(si_t *sih)
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
ASSERT(cc != NULL);
if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
@ -1824,7 +1824,7 @@ u32 si_pmu_measure_alpclk(si_t *sih)
alp_khz = 0;
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
return alp_khz;
}
@ -1837,7 +1837,7 @@ bool si_pmu_is_otp_powered(si_t *sih)
/* Remember original core before switch to chipc */
idx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -1874,7 +1874,7 @@ bool si_pmu_is_otp_powered(si_t *sih)
}
/* Return to original core */
si_setcoreidx(sih, idx);
ai_setcoreidx(sih, idx);
return st;
}
@ -1886,12 +1886,12 @@ void si_pmu_otp_power(si_t *sih, bool on)
u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
/* Don't do anything if OTP is disabled */
if (si_is_otp_disabled(sih))
if (ai_is_otp_disabled(sih))
return;
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
switch (sih->chip) {
case BCM4329_CHIP_ID:
@ -1932,5 +1932,5 @@ void si_pmu_otp_power(si_t *sih, bool on)
}
/* Return to original core */
si_setcoreidx(sih, origidx);
ai_setcoreidx(sih, origidx);
}

88
drivers/staging/brcm80211/include/aiutils.h
View File

@ -477,72 +477,72 @@ extern u32 ai_addrspacesize(si_t *sih, uint asidx);
extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
/* === exported functions === */
extern si_t *si_attach(uint pcidev, void *regs, uint bustype,
extern si_t *ai_attach(uint pcidev, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz);
extern void si_detach(si_t *sih);
extern bool si_pci_war16165(si_t *sih);
extern void ai_detach(si_t *sih);
extern bool ai_pci_war16165(si_t *sih);
extern uint si_coreid(si_t *sih);
extern uint si_corerev(si_t *sih);
extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
extern uint ai_coreid(si_t *sih);
extern uint ai_corerev(si_t *sih);
extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
uint val);
extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
extern bool si_iscoreup(si_t *sih);
extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
extern void *si_setcoreidx(si_t *sih, uint coreidx);
extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
extern void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val);
extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
extern bool ai_iscoreup(si_t *sih);
extern uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit);
extern void *ai_setcoreidx(si_t *sih, uint coreidx);
extern void *ai_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *ai_switch_core(si_t *sih, uint coreid, uint *origidx,
uint *intr_val);
extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void si_core_disable(si_t *sih, u32 bits);
extern u32 si_alp_clock(si_t *sih);
extern u32 si_ilp_clock(si_t *sih);
extern void si_pci_setup(si_t *sih, uint coremask);
extern void si_setint(si_t *sih, int siflag);
extern bool si_backplane64(si_t *sih);
extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
extern void ai_restore_core(si_t *sih, uint coreid, uint intr_val);
extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(si_t *sih, u32 bits);
extern u32 ai_alp_clock(si_t *sih);
extern u32 ai_ilp_clock(si_t *sih);
extern void ai_pci_setup(si_t *sih, uint coremask);
extern void ai_setint(si_t *sih, int siflag);
extern bool ai_backplane64(si_t *sih);
extern void ai_register_intr_callback(si_t *sih, void *intrsoff_fn,
void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg);
extern void si_deregister_intr_callback(si_t *sih);
extern void si_clkctl_init(si_t *sih);
extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
extern bool si_clkctl_cc(si_t *sih, uint mode);
extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
extern bool si_deviceremoved(si_t *sih);
extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
extern void ai_deregister_intr_callback(si_t *sih);
extern void ai_clkctl_init(si_t *sih);
extern u16 ai_clkctl_fast_pwrup_delay(si_t *sih);
extern bool ai_clkctl_cc(si_t *sih, uint mode);
extern int ai_clkctl_xtal(si_t *sih, uint what, bool on);
extern bool ai_deviceremoved(si_t *sih);
extern u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val,
u8 priority);
/* OTP status */
extern bool si_is_otp_disabled(si_t *sih);
extern bool si_is_otp_powered(si_t *sih);
extern void si_otp_power(si_t *sih, bool on);
extern bool ai_is_otp_disabled(si_t *sih);
extern bool ai_is_otp_powered(si_t *sih);
extern void ai_otp_power(si_t *sih, bool on);
/* SPROM availability */
extern bool si_is_sprom_available(si_t *sih);
extern bool ai_is_sprom_available(si_t *sih);
/*
* Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
* The returned path is NULL terminated and has trailing '/'.
* Return 0 on success, nonzero otherwise.
*/
extern int si_devpath(si_t *sih, char *path, int size);
extern int ai_devpath(si_t *sih, char *path, int size);
/* Read variable with prepending the devpath to the name */
extern char *si_getdevpathvar(si_t *sih, const char *name);
extern int si_getdevpathintvar(si_t *sih, const char *name);
extern char *ai_getdevpathvar(si_t *sih, const char *name);
extern int ai_getdevpathintvar(si_t *sih, const char *name);
extern void si_pci_sleep(si_t *sih);
extern void si_pci_down(si_t *sih);
extern void si_pci_up(si_t *sih);
extern int si_pci_fixcfg(si_t *sih);
extern void ai_pci_sleep(si_t *sih);
extern void ai_pci_down(si_t *sih);
extern void ai_pci_up(si_t *sih);
extern int ai_pci_fixcfg(si_t *sih);
extern void si_chipcontrl_epa4331(si_t *sih, bool on);
extern void ai_chipcontrl_epa4331(si_t *sih, bool on);
/* Enable Ex-PA for 4313 */
extern void si_epa_4313war(si_t *sih);
extern void ai_epa_4313war(si_t *sih);
char *si_getnvramflvar(si_t *sih, const char *name);
char *ai_getnvramflvar(si_t *sih, const char *name);
#endif /* _aiutils_h_ */

691
drivers/staging/brcm80211/util/aiutils.c
View File

File diff suppressed because it is too large Load Diff

38
drivers/staging/brcm80211/util/bcmotp.c
View File

@ -314,14 +314,12 @@ static void *ipxotp_init(si_t *sih)
return NULL;
/* Make sure OTP is not disabled */
if (si_is_otp_disabled(sih)) {
if (ai_is_otp_disabled(sih))
return NULL;
}
/* Make sure OTP is powered up */
if (!si_is_otp_powered(sih)) {
if (!ai_is_otp_powered(sih))
return NULL;
}
oi = &otpinfo;
@ -357,11 +355,11 @@ static void *ipxotp_init(si_t *sih)
/* Retrieve OTP region info */
idx = ai_coreidx(sih);
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
_ipxotp_init(oi, cc);
si_setcoreidx(sih, idx);
ai_setcoreidx(sih, idx);
return (void *)oi;
}
@ -440,13 +438,13 @@ static int ipxotp_read_region(void *oh, int region, u16 *data, uint *wlen)
}
idx = ai_coreidx(oi->sih);
cc = si_setcoreidx(oi->sih, SI_CC_IDX);
cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
/* Read the data */
for (i = 0; i < sz; i++)
data[i] = ipxotp_otpr(oh, cc, base + i);
si_setcoreidx(oi->sih, idx);
ai_setcoreidx(oi->sih, idx);
*wlen = sz;
return 0;
}
@ -618,7 +616,7 @@ static void *hndotp_init(si_t *sih)
idx = ai_coreidx(sih);
/* Check for otp */
cc = si_setcoreidx(sih, SI_CC_IDX);
cc = ai_setcoreidx(sih, SI_CC_IDX);
if (cc != NULL) {
cap = R_REG(&cc->capabilities);
if ((cap & CC_CAP_OTPSIZE) == 0) {
@ -670,7 +668,7 @@ static void *hndotp_init(si_t *sih)
}
out: /* All done */
si_setcoreidx(sih, idx);
ai_setcoreidx(sih, idx);
return ret;
}
@ -700,12 +698,12 @@ static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen)
((int)*wlen < oi->boundary / 2) ? *wlen : (uint) oi->boundary / 2;
idx = ai_coreidx(oi->sih);
cc = si_setcoreidx(oi->sih, SI_CC_IDX);
cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
for (i = 0; i < (int)*wlen; i++)
data[i] = hndotp_otpr(oh, cc, i);
si_setcoreidx(oi->sih, idx);
ai_setcoreidx(oi->sih, idx);
return 0;
}
@ -723,7 +721,7 @@ static int hndotp_nvread(void *oh, char *data, uint *len)
/* save the orig core */
idx = ai_coreidx(oi->sih);
cc = si_setcoreidx(oi->sih, SI_CC_IDX);
cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
st = hndotp_status(oh);
if (!(st & (OTP_HW_REGION | OTP_SW_REGION))) {
@ -815,7 +813,7 @@ static int hndotp_nvread(void *oh, char *data, uint *len)
out:
kfree(rawotp);
si_setcoreidx(oi->sih, idx);
ai_setcoreidx(oi->sih, idx);
return rc;
}
@ -861,9 +859,9 @@ u16 otp_read_bit(void *oh, uint offset)
{
otpinfo_t *oi = (otpinfo_t *) oh;
uint idx = ai_coreidx(oi->sih);
chipcregs_t *cc = si_setcoreidx(oi->sih, SI_CC_IDX);
chipcregs_t *cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
u16 readBit = (u16) oi->fn->read_bit(oh, cc, offset);
si_setcoreidx(oi->sih, idx);
ai_setcoreidx(oi->sih, idx);
return readBit;
}
@ -905,11 +903,11 @@ otp_read_region(si_t *sih, int region, u16 *data,
void *oh;
int err = 0;
wasup = si_is_otp_powered(sih);
wasup = ai_is_otp_powered(sih);
if (!wasup)
si_otp_power(sih, true);
ai_otp_power(sih, true);
if (!si_is_otp_powered(sih) || si_is_otp_disabled(sih)) {
if (!ai_is_otp_powered(sih) || ai_is_otp_disabled(sih)) {
err = -EPERM;
goto out;
}
@ -924,7 +922,7 @@ otp_read_region(si_t *sih, int region, u16 *data,
out:
if (!wasup)
si_otp_power(sih, false);
ai_otp_power(sih, false);
return err;
}

10
drivers/staging/brcm80211/util/bcmsrom.c
View File

@ -25,7 +25,7 @@
#include <sbchipc.h>
#include <bcmdevs.h>
#include <pcicfg.h>
#include <siutils.h>
#include <aiutils.h>
#include <bcmsrom.h>
#include <bcmsrom_tbl.h>
@ -353,7 +353,7 @@ static int initvars_flash(si_t *sih, char **base, uint len)
if (err)
goto exit;
si_devpath(sih, devpath, sizeof(devpath));
ai_devpath(sih, devpath, sizeof(devpath));
/* grab vars with the <devpath> prefix in name */
dl = strlen(devpath);
@ -595,7 +595,7 @@ static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count)
return -2;
sromwindow = (u16 *) SROM_OFFSET(sih);
if (si_is_sprom_available(sih)) {
if (ai_is_sprom_available(sih)) {
err =
sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
true);
@ -643,14 +643,14 @@ static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count)
u32 val;
val = 0;
value = si_getdevpathvar(sih, "sromrev");
value = ai_getdevpathvar(sih, "sromrev");
if (value) {
sromrev = (u8) simple_strtoul(value, NULL, 0);
flash = true;
goto varscont;
}
value = si_getnvramflvar(sih, "sromrev");
value = ai_getnvramflvar(sih, "sromrev");
if (value) {
err = 0;
goto errout;

17
drivers/staging/brcm80211/util/hnddma.c
View File

@ -22,7 +22,7 @@
#include <bcmdevs.h>
#include <hndsoc.h>
#include <bcmutils.h>
#include <siutils.h>
#include <aiutils.h>
#include <sbhnddma.h>
#include <hnddma.h>
@ -293,7 +293,8 @@ struct hnddma_pub *dma_attach(char *name, si_t *sih,
di->msg_level = msg_level ? msg_level : &dma_msg_level;
di->dma64 = ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
di->dma64 = ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
/* init dma reg pointer */
di->d64txregs = (dma64regs_t *) dmaregstx;
@ -355,11 +356,11 @@ struct hnddma_pub *dma_attach(char *name, si_t *sih,
di->dataoffsetlow = di->dataoffsetlow + SI_SDRAM_SWAPPED;
#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
/* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
if ((si_coreid(sih) == SDIOD_CORE_ID)
&& ((si_corerev(sih) > 0) && (si_corerev(sih) <= 2)))
if ((ai_coreid(sih) == SDIOD_CORE_ID)
&& ((ai_corerev(sih) > 0) && (ai_corerev(sih) <= 2)))
di->addrext = 0;
else if ((si_coreid(sih) == I2S_CORE_ID) &&
((si_corerev(sih) == 0) || (si_corerev(sih) == 1)))
else if ((ai_coreid(sih) == I2S_CORE_ID) &&
((ai_corerev(sih) == 0) || (ai_corerev(sih) == 1)))
di->addrext = 0;
else
di->addrext = _dma_isaddrext(di);
@ -1725,9 +1726,9 @@ uint dma_addrwidth(si_t *sih, void *dmaregs)
{
/* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */
/* DMA engine is 64-bit capable */
if ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) {
if ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) {
/* backplane are 64-bit capable */
if (si_backplane64(sih))
if (ai_backplane64(sih))
/* If bus is System Backplane or PCIE then we can access 64-bits */
if ((sih->bustype == SI_BUS) ||
((sih->bustype == PCI_BUS) &&

12
drivers/staging/brcm80211/util/nicpci.c
View File

@ -19,7 +19,7 @@
#include <linux/pci.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <siutils.h>
#include <aiutils.h>
#include <hndsoc.h>
#include <bcmdevs.h>
#include <sbchipc.h>
@ -382,10 +382,10 @@ static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
break;
case SI_PCIDOWN:
if (sih->buscorerev == 6) { /* turn on serdes PLL down */
si_corereg(sih, SI_CC_IDX,
ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_addr), ~0,
0);
si_corereg(sih, SI_CC_IDX,
ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_data),
~0x40, 0);
} else if (pi->pcie_pr42767) {
@ -394,10 +394,10 @@ static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
break;
case SI_PCIUP:
if (sih->buscorerev == 6) { /* turn off serdes PLL down */
si_corereg(sih, SI_CC_IDX,
ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_addr), ~0,
0);
si_corereg(sih, SI_CC_IDX,
ai_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_data),
~0x40, 0x40);
} else if (PCIE_ASPM(sih)) { /* disable clkreq */
@ -523,7 +523,7 @@ static void pcie_war_noplldown(pcicore_info_t *pi)
u16 *reg16;
/* turn off serdes PLL down */
si_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol),
ai_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol),
CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
/* clear srom shadow backdoor */