From 6f31ba17c83c184de658a78a8f84b8c843eb8e74 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 23 Nov 2018 14:45:41 +0000 Subject: [PATCH 1/8] arm64: dts: meson-axg: Enable watchdog on Meson AXG SoCs Add the watchdog node also on the AXG platforms. Signed-off-by: Carlo Caione Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 5f512c91471e..524f6ab85070 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1551,6 +1551,12 @@ status = "disabled"; }; + watchdog@f0d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0xf0d0 0x0 0x10>; + clocks = <&xtal>; + }; + pwm_ab: pwm@1b000 { compatible = "amlogic,meson-axg-ee-pwm"; reg = <0x0 0x1b000 0x0 0x20>; From ed85b3435e45a983dc24e388bfe0b1b337c6377f Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 29 Nov 2018 17:54:51 +0100 Subject: [PATCH 2/8] arm64: dts: meson-axg: remove alternate xtal There is actually no alternate xtal on any of the axg board I have seen so far. The 32k is actually generated internally, deriving from the 24MHz main xtal. Amlogic SoC also have the option to provide the 32k reference externally, through one of the AO pads, but no platform is using this ATM. Fixes: 5e395e146667 ("ARM64: dts: meson-axg: add an 32K alt aoclk") Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 524f6ab85070..cb6c222f9d0e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -53,13 +53,6 @@ status = "disabled"; }; - ao_alt_xtal: ao_alt_xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <32000000>; - clock-output-names = "ao_alt_xtal"; - #clock-cells = <0>; - }; - arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , From fa3abfb6943ef2976deda78d83788a1352963f47 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:38 +0100 Subject: [PATCH 3/8] dt-bindings: clk: meson: add ao controller clock inputs Add the clock inputs of amlogic AO clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- .../devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a880528030e..79511d7bb321 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -11,6 +11,13 @@ Required Properties: - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" +- clocks: list of clock phandle, one for each entry clock-names. +- clock-names: should contain the following: + * "xtal" : the platform xtal + * "mpeg-clk" : the main clock controller mother clock (aka clk81) + * "ext-32k-0" : external 32kHz reference #0 if any (optional) + * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) + * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) - #clock-cells: should be 1. @@ -40,8 +47,9 @@ ao_sysctrl: sys-ctrl@0 { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; -}; Example: UART controller node that consumes the clock and reset generated by the clock controller: From b1d02a84b552fde1232dc11b3c8465433fa1339d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:39 +0100 Subject: [PATCH 4/8] dt-bindings: clk: meson: add main controller clock input Add the clock input of the main clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- .../devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599566a9..a6871953bf04 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,9 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. +- clocks : list of clock phandle, one for each entry clock-names. +- clock-names : should contain the following: + * "xtal": the platform xtal - #clock-cells: should be 1. @@ -31,6 +34,8 @@ sysctrl: system-controller@0 { clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; }; }; From 16361ff23e20d2f967456fab9971152331b65117 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:40 +0100 Subject: [PATCH 5/8] arm64: dts: meson: add clock controller clock inputs Add the clock inputs of the clock controllers Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index cb6c222f9d0e..f077b2102b7e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1082,6 +1082,8 @@ clkc: clock-controller { compatible = "amlogic,axg-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; }; @@ -1327,6 +1329,8 @@ compatible = "amlogic,meson-axg-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 6796d250985a..a7b883ced0a8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -299,6 +299,8 @@ &clkc_AO { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; &efuse { @@ -334,6 +336,8 @@ clkc: clock-controller { compatible = "amlogic,gxbb-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index ed278097825b..d5c3d78aafeb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -260,6 +260,8 @@ &clkc_AO { compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; &gpio_intc { @@ -284,6 +286,8 @@ clkc: clock-controller { compatible = "amlogic,gxl-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; From de7c2fa5fc9f74a2777b3bc6397a227be755f203 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 5 Dec 2018 15:52:07 +0000 Subject: [PATCH 6/8] arm64: dts: meson-axg: s400: Enable PHY interrupt Now that the GPIO controller has been enabled also on AXG we can hook up the GPIO interrupt for the PHY. Tested-by: Jerome Brunet Signed-off-by: Carlo Caione Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 7759fda3ddfd..824eba98db2c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -357,6 +357,8 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + interrupt-parent = <&gpio_intc>; + interrupts = <98 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; }; From cbddb02e37b8bad058e1c552d4db87aa4d7c9582 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 1 Dec 2018 16:43:01 +0000 Subject: [PATCH 7/8] arm64: dts: meson-axg: Enable GPIO interrupt controller Enable the GPIO interrupt controller for the AXG SoCs. Signed-off-by: Carlo Caione Reviewed-by: Jerome Brunet Tested-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f077b2102b7e..b160bd1084de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1540,12 +1540,12 @@ }; gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-gpio-intc"; + compatible = "amlogic,meson-axg-gpio-intc", + "amlogic,meson-gpio-intc"; reg = <0x0 0xf080 0x0 0x10>; interrupt-controller; #interrupt-cells = <2>; amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; }; watchdog@f0d0 { From 8b3e6f8999f8d704fccce225b9455b3fa639d1c9 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 7 Dec 2018 10:52:30 +0000 Subject: [PATCH 8/8] arm64: dts: meson: Fix IRQ trigger type for macirq A long running stress test on a custom board shipping an AXG SoCs and a Realtek RTL8211F PHY revealed that after a few hours the connection speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time the 'macirq' (eth0) IRQ would stop being triggered at all and as consequence the GMAC IRQs never ACKed. After a painful investigation the problem seemed to be due to a wrong defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of EDGE_RISING. The change in the macirq IRQ type also solved another long standing issue affecting this SoC/PHY where EEE was causing the network connection to die after stressing it with iperf3 (even though much sooner). It's now possible to remove the 'eee-broken-1000t' quirk as well. Fixes: feb3cbea0946 ("ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage") Fixes: 6d28d577510f ("ARM64: dts: meson-axg: fix ethernet stability issue") Reviewed-by: Jerome Brunet Tested-by: Jerome Brunet Acked-by: Neil Armstrong Signed-off-by: Carlo Caione Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 1 - 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index b160bd1084de..fffd55787981 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -166,7 +166,7 @@ compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; reg = <0x0 0xff3f0000 0x0 0x10000 0x0 0xff634540 0x0 0x8>; - interrupts = ; + interrupts = ; interrupt-names = "macirq"; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index ed336c7a98a7..44c5c51ff1fa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -467,7 +467,7 @@ compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; - interrupts = ; + interrupts = ; interrupt-names = "macirq"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 00f7be6d83f7..2e1cd5e3a246 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -143,7 +143,6 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_15 */ interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index 70325b273bd2..ec09bb5792b7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -142,7 +142,6 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; - eee-broken-1000t; }; }; };