arm64: introduce basic aarch64 instruction decoding helpers
Introduce basic aarch64 instruction decoding helper aarch64_get_insn_class() and aarch64_insn_hotpatch_safe(). Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jiang Liu <liuj97@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Jiang Liu
Catalin Marinas
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77
arch/arm64/include/asm/insn.h
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77
arch/arm64/include/asm/insn.h
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/*
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* Copyright (C) 2013 Huawei Ltd.
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* Author: Jiang Liu <liuj97@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_INSN_H
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#define __ASM_INSN_H
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#include <linux/types.h>
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/*
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* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
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* Section C3.1 "A64 instruction index by encoding":
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* AArch64 main encoding table
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* Bit position
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* 28 27 26 25 Encoding Group
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* 0 0 - - Unallocated
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* 1 0 0 - Data processing, immediate
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* 1 0 1 - Branch, exception generation and system instructions
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* - 1 - 0 Loads and stores
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* - 1 0 1 Data processing - register
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* 0 1 1 1 Data processing - SIMD and floating point
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* 1 1 1 1 Data processing - SIMD and floating point
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* "-" means "don't care"
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*/
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enum aarch64_insn_encoding_class {
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AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
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AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
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AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
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AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
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AARCH64_INSN_CLS_LDST, /* Loads and stores */
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AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
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* system instructions */
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};
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enum aarch64_insn_hint_op {
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AARCH64_INSN_HINT_NOP = 0x0 << 5,
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AARCH64_INSN_HINT_YIELD = 0x1 << 5,
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AARCH64_INSN_HINT_WFE = 0x2 << 5,
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AARCH64_INSN_HINT_WFI = 0x3 << 5,
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AARCH64_INSN_HINT_SEV = 0x4 << 5,
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AARCH64_INSN_HINT_SEVL = 0x5 << 5,
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};
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#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
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static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
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{ return (code & (mask)) == (val); } \
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static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
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{ return (val); }
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__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
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__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
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__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
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__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
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__AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
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__AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
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__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
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#undef __AARCH64_INSN_FUNCS
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bool aarch64_insn_is_nop(u32 insn);
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enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
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bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
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#endif /* __ASM_INSN_H */
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@ -9,7 +9,7 @@ AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET)
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arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \
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entry-fpsimd.o process.o ptrace.o setup.o signal.o \
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sys.o stacktrace.o time.o traps.o io.o vdso.o \
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hyp-stub.o psci.o cpu_ops.o
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hyp-stub.o psci.o cpu_ops.o insn.o
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arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
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sys_compat.o
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91
arch/arm64/kernel/insn.c
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arch/arm64/kernel/insn.c
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@ -0,0 +1,91 @@
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/*
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* Copyright (C) 2013 Huawei Ltd.
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* Author: Jiang Liu <liuj97@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <asm/insn.h>
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static int aarch64_insn_encoding_class[] = {
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_UNKNOWN,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_REG,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_FPSIMD,
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AARCH64_INSN_CLS_DP_IMM,
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AARCH64_INSN_CLS_DP_IMM,
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AARCH64_INSN_CLS_BR_SYS,
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AARCH64_INSN_CLS_BR_SYS,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_REG,
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AARCH64_INSN_CLS_LDST,
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AARCH64_INSN_CLS_DP_FPSIMD,
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};
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enum aarch64_insn_encoding_class __kprobes aarch64_get_insn_class(u32 insn)
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{
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return aarch64_insn_encoding_class[(insn >> 25) & 0xf];
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}
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/* NOP is an alias of HINT */
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bool __kprobes aarch64_insn_is_nop(u32 insn)
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{
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if (!aarch64_insn_is_hint(insn))
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return false;
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switch (insn & 0xFE0) {
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case AARCH64_INSN_HINT_YIELD:
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case AARCH64_INSN_HINT_WFE:
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case AARCH64_INSN_HINT_WFI:
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case AARCH64_INSN_HINT_SEV:
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case AARCH64_INSN_HINT_SEVL:
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return false;
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default:
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return true;
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}
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}
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static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn)
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{
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if (aarch64_get_insn_class(insn) != AARCH64_INSN_CLS_BR_SYS)
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return false;
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return aarch64_insn_is_b(insn) ||
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aarch64_insn_is_bl(insn) ||
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aarch64_insn_is_svc(insn) ||
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aarch64_insn_is_hvc(insn) ||
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aarch64_insn_is_smc(insn) ||
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aarch64_insn_is_brk(insn) ||
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aarch64_insn_is_nop(insn);
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}
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/*
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* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
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* Section B2.6.5 "Concurrent modification and execution of instructions":
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* Concurrent modification and execution of instructions can lead to the
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* resulting instruction performing any behavior that can be achieved by
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* executing any sequence of instructions that can be executed from the
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* same Exception level, except where the instruction before modification
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* and the instruction after modification is a B, BL, NOP, BKPT, SVC, HVC,
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* or SMC instruction.
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*/
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bool __kprobes aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn)
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{
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return __aarch64_insn_hotpatch_safe(old_insn) &&
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__aarch64_insn_hotpatch_safe(new_insn);
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}
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