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ARM: dts: r8a73a4: Fix W=1 dtc warnings

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Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property

Move the cache-controller nodes under the cpus node, and make their
unit names and reg properties match the MPIDR values.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2016-05-20 09:09:53 +02:00 committed by Simon Horman
parent 33df275363
commit b0da45c60d
1 changed files with 18 additions and 16 deletions
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34
arch/arm/boot/dts/r8a73a4.dtsi
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@ -31,6 +31,24 @@
power-domains = <&pd_a2sl>; power-domains = <&pd_a2sl>;
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
L2_CA15: cache-controller@0 {
compatible = "cache";
reg = <0>;
clocks = <&cpg_clocks R8A73A4_CLK_Z>;
power-domains = <&pd_a3sm>;
cache-unified;
cache-level = <2>;
};
L2_CA7: cache-controller@100 {
compatible = "cache";
reg = <0x100>;
clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
power-domains = <&pd_a3km>;
cache-unified;
cache-level = <2>;
};
}; };
ptm { ptm {
@ -46,22 +64,6 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
L2_CA15: cache-controller@0 {
compatible = "cache";
clocks = <&cpg_clocks R8A73A4_CLK_Z>;
power-domains = <&pd_a3sm>;
cache-unified;
cache-level = <2>;
};
L2_CA7: cache-controller@1 {
compatible = "cache";
clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
power-domains = <&pd_a3km>;
cache-unified;
cache-level = <2>;
};
dbsc1: memory-controller@e6790000 { dbsc1: memory-controller@e6790000 {
compatible = "renesas,dbsc-r8a73a4"; compatible = "renesas,dbsc-r8a73a4";
reg = <0 0xe6790000 0 0x10000>; reg = <0 0xe6790000 0 0x10000>;