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drm/i915/icp: Add Panel Power Sequencing Support

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ICP, like BXT, has has two panel power sequencers.

v2: Simplify the code. Remove unwanted register definitions.
Make code as close to BXT style as possible. (Ville)
Also, remove the use of ICP_SECOND_PPS_BACKLIGHT for now.
Moving forward, if we are sure we need to set this register,
we can access it.

v3: Use INTEL_GEN(dev_priv), make code more readeable. (Ville)

v4 (from Paulo):
 - Coding style fixes.
 - Add a missing HAS_PCH_CNP -> gen10+ check.
 - Rebase.

v5: Use per platform checks rather than INTEL_GEN().
    v4 of this patch breaks on CoffeeLake, since CFL uses
    CNP and per platform check makes sense in that case.

v6 (from Paulo):
 - v5 was a patch on top of v4, not a new version. Now v6 is correctly
   a new version of the original patch.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180111180010.24357-6-paulo.r.zanoni@intel.com
This commit is contained in:
Anusha Srivatsa 2018-01-11 16:00:07 -02:00 committed by Paulo Zanoni
parent 4ef99abd07
commit b0d6a0f27e
1 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/drm/i915/intel_dp.c
View File

@ -794,7 +794,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
!HAS_PCH_ICP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
}
@ -5229,7 +5230,8 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
!HAS_PCH_ICP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@ -5247,7 +5249,8 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
HAS_PCH_ICP(dev_priv)) {
seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
} else {
@ -5418,7 +5421,8 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
HAS_PCH_ICP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
@ -5444,7 +5448,8 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
HAS_PCH_ICP(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@ -5452,7 +5457,8 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
(IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
(IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
HAS_PCH_ICP(dev_priv)) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}