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drm/nouveau/tegra: Avoid pulsing reset twice

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When the GPU powergate is controlled by a generic power domain provider,
the reset will automatically be asserted and deasserted as part of the
power-ungating procedure.

On some Jetson TX2 boards, doing an additional assert and deassert of
the GPU outside of the power-ungate procedure can cause the GPU to go
into a bad state where the memory interface can no longer access system
memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Thierry Reding 2019-12-09 13:00:01 +01:00 committed by Ben Skeggs
parent f1331ea8ee
commit b0b651aedb
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
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@ -52,18 +52,18 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
clk_set_rate(tdev->clk_pwr, 204000000); clk_set_rate(tdev->clk_pwr, 204000000);
udelay(10); udelay(10);
reset_control_assert(tdev->rst);
udelay(10);
if (!tdev->pdev->dev.pm_domain) { if (!tdev->pdev->dev.pm_domain) {
reset_control_assert(tdev->rst);
udelay(10);
ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
if (ret) if (ret)
goto err_clamp; goto err_clamp;
udelay(10); udelay(10);
}
reset_control_deassert(tdev->rst); reset_control_deassert(tdev->rst);
udelay(10); udelay(10);
}
return 0; return 0;